Pub Date : 1996-08-06DOI: 10.1109/HPDC.1996.546214
J. Nieplocha, R. Harrison
The performance of the Global Array shared-memory non-uniform memory-access programming model is explored on the I-WAY, wide-area network distributed supercomputer environment. The Global Array model is extended by introducing a concept of mirrored arrays. Latencies and bandwidths for remote memory access are studied, and the performance of a large application from computational chemistry is evaluated using both fully distributed and also mirrored arrays. Excellent performance can be obtained with mirroring if even modest (0.5 MB/s) network bandwidth is available.
{"title":"Shared memory NUMA programming on I-WAY","authors":"J. Nieplocha, R. Harrison","doi":"10.1109/HPDC.1996.546214","DOIUrl":"https://doi.org/10.1109/HPDC.1996.546214","url":null,"abstract":"The performance of the Global Array shared-memory non-uniform memory-access programming model is explored on the I-WAY, wide-area network distributed supercomputer environment. The Global Array model is extended by introducing a concept of mirrored arrays. Latencies and bandwidths for remote memory access are studied, and the performance of a large application from computational chemistry is evaluated using both fully distributed and also mirrored arrays. Excellent performance can be obtained with mirroring if even modest (0.5 MB/s) network bandwidth is available.","PeriodicalId":267002,"journal":{"name":"Proceedings of 5th IEEE International Symposium on High Performance Distributed Computing","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1996-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115029400","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-08-06DOI: 10.1109/HPDC.1996.546194
George Horatiu Botorog, H. Kuchen
We present Skil, an imperative language enhanced with higher order functions and currying, as well as with a polymorphic type system. The high level of Skil allows the integration of algorithmic skeletons, i.e. of higher order functions representing parallel computation patterns. At the same time, the language can be efficiently implemented. After describing a series of skeletons which work with distributed arrays, we give two examples of parallel programs implemented on the basis of skeletons, namely shortest paths in graphs and Gaussian elimination. Run time measurements show that we approach the efficiency of message passing C up to a factor between 1 and 2.5.
{"title":"Skil: an imperative language with algorithmic skeletons for efficient distributed programming","authors":"George Horatiu Botorog, H. Kuchen","doi":"10.1109/HPDC.1996.546194","DOIUrl":"https://doi.org/10.1109/HPDC.1996.546194","url":null,"abstract":"We present Skil, an imperative language enhanced with higher order functions and currying, as well as with a polymorphic type system. The high level of Skil allows the integration of algorithmic skeletons, i.e. of higher order functions representing parallel computation patterns. At the same time, the language can be efficiently implemented. After describing a series of skeletons which work with distributed arrays, we give two examples of parallel programs implemented on the basis of skeletons, namely shortest paths in graphs and Gaussian elimination. Run time measurements show that we approach the efficiency of message passing C up to a factor between 1 and 2.5.","PeriodicalId":267002,"journal":{"name":"Proceedings of 5th IEEE International Symposium on High Performance Distributed Computing","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1996-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126459476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-08-06DOI: 10.1109/HPDC.1996.546174
Jonathan Robinson, S. Russ, B. Flachs, Bjørn Heckel
In order to use networks of workstations in parallel processing applications, several schemes have been devised to allow processes on different, possibly heterogeneous, platforms to communicate with one another. The Message-Passing Interface (MPI) is one such scheme that allows for message-passing across different architectures. The MPI specification does not make provisions for the migration of a process between machines. This paper describes the work required to modify, an MPI implementation to allow for task migration. It also describes "Hector", our heterogeneous computing task allocator that is used to migrate tasks automatically and improve the overall performance of a parallel program.
{"title":"A task migration implementation of the Message-Passing Interface","authors":"Jonathan Robinson, S. Russ, B. Flachs, Bjørn Heckel","doi":"10.1109/HPDC.1996.546174","DOIUrl":"https://doi.org/10.1109/HPDC.1996.546174","url":null,"abstract":"In order to use networks of workstations in parallel processing applications, several schemes have been devised to allow processes on different, possibly heterogeneous, platforms to communicate with one another. The Message-Passing Interface (MPI) is one such scheme that allows for message-passing across different architectures. The MPI specification does not make provisions for the migration of a process between machines. This paper describes the work required to modify, an MPI implementation to allow for task migration. It also describes \"Hector\", our heterogeneous computing task allocator that is used to migrate tasks automatically and improve the overall performance of a parallel program.","PeriodicalId":267002,"journal":{"name":"Proceedings of 5th IEEE International Symposium on High Performance Distributed Computing","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1996-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126339772","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-08-06DOI: 10.1109/HPDC.1996.546208
M. Chan, G. Pacifici, R. Stadler
Outlines a methodology for developing network control systems which allows for an evaluation of the dynamic behavior and overall performance at an early stage of the development process. Our approach is to build a software prototype which is designed according to the architecture under consideration and runs the intended control algorithms. The functional and dynamic properties of this prototype are tested and evaluated on an emulation platform that we built for this purpose. By providing support for real-time visualization and interactive emulation, this platform can be used to study multimedia networks in various scenarios, such as different load patterns, network sizes and management operations. The current implementation runs on a KSR-1 and an SP2 parallel processor, which are connected to a graphics workstation via ATM links. We use the platform in several projects, one of which aims at developing an architecture for managing multimedia network services.
{"title":"Prototyping network architectures on a supercomputer","authors":"M. Chan, G. Pacifici, R. Stadler","doi":"10.1109/HPDC.1996.546208","DOIUrl":"https://doi.org/10.1109/HPDC.1996.546208","url":null,"abstract":"Outlines a methodology for developing network control systems which allows for an evaluation of the dynamic behavior and overall performance at an early stage of the development process. Our approach is to build a software prototype which is designed according to the architecture under consideration and runs the intended control algorithms. The functional and dynamic properties of this prototype are tested and evaluated on an emulation platform that we built for this purpose. By providing support for real-time visualization and interactive emulation, this platform can be used to study multimedia networks in various scenarios, such as different load patterns, network sizes and management operations. The current implementation runs on a KSR-1 and an SP2 parallel processor, which are connected to a graphics workstation via ATM links. We use the platform in several projects, one of which aims at developing an architecture for managing multimedia network services.","PeriodicalId":267002,"journal":{"name":"Proceedings of 5th IEEE International Symposium on High Performance Distributed Computing","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1996-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126439210","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-08-06DOI: 10.1109/HPDC.1996.546183
G. Cooperman
The goal of this work is to simplify parallel application development, and thus ease the learning barriers faced by non-experts. It is especially useful where there is little data-parallelism to be recognized by a compiler. The applications programmer need learn the intricacies of only one primary subroutine in order to get the full benefits of the parallel interface. The applications programmer defines a high level concept, the task, that depends only on his application, and not on any particular parallel library. The task is defined by its three phases: (a) the task input, (b) sequential code to execute the task, and (c) any modifications of global variables that occur as a result of the task. In particular, side effects (which change global variable values) must not occur in phase (b). Forcing the user to re-organize his computation in these terms allows us to present the applications programmer with a single global environment visible to all processors (whether on a SMP or a NOW architecture), in the context of a masterslave architecture. Both a shared memory implementation (running on an SGI or SUN Solaris architecture) and a NOW memory implementation (running on top of MPI) are described. The implementations were tested by a naive program for integer factorization, and by a more sophisticated Todd-Coxeter coset enumeration. Integer factorization was chosen so as to exercise the major features of TOP-C in an unambiguous context.
{"title":"TOP-C: a task-oriented parallel C interface","authors":"G. Cooperman","doi":"10.1109/HPDC.1996.546183","DOIUrl":"https://doi.org/10.1109/HPDC.1996.546183","url":null,"abstract":"The goal of this work is to simplify parallel application development, and thus ease the learning barriers faced by non-experts. It is especially useful where there is little data-parallelism to be recognized by a compiler. The applications programmer need learn the intricacies of only one primary subroutine in order to get the full benefits of the parallel interface. The applications programmer defines a high level concept, the task, that depends only on his application, and not on any particular parallel library. The task is defined by its three phases: (a) the task input, (b) sequential code to execute the task, and (c) any modifications of global variables that occur as a result of the task. In particular, side effects (which change global variable values) must not occur in phase (b). Forcing the user to re-organize his computation in these terms allows us to present the applications programmer with a single global environment visible to all processors (whether on a SMP or a NOW architecture), in the context of a masterslave architecture. Both a shared memory implementation (running on an SGI or SUN Solaris architecture) and a NOW memory implementation (running on top of MPI) are described. The implementations were tested by a naive program for integer factorization, and by a more sophisticated Todd-Coxeter coset enumeration. Integer factorization was chosen so as to exercise the major features of TOP-C in an unambiguous context.","PeriodicalId":267002,"journal":{"name":"Proceedings of 5th IEEE International Symposium on High Performance Distributed Computing","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1996-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121378104","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-08-06DOI: 10.1109/HPDC.1996.546202
M. Chandy, Eve M. SchoolerComputer
Proposes a framework for the systematic design of directory-based distributed applications. We evaluate a space of directory designs using our framework. We present a case study consisting of design, implementation and analysis of directories for a multicast application. Our framework is based on a model that extends the formal concept of process knowledge in distributed systems. This concept is used informally in phrases such as "process p knows when it is in state s that process q is active". We show that this definition of knowledge is too strong for many distributed applications, including directory design. We propose a weaker concept: estimation. We describe the meaning of phrases of the form: "process p in state s estimates with probability 0.9 that process q is active". We specify directory design as an optimization problem with the objective function of maximizing estimation probabilities, and with constraints on the amount of bandwidth, computation and storage used. We show how this specification helps in a systematic analysts of alternative directory designs.
{"title":"Designing directories in distributed systems: a systematic framework","authors":"M. Chandy, Eve M. SchoolerComputer","doi":"10.1109/HPDC.1996.546202","DOIUrl":"https://doi.org/10.1109/HPDC.1996.546202","url":null,"abstract":"Proposes a framework for the systematic design of directory-based distributed applications. We evaluate a space of directory designs using our framework. We present a case study consisting of design, implementation and analysis of directories for a multicast application. Our framework is based on a model that extends the formal concept of process knowledge in distributed systems. This concept is used informally in phrases such as \"process p knows when it is in state s that process q is active\". We show that this definition of knowledge is too strong for many distributed applications, including directory design. We propose a weaker concept: estimation. We describe the meaning of phrases of the form: \"process p in state s estimates with probability 0.9 that process q is active\". We specify directory design as an optimization problem with the objective function of maximizing estimation probabilities, and with constraints on the amount of bandwidth, computation and storage used. We show how this specification helps in a systematic analysts of alternative directory designs.","PeriodicalId":267002,"journal":{"name":"Proceedings of 5th IEEE International Symposium on High Performance Distributed Computing","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1996-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115449251","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-08-06DOI: 10.1109/HPDC.1996.546226
M. Lewis, A. Grimshaw
The Legion project at the University of Virginia is an architecture for designing and building system services that provide the illusion of a single virtual machine to users, a virtual machine that provides secure shared object and shared name spaces, application adjustable fault tolerance, improved response time, and greater throughput. Legion targets wide area assemblies of workstations, supercomputers, and parallel supercomputers. Legion tackles problems not solved by existing workstation based parallel processing tools; the system will enable fault tolerance, wide area parallel processing, interoperability, heterogeneity, a single global name space, protection, security, efficient scheduling, and comprehensive resource management. The paper describes the core Legion object model, which specifies the composition and functionality of Legion's core objects-those objects that cooperate to create, locate, manage, and remove objects in the Legion system. The object model facilitates a flexible extensible implementation, provides a single global name space, grants site autonomy to participating organizations, and scales to millions of sites and trillions of objects.
弗吉尼亚大学(University of Virginia)的Legion项目是一个设计和构建系统服务的体系结构，该体系结构为用户提供单个虚拟机的假象，该虚拟机提供安全的共享对象和共享名称空间、应用程序可调容错、改进的响应时间和更高的吞吐量。军团的目标是工作站、超级计算机和并行超级计算机的广域集合。Legion解决了现有的基于工作站的并行处理工具无法解决的问题;该系统将实现容错、广域并行处理、互操作性、异构性、单一全局命名空间、保护、安全性、高效调度和综合资源管理。本文描述了核心Legion对象模型，该模型指定了Legion核心对象的组成和功能——这些对象在Legion系统中协同创建、定位、管理和删除对象。对象模型促进灵活的可扩展实现，提供单一的全局名称空间，向参与的组织授予站点自主权，并扩展到数百万个站点和数万亿个对象。
{"title":"The core Legion object model","authors":"M. Lewis, A. Grimshaw","doi":"10.1109/HPDC.1996.546226","DOIUrl":"https://doi.org/10.1109/HPDC.1996.546226","url":null,"abstract":"The Legion project at the University of Virginia is an architecture for designing and building system services that provide the illusion of a single virtual machine to users, a virtual machine that provides secure shared object and shared name spaces, application adjustable fault tolerance, improved response time, and greater throughput. Legion targets wide area assemblies of workstations, supercomputers, and parallel supercomputers. Legion tackles problems not solved by existing workstation based parallel processing tools; the system will enable fault tolerance, wide area parallel processing, interoperability, heterogeneity, a single global name space, protection, security, efficient scheduling, and comprehensive resource management. The paper describes the core Legion object model, which specifies the composition and functionality of Legion's core objects-those objects that cooperate to create, locate, manage, and remove objects in the Legion system. The object model facilitates a flexible extensible implementation, provides a single global name space, grants site autonomy to participating organizations, and scales to millions of sites and trillions of objects.","PeriodicalId":267002,"journal":{"name":"Proceedings of 5th IEEE International Symposium on High Performance Distributed Computing","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1996-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129280043","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-08-06DOI: 10.1109/HPDC.1996.546168
Mani Chandy, B. Dimitrov, Jacob Mandelson, Matthew Richardson, Adam Rifkin, Wesley Tanaka, Luke Weisman
This paper describes the design of a distributed system built using Java that supports peer-to-peer communication among processes spread across a network. We identify the requirements of a software layer that supports distributed computing, and we propose a design that meets those requirements. Our primary concerns are (I) the identification, specification, and implementation of software components that can be composed in different ways to develop correct distributed applications; (2) reasoning about the components systematically; and (3) providing services to the components. This paper deals with the last of these concerns. Though our implementation uses Java, the fundamental ideas apply to any object-oriented language that supports messaging and threads. Alternative implementations use such languages coupled with object request brokers or remote procedure invocation mechanisms.
{"title":"A world-wide distributed system using Java and the Internet","authors":"Mani Chandy, B. Dimitrov, Jacob Mandelson, Matthew Richardson, Adam Rifkin, Wesley Tanaka, Luke Weisman","doi":"10.1109/HPDC.1996.546168","DOIUrl":"https://doi.org/10.1109/HPDC.1996.546168","url":null,"abstract":"This paper describes the design of a distributed system built using Java that supports peer-to-peer communication among processes spread across a network. We identify the requirements of a software layer that supports distributed computing, and we propose a design that meets those requirements. Our primary concerns are (I) the identification, specification, and implementation of software components that can be composed in different ways to develop correct distributed applications; (2) reasoning about the components systematically; and (3) providing services to the components. This paper deals with the last of these concerns. Though our implementation uses Java, the fundamental ideas apply to any object-oriented language that supports messaging and threads. Alternative implementations use such languages coupled with object request brokers or remote procedure invocation mechanisms.","PeriodicalId":267002,"journal":{"name":"Proceedings of 5th IEEE International Symposium on High Performance Distributed Computing","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1996-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129425836","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-08-06DOI: 10.1109/HPDC.1996.546169
J. P. Harrison, B. Christensen, Michael Gulli, Joseph Bianco
A virtual collaborative engineering (VCE) capability for integrated product and process design (IPPD) has been demonstrated which allows distributed, real-time visualization and evaluation of design concepts, manufacturing processes, the total factory and enterprises in one seamless simulation environment. Deneb's VCE dynamic simulation environment provides a capability for realistic engineering 3D simulations to link integrated product teams over WANs. Users can interactively evaluate design concepts, manufacturing workcells, processes and factory layouts at geographically remote locations to support informal and formal IPPD meetings. Anyone on the network can assume control of the simulation and make changes in real-time that can be visualized by others on the network. Benefits include: facilitating and streamlining design reviews; linking integrated product teams early in acquisition programs; integrating suppliers and users to get early feedback in design; and reducing travel costs and improving communications across integrated product teams throughout a program's life cycle. VCE capability enables interactive graphic simulation and development of key elements, including: system performance requirements; configuration definition; assembly sequences and tooling concepts; shop floor layout; handling requirements; and training. Deneb's VCE capability enables real-time, interactive participation regardless of geographical location and is useful from the earliest system definition activities, through the detail design and engineering development phase, and into production and training activities.
{"title":"Virtual collaborative simulation environment for integrated product and process development","authors":"J. P. Harrison, B. Christensen, Michael Gulli, Joseph Bianco","doi":"10.1109/HPDC.1996.546169","DOIUrl":"https://doi.org/10.1109/HPDC.1996.546169","url":null,"abstract":"A virtual collaborative engineering (VCE) capability for integrated product and process design (IPPD) has been demonstrated which allows distributed, real-time visualization and evaluation of design concepts, manufacturing processes, the total factory and enterprises in one seamless simulation environment. Deneb's VCE dynamic simulation environment provides a capability for realistic engineering 3D simulations to link integrated product teams over WANs. Users can interactively evaluate design concepts, manufacturing workcells, processes and factory layouts at geographically remote locations to support informal and formal IPPD meetings. Anyone on the network can assume control of the simulation and make changes in real-time that can be visualized by others on the network. Benefits include: facilitating and streamlining design reviews; linking integrated product teams early in acquisition programs; integrating suppliers and users to get early feedback in design; and reducing travel costs and improving communications across integrated product teams throughout a program's life cycle. VCE capability enables interactive graphic simulation and development of key elements, including: system performance requirements; configuration definition; assembly sequences and tooling concepts; shop floor layout; handling requirements; and training. Deneb's VCE capability enables real-time, interactive participation regardless of geographical location and is useful from the earliest system definition activities, through the detail design and engineering development phase, and into production and training activities.","PeriodicalId":267002,"journal":{"name":"Proceedings of 5th IEEE International Symposium on High Performance Distributed Computing","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1996-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129089316","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-08-06DOI: 10.1109/HPDC.1996.546175
K. Dinçer, G. Fox, K. Hawick
Evaluates the High Performance Fortran (HPF) language for the compact expression and efficient implementation of conjugate-gradient iterative matrix-solvers on high-performance computing and communications (HPCC) platforms. We discuss the use of intrinsic functions, data distribution directives and explicitly parallel constructs to optimize performance by minimizing communications requirements in a portable manner. We focus on implementations using the existing HPF definitions but also discuss issues arising that may influence a revised definition for HPF-2. Some of the codes discussed are available on the World Wide Web at http://www.npac.syr.edu/hpfa/, along with other educational and discussion material related to applications in HPF.
{"title":"High-Performance Fortran and possible extensions to support conjugate gradient algorithms","authors":"K. Dinçer, G. Fox, K. Hawick","doi":"10.1109/HPDC.1996.546175","DOIUrl":"https://doi.org/10.1109/HPDC.1996.546175","url":null,"abstract":"Evaluates the High Performance Fortran (HPF) language for the compact expression and efficient implementation of conjugate-gradient iterative matrix-solvers on high-performance computing and communications (HPCC) platforms. We discuss the use of intrinsic functions, data distribution directives and explicitly parallel constructs to optimize performance by minimizing communications requirements in a portable manner. We focus on implementations using the existing HPF definitions but also discuss issues arising that may influence a revised definition for HPF-2. Some of the codes discussed are available on the World Wide Web at http://www.npac.syr.edu/hpfa/, along with other educational and discussion material related to applications in HPF.","PeriodicalId":267002,"journal":{"name":"Proceedings of 5th IEEE International Symposium on High Performance Distributed Computing","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1996-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128860390","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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