Pub Date : 2022-12-03DOI: 10.1109/IEDM45625.2022.10019419
S. Yoon
For HPC applications, 2.5D and 3D technologies are employed for cloud, AI and ML. High-performance chip size continues to increase up to one reticle size and the cost of the leading-edge silicon node is recently soaring. This makes various solutions, such as MCM, 2.5D and 3D, necessary to develop fine pitch interconnection evolutions with hybrid Cu bonding or fine pitch microbump bonding processes. In this paper, the above mentioned Advanced Package FAB Solutions (APFS) will be introduced and discussed in terms of challenges and opportunities for emerging high-end computing and mobile processor platforms. Additionally, Fanout PKG, RDL interposer, high-performance 3D SIP and Integrated Stacked Capacitor (ISC) will also be introduced.
{"title":"Advanced Package FAB Solutions(APFS) for Chiplet Integration","authors":"S. Yoon","doi":"10.1109/IEDM45625.2022.10019419","DOIUrl":"https://doi.org/10.1109/IEDM45625.2022.10019419","url":null,"abstract":"For HPC applications, 2.5D and 3D technologies are employed for cloud, AI and ML. High-performance chip size continues to increase up to one reticle size and the cost of the leading-edge silicon node is recently soaring. This makes various solutions, such as MCM, 2.5D and 3D, necessary to develop fine pitch interconnection evolutions with hybrid Cu bonding or fine pitch microbump bonding processes. In this paper, the above mentioned Advanced Package FAB Solutions (APFS) will be introduced and discussed in terms of challenges and opportunities for emerging high-end computing and mobile processor platforms. Additionally, Fanout PKG, RDL interposer, high-performance 3D SIP and Integrated Stacked Capacitor (ISC) will also be introduced.","PeriodicalId":275494,"journal":{"name":"2022 International Electron Devices Meeting (IEDM)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121835153","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-03DOI: 10.1109/IEDM45625.2022.10019409
Xueqi Li, B. Gao, Bohan Lin, Ruihua Yu, Han Zhao, Ze Wang, Qiao Qin, Jianshi Tang, Qingtian Zhang, Xinyi Li, Zhenqi Hao, Xiaotao Li, Dequn Kong, Liqiu Ma, Ning Deng, H. Qian, Huaqiang Wu
Homomorphic encryption (HE) is an encryption technology of which encryption and decryption process can be summarized as polynomials modulo multiplication computing with noise. In this paper, HE is firstly implemented on resistive random-access memory (RRAM) arrays, which are utilized as both matrix-vector multiplication (MVM) units and true random number generators (TRNG). Both high stability and good randomness are achieved for MVM and TRNG, respectively, by using different forming schemes, so that two distinct functions can be realized using the same device. Furthermore, the encryption-decryption process for privacy-preserving cloud computing is experimentally implemented on a hardware system with eight 144Kb RRAM arrays. For the whole RRAM array-based encryption-decryption process, small accuracy losses of 0.73% (for SVM) and 1.9% (for CNN) are achieved. This is the first demonstration of encryption computing acceleration with emerging device technology.
{"title":"First Demonstration of Homomorphic Encryption using Multi-Functional RRAM Arrays with a Novel Noise-Modulation Scheme","authors":"Xueqi Li, B. Gao, Bohan Lin, Ruihua Yu, Han Zhao, Ze Wang, Qiao Qin, Jianshi Tang, Qingtian Zhang, Xinyi Li, Zhenqi Hao, Xiaotao Li, Dequn Kong, Liqiu Ma, Ning Deng, H. Qian, Huaqiang Wu","doi":"10.1109/IEDM45625.2022.10019409","DOIUrl":"https://doi.org/10.1109/IEDM45625.2022.10019409","url":null,"abstract":"Homomorphic encryption (HE) is an encryption technology of which encryption and decryption process can be summarized as polynomials modulo multiplication computing with noise. In this paper, HE is firstly implemented on resistive random-access memory (RRAM) arrays, which are utilized as both matrix-vector multiplication (MVM) units and true random number generators (TRNG). Both high stability and good randomness are achieved for MVM and TRNG, respectively, by using different forming schemes, so that two distinct functions can be realized using the same device. Furthermore, the encryption-decryption process for privacy-preserving cloud computing is experimentally implemented on a hardware system with eight 144Kb RRAM arrays. For the whole RRAM array-based encryption-decryption process, small accuracy losses of 0.73% (for SVM) and 1.9% (for CNN) are achieved. This is the first demonstration of encryption computing acceleration with emerging device technology.","PeriodicalId":275494,"journal":{"name":"2022 International Electron Devices Meeting (IEDM)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121247990","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-03DOI: 10.1109/IEDM45625.2022.10019418
M. Vinet
Quantum computing when available will tackle life changing applications, like in energy or chemistry. Silicon has the ability to enable this full quantum advantage leveraging Very-Large-Scale Integration (VLSI) fabrication and design techniques. First scientific demonstrations have been made, it’s now up to electrical engineers in collaboration with physicist to turn these demonstrations into practical machines.
{"title":"Enabling full fault tolerant quantum computing with silicon based VLSI technologies","authors":"M. Vinet","doi":"10.1109/IEDM45625.2022.10019418","DOIUrl":"https://doi.org/10.1109/IEDM45625.2022.10019418","url":null,"abstract":"Quantum computing when available will tackle life changing applications, like in energy or chemistry. Silicon has the ability to enable this full quantum advantage leveraging Very-Large-Scale Integration (VLSI) fabrication and design techniques. First scientific demonstrations have been made, it’s now up to electrical engineers in collaboration with physicist to turn these demonstrations into practical machines.","PeriodicalId":275494,"journal":{"name":"2022 International Electron Devices Meeting (IEDM)","volume":"151 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123784216","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-03DOI: 10.1109/IEDM45625.2022.10019512
Sihan Chen, M. T. Hwang, Jiaojiao Wang, A. Ganguli, Insu Park, Yongdeok Kim, E. Valera, Sungwoo Nam, N. Aluru, A. M. van der Zande, Rashid Bashir
Nano-biosensors offer unprecedented sensitivities over conventional biosensors and enable single bio-molecule analysis. Electronic nano-biosensors offer advantages of label-free detection, low cost, and potential for high-density parallelization. In this paper, we review our past work on electrical detection of DNA and proteins on silicon field-effect transistor (FET) biosensors, ultrasensitive detection of DNA, proteins, and viruses using crumpled graphene FETs, and solid-state nanopore devices for characterization of individual DNA molecules. In addition, a new frontier in bioengineering is the use of biological components for applications in engineering and computing. We also highlight our work on muscle-based miniature bio-robots, and briefly discuss our ongoing work on developing neuron-based bio-computers.
{"title":"Advances in Electronic Nano-biosensors and New Frontiers in Bioengineering","authors":"Sihan Chen, M. T. Hwang, Jiaojiao Wang, A. Ganguli, Insu Park, Yongdeok Kim, E. Valera, Sungwoo Nam, N. Aluru, A. M. van der Zande, Rashid Bashir","doi":"10.1109/IEDM45625.2022.10019512","DOIUrl":"https://doi.org/10.1109/IEDM45625.2022.10019512","url":null,"abstract":"Nano-biosensors offer unprecedented sensitivities over conventional biosensors and enable single bio-molecule analysis. Electronic nano-biosensors offer advantages of label-free detection, low cost, and potential for high-density parallelization. In this paper, we review our past work on electrical detection of DNA and proteins on silicon field-effect transistor (FET) biosensors, ultrasensitive detection of DNA, proteins, and viruses using crumpled graphene FETs, and solid-state nanopore devices for characterization of individual DNA molecules. In addition, a new frontier in bioengineering is the use of biological components for applications in engineering and computing. We also highlight our work on muscle-based miniature bio-robots, and briefly discuss our ongoing work on developing neuron-based bio-computers.","PeriodicalId":275494,"journal":{"name":"2022 International Electron Devices Meeting (IEDM)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125394581","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-03DOI: 10.1109/IEDM45625.2022.10019452
D. Zheng, A. Charnas, J. Anderson, H. Dou, Z. Hu, Z. Lin, Z. Zhang, J. Zhang, Pai-Ying Liao, M. Si, Hong Wang, D. Weinstein, P. Ye
This work reports for the first time ultrathin atomic-layer-deposited (ALD) InZnO as a novel back-end-of line (BEOL) channel material for monolithic 3D integration. By tuning the ratio of In to Zn with ALD cycles, InZnO transistors with 3.5 nm channel thickness can achieve excellent subthreshold swings (SS) as low as 65 mV/dec, high on-off current ratio up to $10 ^{11}$, and sizeable on-current density (ION) up to 1.33 A/mm for In-rich channels at 100 nm channel length with drain voltage (VDS) of 1 V. A surprising high degree of stability under large positive gate bias stress (statistically measured threshold voltage shift $Delta mathrm{V}_{T}$ of -16 mV after 1500 s stress with gate voltage bias (VBias) of 3.5 V) is observed in the In:Zn $=1$:1 case. ALD process resolves the long-time concern on the stability of sputtered InZnO films as the channels without Ga doping. A charge-neutrality-level (CNL) alignment and trap generation model is proposed to explain this unique phenomenon of negligible VT shift under positive gate bias stress (PBS). Finally, ground-signal-ground (GSG) structures are also fabricated to investigate the RF performance of these BEOL-compatible transistors with GHz operation frequencies.
{"title":"First Demonstration of BEOL-Compatible Ultrathin AtomicLayer-Deposited InZnO Transistors with GHz Operation and Record High Bias-Stress Stability","authors":"D. Zheng, A. Charnas, J. Anderson, H. Dou, Z. Hu, Z. Lin, Z. Zhang, J. Zhang, Pai-Ying Liao, M. Si, Hong Wang, D. Weinstein, P. Ye","doi":"10.1109/IEDM45625.2022.10019452","DOIUrl":"https://doi.org/10.1109/IEDM45625.2022.10019452","url":null,"abstract":"This work reports for the first time ultrathin atomic-layer-deposited (ALD) InZnO as a novel back-end-of line (BEOL) channel material for monolithic 3D integration. By tuning the ratio of In to Zn with ALD cycles, InZnO transistors with 3.5 nm channel thickness can achieve excellent subthreshold swings (SS) as low as 65 mV/dec, high on-off current ratio up to $10 ^{11}$, and sizeable on-current density (ION) up to 1.33 A/mm for In-rich channels at 100 nm channel length with drain voltage (VDS) of 1 V. A surprising high degree of stability under large positive gate bias stress (statistically measured threshold voltage shift $Delta mathrm{V}_{T}$ of -16 mV after 1500 s stress with gate voltage bias (VBias) of 3.5 V) is observed in the In:Zn $=1$:1 case. ALD process resolves the long-time concern on the stability of sputtered InZnO films as the channels without Ga doping. A charge-neutrality-level (CNL) alignment and trap generation model is proposed to explain this unique phenomenon of negligible VT shift under positive gate bias stress (PBS). Finally, ground-signal-ground (GSG) structures are also fabricated to investigate the RF performance of these BEOL-compatible transistors with GHz operation frequencies.","PeriodicalId":275494,"journal":{"name":"2022 International Electron Devices Meeting (IEDM)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126938186","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-03DOI: 10.1109/IEDM45625.2022.10019406
Zhenyu Wang, Gopikrishnan Raveendran Nair, Gokul Krishnan, Sumit K. Mandal, Ninoo Cherian, Jae-sun Seo, C. Chakrabarti, U. Ogras, Yu Cao
The demands on bandwidth, latency and energy efficiency are ever increasing in AI computing. Chiplets, connected by 2. 5D interconnect, promise a scalable platform to meet such needs. We present a pathfinding study to bridge AI algorithms with the chiplet architecture, covering in memory computing (IMC), network-on-package (NoP), and heterogeneous architecture. This study is enabled by our newly developed benchmarking tool, SIAM. We perform simulations on representative algorithms (DNNs, transformers and GCNs). Particular contributions include: (1) A roadmap of 2. 5D interconnect for technological exploration; (2) A generic mapping and optimization methodology that reveals various bandwidth needs in AI computing, where the evolution of 2.5D interconnect can or cannot support; (3) A big-little chiplet architecture that matches the non-uniform nature of AI algorithms and achieves >100× improvement in EDP. Overall, heterogeneous big-little chiplets with 2. 5D interconnect advance AI computing to the next level of data movement and computing efficiency.
{"title":"AI Computing in Light of 2.5D Interconnect Roadmap: Big-Little Chiplets for In-memory Acceleration","authors":"Zhenyu Wang, Gopikrishnan Raveendran Nair, Gokul Krishnan, Sumit K. Mandal, Ninoo Cherian, Jae-sun Seo, C. Chakrabarti, U. Ogras, Yu Cao","doi":"10.1109/IEDM45625.2022.10019406","DOIUrl":"https://doi.org/10.1109/IEDM45625.2022.10019406","url":null,"abstract":"The demands on bandwidth, latency and energy efficiency are ever increasing in AI computing. Chiplets, connected by 2. 5D interconnect, promise a scalable platform to meet such needs. We present a pathfinding study to bridge AI algorithms with the chiplet architecture, covering in memory computing (IMC), network-on-package (NoP), and heterogeneous architecture. This study is enabled by our newly developed benchmarking tool, SIAM. We perform simulations on representative algorithms (DNNs, transformers and GCNs). Particular contributions include: (1) A roadmap of 2. 5D interconnect for technological exploration; (2) A generic mapping and optimization methodology that reveals various bandwidth needs in AI computing, where the evolution of 2.5D interconnect can or cannot support; (3) A big-little chiplet architecture that matches the non-uniform nature of AI algorithms and achieves >100× improvement in EDP. Overall, heterogeneous big-little chiplets with 2. 5D interconnect advance AI computing to the next level of data movement and computing efficiency.","PeriodicalId":275494,"journal":{"name":"2022 International Electron Devices Meeting (IEDM)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115087862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-03DOI: 10.1109/IEDM45625.2022.10019507
X.-R. Yu, Min-Hui Chuang, S. Chang, W. Chang, T. Hong, Chien-Hsueh Chiang, W.-H. Lu, C.-Y. Yang, W.-J. Chen, J. Lin, Pei-Hsuan Wu, T.-C. Sun, S. Kola, Y.-S. Yang, Yun Da, P. Sung, C. Wu, Ta-Chun Cho, G. Luo, K. Kao, M. Chiang, W. C. Ma, C. Su, T. Chao, T. Maeda, S. Samukawa, Y. Li, Y. Lee, W. Wu, J. Tarng, Y. Wang
In this work, we propose an advanced 3-D heterogeneous 6T SRAM with a newly designed hetero-integration method. CFET inverters and IGZO pass gates are vertically stacked within a 2T footprint area. The Low-Temperature Hetero-Layers Bonding Technique (LT-HBT) process is utilized successfully to fabricate single crystalline heterogeneous Double Layer Transferred (DLT) Ge/2Si CFET-OI on an 8-inch full wafer. Furthermore, an IGZO nFET is deposited and treated as a pass gate (PG) to realize a 6T SRAM operation. The hetero-integration of IGZO PG and self-align DLT Ge/2Si CFET inverters showed improved Read Static Noise Margin (RSNM) and stand-by leakage power. The state-of-the-art 3-D heterogeneous 6T SRAM leads to 42% area reduction.
{"title":"Integration Design and Process of 3-D Heterogeneous 6T SRAM with Double Layer Transferred Ge/2Si CFET and IGZO Pass Gates for 42% Reduced Cell Size","authors":"X.-R. Yu, Min-Hui Chuang, S. Chang, W. Chang, T. Hong, Chien-Hsueh Chiang, W.-H. Lu, C.-Y. Yang, W.-J. Chen, J. Lin, Pei-Hsuan Wu, T.-C. Sun, S. Kola, Y.-S. Yang, Yun Da, P. Sung, C. Wu, Ta-Chun Cho, G. Luo, K. Kao, M. Chiang, W. C. Ma, C. Su, T. Chao, T. Maeda, S. Samukawa, Y. Li, Y. Lee, W. Wu, J. Tarng, Y. Wang","doi":"10.1109/IEDM45625.2022.10019507","DOIUrl":"https://doi.org/10.1109/IEDM45625.2022.10019507","url":null,"abstract":"In this work, we propose an advanced 3-D heterogeneous 6T SRAM with a newly designed hetero-integration method. CFET inverters and IGZO pass gates are vertically stacked within a 2T footprint area. The Low-Temperature Hetero-Layers Bonding Technique (LT-HBT) process is utilized successfully to fabricate single crystalline heterogeneous Double Layer Transferred (DLT) Ge/2Si CFET-OI on an 8-inch full wafer. Furthermore, an IGZO nFET is deposited and treated as a pass gate (PG) to realize a 6T SRAM operation. The hetero-integration of IGZO PG and self-align DLT Ge/2Si CFET inverters showed improved Read Static Noise Margin (RSNM) and stand-by leakage power. The state-of-the-art 3-D heterogeneous 6T SRAM leads to 42% area reduction.","PeriodicalId":275494,"journal":{"name":"2022 International Electron Devices Meeting (IEDM)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116139941","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-03DOI: 10.1109/IEDM45625.2022.10019414
S. Shimada, Y. Otake, S. Yoshida, Y. Jibiki, M. Fujii, S. Endo, R. Nakamura, H. Tsugawa, Y. Fujisaki, K. Yokochi, J. Iwase, K. Takabayashi, H. Maeda, K. Sugihara, K. Yamamoto, M. Ono, K. Ishibashi, S. Matsumoto, H. Hiyama, T. Wakano
We present scaled down Single Photon Avalanche Diode (SPAD) pixels to prevent Photon Detection Efficiency (PDE) degradation under high ambient light. This study is carried out on Back-Illuminated (BI) 3D-stacked SPAD array sensors with 3.3, 3.0, and 2.5μm pixel pitches fabricated using a CMOS 300mm platform. To achieve pixel scaling, the developed pixels introduce a sub-micron avalanche region to prevent premature edge breakdown while allowing for a low Dark Count Rate (DCR). Moreover, optimized optical lenses enable scaled down pixels to achieve approximately 100% fill factor, thereby boosting the PDE at λ=940nm beyond 20%, even under sunlight conditions. These sensors offer cost-efficient and high accuracy depth-sensing capabilities, even under challenging ambient light conditions.
{"title":"A SPAD Depth Sensor Robust Against Ambient Light: The Importance of Pixel Scaling and Demonstration of a 2.5μm Pixel with 21.8% PDE at 940nm","authors":"S. Shimada, Y. Otake, S. Yoshida, Y. Jibiki, M. Fujii, S. Endo, R. Nakamura, H. Tsugawa, Y. Fujisaki, K. Yokochi, J. Iwase, K. Takabayashi, H. Maeda, K. Sugihara, K. Yamamoto, M. Ono, K. Ishibashi, S. Matsumoto, H. Hiyama, T. Wakano","doi":"10.1109/IEDM45625.2022.10019414","DOIUrl":"https://doi.org/10.1109/IEDM45625.2022.10019414","url":null,"abstract":"We present scaled down Single Photon Avalanche Diode (SPAD) pixels to prevent Photon Detection Efficiency (PDE) degradation under high ambient light. This study is carried out on Back-Illuminated (BI) 3D-stacked SPAD array sensors with 3.3, 3.0, and 2.5μm pixel pitches fabricated using a CMOS 300mm platform. To achieve pixel scaling, the developed pixels introduce a sub-micron avalanche region to prevent premature edge breakdown while allowing for a low Dark Count Rate (DCR). Moreover, optimized optical lenses enable scaled down pixels to achieve approximately 100% fill factor, thereby boosting the PDE at λ=940nm beyond 20%, even under sunlight conditions. These sensors offer cost-efficient and high accuracy depth-sensing capabilities, even under challenging ambient light conditions.","PeriodicalId":275494,"journal":{"name":"2022 International Electron Devices Meeting (IEDM)","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117253850","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-03DOI: 10.1109/IEDM45625.2022.10019539
Jinwoo Park, Tae-Hyeon Kim, Sungjoon Kim, M. Song, S. Youn, Kyungho Hong, Byung-Gook Park, Hyungjin Kim
In this work, we present highly reliable operations of physical unclonable function (PUF) using the pristine state of Al2 O3/TiOx memristor crossbar arrays. The device stack is optimized in terms of stoichiometry and thickness to obtain temperature-independent $I-V$ properties. A strong PUF with a large $(sim 10 ^{17})$ number of challenge-response pairs is demonstrated based on the crossbars, and the bit-error rate (BER) was experimentally verified less than 1% (0.896% at 80 °C) without correction methods thanks to tunneling conduction. In addition, the uniformity, diffuseness, and uniqueness of the PUF are evaluated ~50%, and its randomness is verified through both NIST tests and machine learning attacks, confirming robust security property.
{"title":"Highly Reliable Physical Unclonable Functions using Memristor Crossbar with Tunneling Conduction","authors":"Jinwoo Park, Tae-Hyeon Kim, Sungjoon Kim, M. Song, S. Youn, Kyungho Hong, Byung-Gook Park, Hyungjin Kim","doi":"10.1109/IEDM45625.2022.10019539","DOIUrl":"https://doi.org/10.1109/IEDM45625.2022.10019539","url":null,"abstract":"In this work, we present highly reliable operations of physical unclonable function (PUF) using the pristine state of Al2 O3/TiOx memristor crossbar arrays. The device stack is optimized in terms of stoichiometry and thickness to obtain temperature-independent $I-V$ properties. A strong PUF with a large $(sim 10 ^{17})$ number of challenge-response pairs is demonstrated based on the crossbars, and the bit-error rate (BER) was experimentally verified less than 1% (0.896% at 80 °C) without correction methods thanks to tunneling conduction. In addition, the uniformity, diffuseness, and uniqueness of the PUF are evaluated ~50%, and its randomness is verified through both NIST tests and machine learning attacks, confirming robust security property.","PeriodicalId":275494,"journal":{"name":"2022 International Electron Devices Meeting (IEDM)","volume":"275 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129630332","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-03DOI: 10.1109/IEDM45625.2022.10019560
N. Haratipour, Sou-Chi Chang, S. Shivaraman, C. Neumann, Y. Liao, B. G. Alpizar, I. Tung, Hai Helen Li, Vachan Kumar, B. Doyle, S. Atanasov, J. Peck, N. Kabir, G. Allen, T. Hoff, A. Oni, Sourav Dutta, T. Tronic, Anandi Roy, F. Hamzaoglu, R. Bristol, M. Metz, I. Young, J. Kavalieros, U. Avci
FeRAM is a promising candidate for next generation embedded DRAM and has attracted significant attention with the advancements in hafnia-based ferroelectric research. In this work, we will review record specifications achieved for implementing FeRAM as an embedded memory such as 2 nanoseconds switching speed, >1012 read/write endurance cycles, low operation voltage, long retention, and operation under worst case anti-ferroelectric (AFE) capacitors process variations at elevated temperature of 85°C. Array-level circuit simulation based on the advanced technology node also indicates that FeRAM can be used as a high-density embedded memory. Finally, functional 3D stacked AFE capacitors with matched performance to conventional trench AFE capacitors are demonstrated for the first time paving the path toward ultrahigh density embedded FeRAM.
{"title":"Hafnia-Based FeRAM: A Path Toward Ultra-High Density for Next-Generation High-Speed Embedded Memory","authors":"N. Haratipour, Sou-Chi Chang, S. Shivaraman, C. Neumann, Y. Liao, B. G. Alpizar, I. Tung, Hai Helen Li, Vachan Kumar, B. Doyle, S. Atanasov, J. Peck, N. Kabir, G. Allen, T. Hoff, A. Oni, Sourav Dutta, T. Tronic, Anandi Roy, F. Hamzaoglu, R. Bristol, M. Metz, I. Young, J. Kavalieros, U. Avci","doi":"10.1109/IEDM45625.2022.10019560","DOIUrl":"https://doi.org/10.1109/IEDM45625.2022.10019560","url":null,"abstract":"FeRAM is a promising candidate for next generation embedded DRAM and has attracted significant attention with the advancements in hafnia-based ferroelectric research. In this work, we will review record specifications achieved for implementing FeRAM as an embedded memory such as 2 nanoseconds switching speed, >1012 read/write endurance cycles, low operation voltage, long retention, and operation under worst case anti-ferroelectric (AFE) capacitors process variations at elevated temperature of 85°C. Array-level circuit simulation based on the advanced technology node also indicates that FeRAM can be used as a high-density embedded memory. Finally, functional 3D stacked AFE capacitors with matched performance to conventional trench AFE capacitors are demonstrated for the first time paving the path toward ultrahigh density embedded FeRAM.","PeriodicalId":275494,"journal":{"name":"2022 International Electron Devices Meeting (IEDM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129266456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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