Pub Date : 2016-12-27DOI: 10.1109/ISOCC.2016.7799755
Koki Ishida, Masamitsu Tanaka, Takatsugu Ono, Koji Inoue
Single-flux-quantum (SFQ) logic is promising technology to realize an incredible microprocessor which operates over 100 GHz due to its ultra-fast-speed and ultra-low-power natures. Although previous work has demonstrated prototype of an SFQ microprocessor, the SFQ based L1 cache memory has not well optimized: a large access latency and strictly limited scalability. This paper proposes a novel SFQ cache architecture to support fast accesses. The sub-arrayed structure applied to the cache produces better scalability in terms of capacity. Evaluation results show that the proposed cache achieves 1.8X fast access speed.
{"title":"Single-flux-quantum cache memory architecture","authors":"Koki Ishida, Masamitsu Tanaka, Takatsugu Ono, Koji Inoue","doi":"10.1109/ISOCC.2016.7799755","DOIUrl":"https://doi.org/10.1109/ISOCC.2016.7799755","url":null,"abstract":"Single-flux-quantum (SFQ) logic is promising technology to realize an incredible microprocessor which operates over 100 GHz due to its ultra-fast-speed and ultra-low-power natures. Although previous work has demonstrated prototype of an SFQ microprocessor, the SFQ based L1 cache memory has not well optimized: a large access latency and strictly limited scalability. This paper proposes a novel SFQ cache architecture to support fast accesses. The sub-arrayed structure applied to the cache produces better scalability in terms of capacity. Evaluation results show that the proposed cache achieves 1.8X fast access speed.","PeriodicalId":278207,"journal":{"name":"2016 International SoC Design Conference (ISOCC)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116510992","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-27DOI: 10.1109/ISOCC.2016.7799721
T. Ishihara, A. Shinya, Koji Inoue, K. Nozaki, M. Notomi
Integrated optical circuits with nanophotonic devices have attracted significant attention due to its low power dissipation and light-speed operation. With light interference and resonance phenomena, the nanophotonic device works as a voltage-controlled optical pass-gate like a pass-transistor. This paper first introduces a concept of the optical pass-gate logic, and then proposes a parallel adder circuit based on the optical pass-gate logic. Experimental results obtained with an optoelectronic circuit simulator show advantages of our optical parallel adder circuit over a traditional CMOS-based parallel adder circuit.
{"title":"An integrated optical parallel adder as a first step towards light speed data processing","authors":"T. Ishihara, A. Shinya, Koji Inoue, K. Nozaki, M. Notomi","doi":"10.1109/ISOCC.2016.7799721","DOIUrl":"https://doi.org/10.1109/ISOCC.2016.7799721","url":null,"abstract":"Integrated optical circuits with nanophotonic devices have attracted significant attention due to its low power dissipation and light-speed operation. With light interference and resonance phenomena, the nanophotonic device works as a voltage-controlled optical pass-gate like a pass-transistor. This paper first introduces a concept of the optical pass-gate logic, and then proposes a parallel adder circuit based on the optical pass-gate logic. Experimental results obtained with an optoelectronic circuit simulator show advantages of our optical parallel adder circuit over a traditional CMOS-based parallel adder circuit.","PeriodicalId":278207,"journal":{"name":"2016 International SoC Design Conference (ISOCC)","volume":"125 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131628695","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-27DOI: 10.1109/ISOCC.2016.7799744
Jiayi Ma, Cong Hao, Wencan Zhang, T. Yoshimura
Network-on-Chip (NoC) is a promising solution for System-on-Chip (SoC) challenges. In this work, we present a Decompose and Cluster generation Refinement (DCR) algorithm to find minimum power consumption simultaneously. A two-stage method is proposed for decompose and cluster generation step to generate solutions with lower power. Refinement step explores optimal positions and adjusts clusters for selected solutions to find balanced point between power consumption and CPU time. Experimental results show that the proposed method outperforms the existing work.
{"title":"Power-efficient partitioning and cluster generation design for application-specific Network-on-Chip","authors":"Jiayi Ma, Cong Hao, Wencan Zhang, T. Yoshimura","doi":"10.1109/ISOCC.2016.7799744","DOIUrl":"https://doi.org/10.1109/ISOCC.2016.7799744","url":null,"abstract":"Network-on-Chip (NoC) is a promising solution for System-on-Chip (SoC) challenges. In this work, we present a Decompose and Cluster generation Refinement (DCR) algorithm to find minimum power consumption simultaneously. A two-stage method is proposed for decompose and cluster generation step to generate solutions with lower power. Refinement step explores optimal positions and adjusts clusters for selected solutions to find balanced point between power consumption and CPU time. Experimental results show that the proposed method outperforms the existing work.","PeriodicalId":278207,"journal":{"name":"2016 International SoC Design Conference (ISOCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129246068","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-27DOI: 10.1109/ISOCC.2016.7799852
Ryota Shimizu, S. Yanagawa, Yasutaka Monde, Hiroki Yamagishi, M. Hamada, Toru Shimizu, T. Kuroda
Personal and easy-to-use health checking system is an attractive application of sensor systems. Sensing data analysis for diagnosis is important as well as preparing small and mobile sensor nodes because sensing data include variations and noises reflecting individual difference of people and sensing conditions. Deep Neural Network, or Deep Learning, is a well-known method of machine learning and it is effective for feature extraction from pictures. Then, we thought Deep Learning also can extract features from sensing data. In this paper, we tried to build a diagnosis system of lung cancer based on Deep Learning. Input data of the system was generated from human urine by Gas Chromatography Mass Spectrometer (GC-MS) and our system achieved 90% accuracy in judging whether the patient had lung cancer or not. This system will be useful for pre- and personal diagnosis because collecting urine is very easy and not harmful to human body. We are targeting installation of this system not only to gas chromatography systems but also to some combination of multiple sensors for detecting gases of low concentration.
{"title":"Deep learning application trial to lung cancer diagnosis for medical sensor systems","authors":"Ryota Shimizu, S. Yanagawa, Yasutaka Monde, Hiroki Yamagishi, M. Hamada, Toru Shimizu, T. Kuroda","doi":"10.1109/ISOCC.2016.7799852","DOIUrl":"https://doi.org/10.1109/ISOCC.2016.7799852","url":null,"abstract":"Personal and easy-to-use health checking system is an attractive application of sensor systems. Sensing data analysis for diagnosis is important as well as preparing small and mobile sensor nodes because sensing data include variations and noises reflecting individual difference of people and sensing conditions. Deep Neural Network, or Deep Learning, is a well-known method of machine learning and it is effective for feature extraction from pictures. Then, we thought Deep Learning also can extract features from sensing data. In this paper, we tried to build a diagnosis system of lung cancer based on Deep Learning. Input data of the system was generated from human urine by Gas Chromatography Mass Spectrometer (GC-MS) and our system achieved 90% accuracy in judging whether the patient had lung cancer or not. This system will be useful for pre- and personal diagnosis because collecting urine is very easy and not harmful to human body. We are targeting installation of this system not only to gas chromatography systems but also to some combination of multiple sensors for detecting gases of low concentration.","PeriodicalId":278207,"journal":{"name":"2016 International SoC Design Conference (ISOCC)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117213635","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-27DOI: 10.1109/ISOCC.2016.7799703
Kohei Yamada, Yosuke Toyama, H. Ishikuro
This paper presents an ADC with programmability between SAR-only mode and delta-sigma (ΔΣ) assisted mode. The ΔΣ assisted mode brings 1st order noise shaping for resolution enhancement. Proposed charge shuttling technique makes it possible to share a charge re-distribution capacitor array for DAC in SAR, feedback DAC, and integrator capacitor in ΔΣ loop and improve the accuracy. The prototype ADC fabricated in 65-nm CMOS achieved SNDR of 44.35 dB at sampling rate of 32 MHz and power consumption of 0.55mW. The SNDR is improved to 62.9dB by ΔΣ assisted mode when the signal bandwidth is 60 kHz.
{"title":"A programmable ΔΣ SAR-ADC with charge shuttling technique","authors":"Kohei Yamada, Yosuke Toyama, H. Ishikuro","doi":"10.1109/ISOCC.2016.7799703","DOIUrl":"https://doi.org/10.1109/ISOCC.2016.7799703","url":null,"abstract":"This paper presents an ADC with programmability between SAR-only mode and delta-sigma (ΔΣ) assisted mode. The ΔΣ assisted mode brings 1st order noise shaping for resolution enhancement. Proposed charge shuttling technique makes it possible to share a charge re-distribution capacitor array for DAC in SAR, feedback DAC, and integrator capacitor in ΔΣ loop and improve the accuracy. The prototype ADC fabricated in 65-nm CMOS achieved SNDR of 44.35 dB at sampling rate of 32 MHz and power consumption of 0.55mW. The SNDR is improved to 62.9dB by ΔΣ assisted mode when the signal bandwidth is 60 kHz.","PeriodicalId":278207,"journal":{"name":"2016 International SoC Design Conference (ISOCC)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115084892","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-27DOI: 10.1109/ISOCC.2016.7799750
Kazushi Kawamura, M. Yanagisawa, N. Togawa
This paper proposes a high-performance circuit design algorithm using input data dependent approximation. In our algorithm, STEPCs (Suspicious Timing Error Prediction Circuits) are utilized for identifying the paths to be optimized inside a circuit efficiently. Experimental results targeting a set of basic adders show that our algorithm can achieve performance increase by up to 11.1% within the error rate of 2.1% compared to a conventional design technique.
{"title":"A high-performance circuit design algorithm using data dependent approximation","authors":"Kazushi Kawamura, M. Yanagisawa, N. Togawa","doi":"10.1109/ISOCC.2016.7799750","DOIUrl":"https://doi.org/10.1109/ISOCC.2016.7799750","url":null,"abstract":"This paper proposes a high-performance circuit design algorithm using input data dependent approximation. In our algorithm, STEPCs (Suspicious Timing Error Prediction Circuits) are utilized for identifying the paths to be optimized inside a circuit efficiently. Experimental results targeting a set of basic adders show that our algorithm can achieve performance increase by up to 11.1% within the error rate of 2.1% compared to a conventional design technique.","PeriodicalId":278207,"journal":{"name":"2016 International SoC Design Conference (ISOCC)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122040597","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-27DOI: 10.1109/ISOCC.2016.7799736
K. Shimazaki, Takashi Aoki, T. Hatano, Takuya Otsuka, A. Miyazaki, T. Tsuda, N. Togawa
Recently, content centric networking (CCN) attracts attention as a next generation network on which every router forwards a packet to another router and also functions as a server. A CCN router has a forwarding table called FIB (Forwarding Information Base) but its table look-up can become a bottleneck. In this paper, we propose FIB data structure for CCN routers which can reduce the number of comparisons in its look-up table. Our proposed FIB is composed of a bloom filter and a hash table and each hash entry is connected to a balanced binary-search tree. By using our FIB, the number of comparisons cannot much increase even if hash collisions occur. Experimental results demonstrate the effectiveness of the proposed FIB over the several existing methods.
最近，内容中心网络(content centric networking, CCN)作为下一代网络备受关注，在该网络上，每个路由器都可以将数据包转发给另一个路由器，同时还可以充当服务器。CCN路由器有一个称为FIB (forwarding Information Base)的转发表，但它的表查找可能成为瓶颈。本文提出了一种用于CCN路由器的FIB数据结构，它可以减少查找表中的比较次数。我们提出的FIB由一个布隆过滤器和一个哈希表组成，每个哈希表连接到一个平衡二叉搜索树。通过使用FIB，即使发生哈希冲突，比较的次数也不会增加太多。实验结果表明，该方法比现有的几种方法更有效。
{"title":"Hash-table and balanced-tree based FIB architecture for CCN routers","authors":"K. Shimazaki, Takashi Aoki, T. Hatano, Takuya Otsuka, A. Miyazaki, T. Tsuda, N. Togawa","doi":"10.1109/ISOCC.2016.7799736","DOIUrl":"https://doi.org/10.1109/ISOCC.2016.7799736","url":null,"abstract":"Recently, content centric networking (CCN) attracts attention as a next generation network on which every router forwards a packet to another router and also functions as a server. A CCN router has a forwarding table called FIB (Forwarding Information Base) but its table look-up can become a bottleneck. In this paper, we propose FIB data structure for CCN routers which can reduce the number of comparisons in its look-up table. Our proposed FIB is composed of a bloom filter and a hash table and each hash entry is connected to a balanced binary-search tree. By using our FIB, the number of comparisons cannot much increase even if hash collisions occur. Experimental results demonstrate the effectiveness of the proposed FIB over the several existing methods.","PeriodicalId":278207,"journal":{"name":"2016 International SoC Design Conference (ISOCC)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129405430","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-25DOI: 10.1109/ISOCC.2016.7799865
Yuechun Wang, K. Man, R. Maunder, Jinkyung Lee, Kyung Ki Kim
This paper presents a UHF RFID Reader designed for recognition and tracking in IoT domain. It is built by NI USRP software radio platform and NI LabVIEW with flexible physical/MAC layer parameters, which can be modified easily and monitored clearly from front panel of this Reader compared to commercial RFID Reader. Queried random number sequence from a commercial Tag can be detected within half meter using this UHF Reader. All designs of this Reader are based on EPC Gen-2 RFID protocol, any further research based on this Reader can be easily connected and tested with commercial Tags.
{"title":"A flexible software defined radio-based UHF RFID reader based on the USRP and LabView","authors":"Yuechun Wang, K. Man, R. Maunder, Jinkyung Lee, Kyung Ki Kim","doi":"10.1109/ISOCC.2016.7799865","DOIUrl":"https://doi.org/10.1109/ISOCC.2016.7799865","url":null,"abstract":"This paper presents a UHF RFID Reader designed for recognition and tracking in IoT domain. It is built by NI USRP software radio platform and NI LabVIEW with flexible physical/MAC layer parameters, which can be modified easily and monitored clearly from front panel of this Reader compared to commercial RFID Reader. Queried random number sequence from a commercial Tag can be detected within half meter using this UHF Reader. All designs of this Reader are based on EPC Gen-2 RFID protocol, any further research based on this Reader can be easily connected and tested with commercial Tags.","PeriodicalId":278207,"journal":{"name":"2016 International SoC Design Conference (ISOCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128579693","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/ISOCC.2016.7799706
Seongheon Shin, Hyung-Joun Yoo
This paper proposes a pipelined time stretching technique for high throughput counter-based time-to-digital converters (TDC). Time stretching technique is used to increase the resolution of counter-based TDCs, yet it carries an inherent weakness of having a long conversion time due to the stretching phase. Without significant increment of chip area, the proposed pipelined time stretching method is realized with addition of a time splitter, a switching circuit and a fine capacitor. Pipelining of sampling and stretching efficiently improves the conversion rate by 29% according to the simulation results with a TSMC 0.25μm CMOS process.
{"title":"A pipelined time stretching for high throughput counter-based time-to-digital converters","authors":"Seongheon Shin, Hyung-Joun Yoo","doi":"10.1109/ISOCC.2016.7799706","DOIUrl":"https://doi.org/10.1109/ISOCC.2016.7799706","url":null,"abstract":"This paper proposes a pipelined time stretching technique for high throughput counter-based time-to-digital converters (TDC). Time stretching technique is used to increase the resolution of counter-based TDCs, yet it carries an inherent weakness of having a long conversion time due to the stretching phase. Without significant increment of chip area, the proposed pipelined time stretching method is realized with addition of a time splitter, a switching circuit and a fine capacitor. Pipelining of sampling and stretching efficiently improves the conversion rate by 29% according to the simulation results with a TSMC 0.25μm CMOS process.","PeriodicalId":278207,"journal":{"name":"2016 International SoC Design Conference (ISOCC)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115429053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/ISOCC.2016.7799851
Young-Hyun Baek
We proposes a robust optical fingerprint sensor to moisture fingerprints. This sensor a new lens and prim design and optical-path change structure is proposed, which shows improvement of difference between a ridge and valley sensing image than typical fingerprint sensor. Simulations show that the optical fingerprint sensor an effective performance in the moisture ten-fingerprints and the result of NIST quality map.
{"title":"Robust optical fingerprint sensor to moisture fingerprints","authors":"Young-Hyun Baek","doi":"10.1109/ISOCC.2016.7799851","DOIUrl":"https://doi.org/10.1109/ISOCC.2016.7799851","url":null,"abstract":"We proposes a robust optical fingerprint sensor to moisture fingerprints. This sensor a new lens and prim design and optical-path change structure is proposed, which shows improvement of difference between a ridge and valley sensing image than typical fingerprint sensor. Simulations show that the optical fingerprint sensor an effective performance in the moisture ten-fingerprints and the result of NIST quality map.","PeriodicalId":278207,"journal":{"name":"2016 International SoC Design Conference (ISOCC)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127173665","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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