BoPi is a programming language with a runtime support that allows the distribution and the execution of programs over the network. The language is a process calculus with XML values and datatypes, and with a pattern matching mechanism for deconstructing values. The compiler gives a typesafe bytecode in the form of an XML document, that may be deployed on the network. What comes out is a simple, statically typed, and formally defined core BPEL language with a basic query mechanism supplied by patterns.
{"title":"BoPi - a distributed machine for experimenting Web services technologies","authors":"Samuele Carpineti, C. Laneve, P. Milazzo","doi":"10.1109/ACSD.2005.6","DOIUrl":"https://doi.org/10.1109/ACSD.2005.6","url":null,"abstract":"BoPi is a programming language with a runtime support that allows the distribution and the execution of programs over the network. The language is a process calculus with XML values and datatypes, and with a pattern matching mechanism for deconstructing values. The compiler gives a typesafe bytecode in the form of an XML document, that may be deployed on the network. What comes out is a simple, statically typed, and formally defined core BPEL language with a basic query mechanism supplied by patterns.","PeriodicalId":279517,"journal":{"name":"Fifth International Conference on Application of Concurrency to System Design (ACSD'05)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116462829","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper deals with the verification of CTL* properties of Time Petri Nets (TPN model). To verify such properties, we need to contract the generally infinite state space of the TPN model into a finite graph that preserves its CTL* properties. Such a graph can be constructed using a partition refinement technique, where an intermediate graph, representing a contraction of the TPN state space, is first built then refined until CTL* properties are restored. Comparing to other approaches, we propose to construct much compact intermediate graphs. Experimental results have shown that our contractions are very appropriate to boost the refinement procedure. We have been able to reduce computation times by factors reaching four and more in certain cases. Resulting graphs have also been reduced in size.
{"title":"Much compact Time Petri Net state class spaces useful to restore CTL* properties","authors":"Rachid Hadjidj, H. Boucheneb","doi":"10.1109/ACSD.2005.28","DOIUrl":"https://doi.org/10.1109/ACSD.2005.28","url":null,"abstract":"This paper deals with the verification of CTL* properties of Time Petri Nets (TPN model). To verify such properties, we need to contract the generally infinite state space of the TPN model into a finite graph that preserves its CTL* properties. Such a graph can be constructed using a partition refinement technique, where an intermediate graph, representing a contraction of the TPN state space, is first built then refined until CTL* properties are restored. Comparing to other approaches, we propose to construct much compact intermediate graphs. Experimental results have shown that our contractions are very appropriate to boost the refinement procedure. We have been able to reduce computation times by factors reaching four and more in certain cases. Resulting graphs have also been reduced in size.","PeriodicalId":279517,"journal":{"name":"Fifth International Conference on Application of Concurrency to System Design (ACSD'05)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122080152","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Wei Zheng, J. Chong, C. Pinello, Sri Kanajan, A. Sangiovanni-Vincentelli
The objective of this paper is to present how to design a system that can accommodate additional functionality with either no changes to the design or adding architectural modules without changing the implementation of the legacy functionality. This objective is very relevant to industrial domains where an architecture is designed before the full range of functionalities to support is known. We focus on an important aspect of the design of automotive systems: the scheduling problem for hard real time distributed embedded systems. Two metrics are used to capture the design goals. The metrics are optimized subject to a set of constraints within a mathematical programming framework. The cost of modifying a legacy system is characterized at an electrical control unit (ECU) component level. Results obtained in automotive applications show that the optimization framework is effective in reducing development and re-verification efforts after incremental design changes.
{"title":"Extensible and scalable time triggered scheduling","authors":"Wei Zheng, J. Chong, C. Pinello, Sri Kanajan, A. Sangiovanni-Vincentelli","doi":"10.1109/ACSD.2005.13","DOIUrl":"https://doi.org/10.1109/ACSD.2005.13","url":null,"abstract":"The objective of this paper is to present how to design a system that can accommodate additional functionality with either no changes to the design or adding architectural modules without changing the implementation of the legacy functionality. This objective is very relevant to industrial domains where an architecture is designed before the full range of functionalities to support is known. We focus on an important aspect of the design of automotive systems: the scheduling problem for hard real time distributed embedded systems. Two metrics are used to capture the design goals. The metrics are optimized subject to a set of constraints within a mathematical programming framework. The cost of modifying a legacy system is characterized at an electrical control unit (ECU) component level. Results obtained in automotive applications show that the optimization framework is effective in reducing development and re-verification efforts after incremental design changes.","PeriodicalId":279517,"journal":{"name":"Fifth International Conference on Application of Concurrency to System Design (ACSD'05)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123875141","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Multicriteria optimisation problems occur naturally in engineering practices. Pareto analysis has proven to be a powerful tool to characterise potentially interesting realisations of a particular engineering problem for design-space exploration. Depending on the optimisation goals, one of the Pareto-optimal alternatives is the optimal realisation. It occurs however, that partial design decisions have to be taken, leaving other aspects of the optimisation problem to be decided at a later stage, and that Pareto-optimal configurations have to be composed (dynamically) from Pareto-optimal configurations of components. Both aspects are not supported by current analysis methods. This paper introduces a novel, algebraic approach to Pareto analysis. It allows for describing incremental design decisions and composing sets of Pareto-optimal configurations. The algebra can be used to study the operations on Pareto sets and the efficient computation of Pareto sets and their compositions.
{"title":"An algebra of Pareto points","authors":"M. Geilen, T. Basten, B. Theelen, R. Otten","doi":"10.1109/ACSD.2005.2","DOIUrl":"https://doi.org/10.1109/ACSD.2005.2","url":null,"abstract":"Multicriteria optimisation problems occur naturally in engineering practices. Pareto analysis has proven to be a powerful tool to characterise potentially interesting realisations of a particular engineering problem for design-space exploration. Depending on the optimisation goals, one of the Pareto-optimal alternatives is the optimal realisation. It occurs however, that partial design decisions have to be taken, leaving other aspects of the optimisation problem to be decided at a later stage, and that Pareto-optimal configurations have to be composed (dynamically) from Pareto-optimal configurations of components. Both aspects are not supported by current analysis methods. This paper introduces a novel, algebraic approach to Pareto analysis. It allows for describing incremental design decisions and composing sets of Pareto-optimal configurations. The algebra can be used to study the operations on Pareto sets and the efficient computation of Pareto sets and their compositions.","PeriodicalId":279517,"journal":{"name":"Fifth International Conference on Application of Concurrency to System Design (ACSD'05)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132068749","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A technique for the verification of concurrent parametric timed systems is presented. In the systems under study, each action has a bounded delay where the bounds are either constants or parameters. Given a safety property, the analysis computes automatically a set of constraints on the parameters sufficient to guarantee the property. The main contribution is an innovative representation of the parametric timed state space based on bit-vectors. Experimental results from the domain of timed circuits show that this representation improves both CPU time and memory usage with respect to another parametric approach, convex polyhedra.
{"title":"Verification of concurrent systems with parametric delays using octahedra","authors":"R. Clarisó, J. Cortadella","doi":"10.1109/ACSD.2005.34","DOIUrl":"https://doi.org/10.1109/ACSD.2005.34","url":null,"abstract":"A technique for the verification of concurrent parametric timed systems is presented. In the systems under study, each action has a bounded delay where the bounds are either constants or parameters. Given a safety property, the analysis computes automatically a set of constraints on the parameters sufficient to guarantee the property. The main contribution is an innovative representation of the parametric timed state space based on bit-vectors. Experimental results from the domain of timed circuits show that this representation improves both CPU time and memory usage with respect to another parametric approach, convex polyhedra.","PeriodicalId":279517,"journal":{"name":"Fifth International Conference on Application of Concurrency to System Design (ACSD'05)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130610690","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Delay-insensitive processes are typically implemented as asynchronous logic blocks; the possibility of transmission interference along the wires that connect them is considered to be a design error. Using DI-Algebra, the concepts of controllability, reflection, testing by interaction, and design by factorisation are explored. In general, a controllable process should be twice reflected so as to make it as abstract as possible.
{"title":"Controllable delay-insensitive processes and their reflection, interaction and factorisation","authors":"H. Kapoor, M. B. Josephs","doi":"10.1109/ACSD.2005.9","DOIUrl":"https://doi.org/10.1109/ACSD.2005.9","url":null,"abstract":"Delay-insensitive processes are typically implemented as asynchronous logic blocks; the possibility of transmission interference along the wires that connect them is considered to be a design error. Using DI-Algebra, the concepts of controllability, reflection, testing by interaction, and design by factorisation are explored. In general, a controllable process should be twice reflected so as to make it as abstract as possible.","PeriodicalId":279517,"journal":{"name":"Fifth International Conference on Application of Concurrency to System Design (ACSD'05)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125314281","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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