Pub Date : 1995-10-02DOI: 10.1109/ICCD.1995.528908
K. Srivatsan, C. Chakrabarti, L. Lucke
In many applications, such as digital signal processing, data format converters are used to reformat the data transferred between processing modules. In VLSI implementations, these converters consume a large portion of the available resources. Various methods have been proposed to synthesize data format converter architectures while optimizing the number of registers used to store the data. In this paper, we present a new register allocation scheme which not only minimizes the number of resistors, but also minimizes the power consumption in the data format converter. Low power data format converters are synthesized by minimizing the transitions and interconnections between the registers used to store the data. We present both a heuristic and an integer linear programming formulation to solve the allocation problem. Our method shows significant improvement over previous techniques.
{"title":"Low power data format converter design using semi-static register allocation","authors":"K. Srivatsan, C. Chakrabarti, L. Lucke","doi":"10.1109/ICCD.1995.528908","DOIUrl":"https://doi.org/10.1109/ICCD.1995.528908","url":null,"abstract":"In many applications, such as digital signal processing, data format converters are used to reformat the data transferred between processing modules. In VLSI implementations, these converters consume a large portion of the available resources. Various methods have been proposed to synthesize data format converter architectures while optimizing the number of registers used to store the data. In this paper, we present a new register allocation scheme which not only minimizes the number of resistors, but also minimizes the power consumption in the data format converter. Low power data format converters are synthesized by minimizing the transitions and interconnections between the registers used to store the data. We present both a heuristic and an integer linear programming formulation to solve the allocation problem. Our method shows significant improvement over previous techniques.","PeriodicalId":281907,"journal":{"name":"Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors","volume":"148 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129106153","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-10-02DOI: 10.1109/ICCD.1995.528928
G. Swamy, R. Brayton, V. Singhal
Computing the set of reachable states of a finite state machine, is an important component of many problems in the synthesis and formal verification of digital systems. The process of design is usually iterative, and the designer may modify and recompute information many times, and reachability is called each time the designer modifies the system because current methods for reachability analysis are not incremental. Unfortunately, the representation of the reachable states that is currently used in synthesis and verification, is inherently non updatable (O. Coudert and J.C. Madre, 1990). We solve this problem by presenting alternate ways to represent the reachable set, and incremental algorithms that can update the new representation each time the designer changes the system. The incremental algorithms use the reachable set computed at a previous iteration, and information about the changes to the system to update it, rather than compute the reachable set from the beginning. This results in computational savings, as demonstrated by the results.
{"title":"Incremental methods for FSM traversal","authors":"G. Swamy, R. Brayton, V. Singhal","doi":"10.1109/ICCD.1995.528928","DOIUrl":"https://doi.org/10.1109/ICCD.1995.528928","url":null,"abstract":"Computing the set of reachable states of a finite state machine, is an important component of many problems in the synthesis and formal verification of digital systems. The process of design is usually iterative, and the designer may modify and recompute information many times, and reachability is called each time the designer modifies the system because current methods for reachability analysis are not incremental. Unfortunately, the representation of the reachable states that is currently used in synthesis and verification, is inherently non updatable (O. Coudert and J.C. Madre, 1990). We solve this problem by presenting alternate ways to represent the reachable set, and incremental algorithms that can update the new representation each time the designer changes the system. The incremental algorithms use the reachable set computed at a previous iteration, and information about the changes to the system to update it, rather than compute the reachable set from the beginning. This results in computational savings, as demonstrated by the results.","PeriodicalId":281907,"journal":{"name":"Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129137931","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-10-02DOI: 10.1109/ICCD.1995.528816
Jin-Tai Yan
In this paper, we firstly propose a k-way connection-oriented net model, chain net model, to generalize the cut analysis for k-way circuit partitioning and to reduce the complexity of edges for the representation of a multiple-pin net between the transformation of a hypergraph and an edge-weighted graph. Furthermore, based on the techniques of fuzzy c-means clustering, we develop and propose fuzzy c-means graph clustering to obtain k groups of fuzzy memberships for the vertices in the mapped graph according to the global information of all the net connections. Finally, by the area information of any cell in the circuit netlist, these k groups of fuzzy memberships will lead to a cut-driven or balance-driven k-way circuit partitioning. As a result, k-way circuit partitioning has been implemented for testing MCNC circuit benchmarks and the experimental results show that the proposed partitioning approach generates effective results on the partitioning cut and the partitioning balance for these benchmarks.
{"title":"Connection-oriented net model and fuzzy clustering techniques for K-way circuit partitioning","authors":"Jin-Tai Yan","doi":"10.1109/ICCD.1995.528816","DOIUrl":"https://doi.org/10.1109/ICCD.1995.528816","url":null,"abstract":"In this paper, we firstly propose a k-way connection-oriented net model, chain net model, to generalize the cut analysis for k-way circuit partitioning and to reduce the complexity of edges for the representation of a multiple-pin net between the transformation of a hypergraph and an edge-weighted graph. Furthermore, based on the techniques of fuzzy c-means clustering, we develop and propose fuzzy c-means graph clustering to obtain k groups of fuzzy memberships for the vertices in the mapped graph according to the global information of all the net connections. Finally, by the area information of any cell in the circuit netlist, these k groups of fuzzy memberships will lead to a cut-driven or balance-driven k-way circuit partitioning. As a result, k-way circuit partitioning has been implemented for testing MCNC circuit benchmarks and the experimental results show that the proposed partitioning approach generates effective results on the partitioning cut and the partitioning balance for these benchmarks.","PeriodicalId":281907,"journal":{"name":"Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114136066","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-10-02DOI: 10.1109/ICCD.1995.528803
J. Adams, J. Miller, D. E. Thomas
This paper presents a technique for back-annotating the results of high-level synthesis into the source description to produce a timing-accurate behavioral simulation model. The resulting simulation model exhibits the same cycle-by-cycle behavior as a register-transfer level model, but can be simulated in a fraction of the time. This idea has analogies both to software profiling and to back-annotation at lower levels of hardware design. Experimental results demonstrate that the annotated behavioral simulation models run two to three orders of magnitude faster than register-transfer level simulation models, and only about an order of magnitude slower than behavioral models with no timing information.
{"title":"Execution-time profiling for multiple-process behavioral synthesis","authors":"J. Adams, J. Miller, D. E. Thomas","doi":"10.1109/ICCD.1995.528803","DOIUrl":"https://doi.org/10.1109/ICCD.1995.528803","url":null,"abstract":"This paper presents a technique for back-annotating the results of high-level synthesis into the source description to produce a timing-accurate behavioral simulation model. The resulting simulation model exhibits the same cycle-by-cycle behavior as a register-transfer level model, but can be simulated in a fraction of the time. This idea has analogies both to software profiling and to back-annotation at lower levels of hardware design. Experimental results demonstrate that the annotated behavioral simulation models run two to three orders of magnitude faster than register-transfer level simulation models, and only about an order of magnitude slower than behavioral models with no timing information.","PeriodicalId":281907,"journal":{"name":"Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors","volume":"341 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124214972","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-10-02DOI: 10.1109/ICCD.1995.528844
B. Hosticka
This paper discusses problems of integrated system design. It is shown what is the current state of the art and where are the deficits. Finally, recommendations for future development of design support are given.
{"title":"Toward integrated system design: a global perspective","authors":"B. Hosticka","doi":"10.1109/ICCD.1995.528844","DOIUrl":"https://doi.org/10.1109/ICCD.1995.528844","url":null,"abstract":"This paper discusses problems of integrated system design. It is shown what is the current state of the art and where are the deficits. Finally, recommendations for future development of design support are given.","PeriodicalId":281907,"journal":{"name":"Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125216859","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-10-02DOI: 10.1109/ICCD.1995.528800
Hong Hao, K. Bhabuthmal
This paper describes the SuperSPARC II clock controller. This controller allows the internal clock to be disabled during the chip's normal operation. Then any number of internal clock pulses can be issued in a controlled fashion. The clock can return to the free running mode after being disabled. All clock control is done in a way that produces no glitches on the internal clock signal The clock controller can be accessed through the IEEE 1149.1 interface, making it useful at the chip level and at the module or system level.
{"title":"Clock controller design in SuperSPARC II microprocessor","authors":"Hong Hao, K. Bhabuthmal","doi":"10.1109/ICCD.1995.528800","DOIUrl":"https://doi.org/10.1109/ICCD.1995.528800","url":null,"abstract":"This paper describes the SuperSPARC II clock controller. This controller allows the internal clock to be disabled during the chip's normal operation. Then any number of internal clock pulses can be issued in a controlled fashion. The clock can return to the free running mode after being disabled. All clock control is done in a way that produces no glitches on the internal clock signal The clock controller can be accessed through the IEEE 1149.1 interface, making it useful at the chip level and at the module or system level.","PeriodicalId":281907,"journal":{"name":"Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123802412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-10-02DOI: 10.1109/ICCD.1995.528904
I. Radivojevic, F. Brewer
Optimization of hardware resources for conditional data-flow graph behavior is particularly important when conditional behavior occurs in cyclic loops and maximization of throughput is desired. In this paper, an exact and efficient conditional resource sharing analysis using a guardbased control representation is presented. The analysis is transparent to a scheduler implementation. The proposed technique systematically handles complex conditional resource sharing for cases when folded (software pipelined) loops include conditional behavior within the loop body.
{"title":"Analysis of conditional resource sharing using a guard-based control representation","authors":"I. Radivojevic, F. Brewer","doi":"10.1109/ICCD.1995.528904","DOIUrl":"https://doi.org/10.1109/ICCD.1995.528904","url":null,"abstract":"Optimization of hardware resources for conditional data-flow graph behavior is particularly important when conditional behavior occurs in cyclic loops and maximization of throughput is desired. In this paper, an exact and efficient conditional resource sharing analysis using a guardbased control representation is presented. The analysis is transparent to a scheduler implementation. The proposed technique systematically handles complex conditional resource sharing for cases when folded (software pipelined) loops include conditional behavior within the loop body.","PeriodicalId":281907,"journal":{"name":"Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors","volume":"186 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116193094","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-10-02DOI: 10.1109/ICCD.1995.528793
S. Campos, E. Clarke, W. Marrero, M. Minea
Symbolic model checking is a successful technique for checking properties of large finite-state systems. This method has been used to verify a number of real-world hardware designs; however it is not able to determine timing or performance properties directly. Since these properties are extremely important in the design of high-performance systems and in time-critical applications, we have extended model checking techniques to produce timing information. Our results allow a more detailed analysis of a model than is possible with tools that simply determine whether a property is satisfied or not. We present algorithms that determine the exact bounds on the time interval between two specified events and the number of occurrences of another event in such an interval. To demonstrate how our method works, we have modelled the PCI local bus and analyzed its temporal behavior. The results demonstrate the usefulness of our technique in analyzing complex modem designs.
{"title":"Verifying the performance of the PCI local bus using symbolic techniques","authors":"S. Campos, E. Clarke, W. Marrero, M. Minea","doi":"10.1109/ICCD.1995.528793","DOIUrl":"https://doi.org/10.1109/ICCD.1995.528793","url":null,"abstract":"Symbolic model checking is a successful technique for checking properties of large finite-state systems. This method has been used to verify a number of real-world hardware designs; however it is not able to determine timing or performance properties directly. Since these properties are extremely important in the design of high-performance systems and in time-critical applications, we have extended model checking techniques to produce timing information. Our results allow a more detailed analysis of a model than is possible with tools that simply determine whether a property is satisfied or not. We present algorithms that determine the exact bounds on the time interval between two specified events and the number of occurrences of another event in such an interval. To demonstrate how our method works, we have modelled the PCI local bus and analyzed its temporal behavior. The results demonstrate the usefulness of our technique in analyzing complex modem designs.","PeriodicalId":281907,"journal":{"name":"Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors","volume":"288 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132490614","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-10-02DOI: 10.1109/ICCD.1995.528823
A. Yousif, J. Gu
The test generation problem for combinational circuits is known to be NP-hard. Efficient techniques for test generation are essential in order to reduce the test generation time. In this paper, we present a new and efficient test generation system based on global computations techniques. We aim at reducing the test generation time by using concurrent search to find tests for more than one fault at a time as opposed to the single target fault technique used by current test systems. In order to achieve our objective, a new, model for test generation is presented. We present a formal definition for the new test generation model and an implementation for the test generation system. Experimental results using ISCAS'85 and ISCAS'89 benchmarks are also presented.
{"title":"Concurrent automatic test pattern generation algorithm for combinational circuits","authors":"A. Yousif, J. Gu","doi":"10.1109/ICCD.1995.528823","DOIUrl":"https://doi.org/10.1109/ICCD.1995.528823","url":null,"abstract":"The test generation problem for combinational circuits is known to be NP-hard. Efficient techniques for test generation are essential in order to reduce the test generation time. In this paper, we present a new and efficient test generation system based on global computations techniques. We aim at reducing the test generation time by using concurrent search to find tests for more than one fault at a time as opposed to the single target fault technique used by current test systems. In order to achieve our objective, a new, model for test generation is presented. We present a formal definition for the new test generation model and an implementation for the test generation system. Experimental results using ISCAS'85 and ISCAS'89 benchmarks are also presented.","PeriodicalId":281907,"journal":{"name":"Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126446114","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-10-02DOI: 10.1109/ICCD.1995.528829
Jean-Paul Theis, L. Thiele
In this paper, we describe a new processor model called Periodic Operation Model (POM) that is suitable for real time image processing. First we analyze existing image processing systems in order to situate our approach. Starting from the processor architecture, we derive the corresponding algorithm class by means of a novel hardware description. Then we address the allocation and scheduling problem. We show that allocation and scheduling can be decoupled in the mapping process related to POM-processor arrays and outline the principles of an optimal mapping trajectory. We describe the outline of a novel ILP-model for allocation of POM-processor arrays which takes into account array-topology and bus bandwidth constraints. Finally we discuss implementational aspects of the POM as well as applications in image processing. We especially show that POM-processor arrays can be integrated onto single chips, thereby allowing to achieve several GOPS processing power per chip.
{"title":"POM: a processor model for image processing","authors":"Jean-Paul Theis, L. Thiele","doi":"10.1109/ICCD.1995.528829","DOIUrl":"https://doi.org/10.1109/ICCD.1995.528829","url":null,"abstract":"In this paper, we describe a new processor model called Periodic Operation Model (POM) that is suitable for real time image processing. First we analyze existing image processing systems in order to situate our approach. Starting from the processor architecture, we derive the corresponding algorithm class by means of a novel hardware description. Then we address the allocation and scheduling problem. We show that allocation and scheduling can be decoupled in the mapping process related to POM-processor arrays and outline the principles of an optimal mapping trajectory. We describe the outline of a novel ILP-model for allocation of POM-processor arrays which takes into account array-topology and bus bandwidth constraints. Finally we discuss implementational aspects of the POM as well as applications in image processing. We especially show that POM-processor arrays can be integrated onto single chips, thereby allowing to achieve several GOPS processing power per chip.","PeriodicalId":281907,"journal":{"name":"Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125303672","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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