Pub Date : 2005-06-27DOI: 10.1108/09540910610665080
K. T. Tsai, F. Liu, E. Wong, R. Rajoo
Understanding the response of the board-to-package (2nd level) interconnections to loading at high strain rates is essential for the design against drop impact failure. To obtain such properties, the impact tester used must provide results for energy to failure and information on impact force and displacement. Knowledge of impact force is essential for quantifying the strength of the interconnection and allows quantitative design against failure. It also allows one-to-one comparison with the failure force measured in a standard quasi-static shear test. This paper reports on a newly-developed micro-impact tester that is capable of registering the dynamic impact force and displacement during the high-strain rate loading of an interconnection. The micro-impact tester was used to evaluate the high strain-rate characteristics of various types of solder interconnections. The interconnections were varied with respect to the type of leaded and lead-free solder alloys, thermal histories, pad finishes and pad definitions. The following observations have been made with regard to the peak loads and failure modes obtained in both static shear tests and high strain rate impact tests: 1) Peak loads obtained from impact tests are between 30% to 100% higher than that obtained from static shear tests for all combinations of solder alloy and pad finish; 2) The SnPb solder alloy had the maximum energy to failure for all pad finishes. Of all the lead-free solders, the SnAg solder alloy had the highest energy to failure; 3) Static shearing induces only bulk solder failure for all combinations of solder alloy and pad finish. Impact testing tends to induce bulk solder failure for SnPb solder and a mixture of bulk and intermetallic failure in all the lead-free solder alloys for all pad finishes; and 4) In general, the peak loads obtained for NSMD pads are significantly lower than that for SMD pads. The results obtained so far have highlighted the vulnerability of NSMD pads to drop impact. This is especially important as I/O pitch is ever decreasing, which will inevitably force pad design to become NSMD due to the more lenient design rules. In addition, the risk of cratering failure will be likely to increase with decreasing pad size
{"title":"High Strain Rate Testing of Solder Interconnections","authors":"K. T. Tsai, F. Liu, E. Wong, R. Rajoo","doi":"10.1108/09540910610665080","DOIUrl":"https://doi.org/10.1108/09540910610665080","url":null,"abstract":"Understanding the response of the board-to-package (2nd level) interconnections to loading at high strain rates is essential for the design against drop impact failure. To obtain such properties, the impact tester used must provide results for energy to failure and information on impact force and displacement. Knowledge of impact force is essential for quantifying the strength of the interconnection and allows quantitative design against failure. It also allows one-to-one comparison with the failure force measured in a standard quasi-static shear test. This paper reports on a newly-developed micro-impact tester that is capable of registering the dynamic impact force and displacement during the high-strain rate loading of an interconnection. The micro-impact tester was used to evaluate the high strain-rate characteristics of various types of solder interconnections. The interconnections were varied with respect to the type of leaded and lead-free solder alloys, thermal histories, pad finishes and pad definitions. The following observations have been made with regard to the peak loads and failure modes obtained in both static shear tests and high strain rate impact tests: 1) Peak loads obtained from impact tests are between 30% to 100% higher than that obtained from static shear tests for all combinations of solder alloy and pad finish; 2) The SnPb solder alloy had the maximum energy to failure for all pad finishes. Of all the lead-free solders, the SnAg solder alloy had the highest energy to failure; 3) Static shearing induces only bulk solder failure for all combinations of solder alloy and pad finish. Impact testing tends to induce bulk solder failure for SnPb solder and a mixture of bulk and intermetallic failure in all the lead-free solder alloys for all pad finishes; and 4) In general, the peak loads obtained for NSMD pads are significantly lower than that for SMD pads. The results obtained so far have highlighted the vulnerability of NSMD pads to drop impact. This is especially important as I/O pitch is ever decreasing, which will inevitably force pad design to become NSMD due to the more lenient design rules. In addition, the risk of cratering failure will be likely to increase with decreasing pad size","PeriodicalId":282857,"journal":{"name":"2005 Conference on High Density Microsystem Design and Packaging and Component Failure Analysis","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115339389","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Air impingement cooling, as a potential air-cooling technique, has been shown to be much efficient and enabled to complement conventional forced convective air-cooling in electronics. To provide reliable references to the computational thermal analyses based on CFD for effective air-cooling technique integrated in microsystem electronics packaging, the numerical simulation based on CFD for air impingement heat transfer is conducted in the case of axisymmetric impinging jet by adopting various turbulence models and wall functions. The results indicate that the inherent disadvantage of the overpredictions of the turbulent kinetic energy and heat transfer rate in the stagnation region for the standard and realizable k-epsiv turbulence models primarily depends on the improper modeling of the source term in the transport equation of the turbulent energy dissipation rate, rather than the isotropic eddy viscosity assumption and high pressure gradient in the vicinity of the stagnation point. The RNG k-epsiv turbulence model greatly improves the prediction accuracy of the turbulent viscosity and heat transfer rate in the stagnation region and seems to be preferable not only to the standard and realizable k-epsiv turbulence models but also to advanced Reynolds stress turbulence model to some extent in respect to the prediction capability with respect to the turbulence and heat transfer characteristics for such an axisymmetric impinging jet
{"title":"Numerical Investigation Based on CFD for Air Impingement Heat Transfer in Electronics Cooling","authors":"Yan Zhang, Jing-yu Fan, J. Liu","doi":"10.1109/HDP.2005.251424","DOIUrl":"https://doi.org/10.1109/HDP.2005.251424","url":null,"abstract":"Air impingement cooling, as a potential air-cooling technique, has been shown to be much efficient and enabled to complement conventional forced convective air-cooling in electronics. To provide reliable references to the computational thermal analyses based on CFD for effective air-cooling technique integrated in microsystem electronics packaging, the numerical simulation based on CFD for air impingement heat transfer is conducted in the case of axisymmetric impinging jet by adopting various turbulence models and wall functions. The results indicate that the inherent disadvantage of the overpredictions of the turbulent kinetic energy and heat transfer rate in the stagnation region for the standard and realizable k-epsiv turbulence models primarily depends on the improper modeling of the source term in the transport equation of the turbulent energy dissipation rate, rather than the isotropic eddy viscosity assumption and high pressure gradient in the vicinity of the stagnation point. The RNG k-epsiv turbulence model greatly improves the prediction accuracy of the turbulent viscosity and heat transfer rate in the stagnation region and seems to be preferable not only to the standard and realizable k-epsiv turbulence models but also to advanced Reynolds stress turbulence model to some extent in respect to the prediction capability with respect to the turbulence and heat transfer characteristics for such an axisymmetric impinging jet","PeriodicalId":282857,"journal":{"name":"2005 Conference on High Density Microsystem Design and Packaging and Component Failure Analysis","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129846031","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Kawamoto, O. Suzuki, Y. Abe, H. Yoshii, T. Fujiki, F. Tanaka
Recently, most of semiconductor companies are developing high density packages using lead free solder and low-k layer. The melting temperature of lead free solder is higher than the eutectic solder. Therefore, the reflow profile for lead free solder is higher approximately 30 degrees C than the conventional profile. When a high temperature profile is used, the organic substrate is expanded and the package stress becomes higher. Furthermore, bump cracking by the package stress is concerned, because lead free solder is very fragile. In addition, it is easy to destroy the low-k layer by the package stress such as the package's warpage. Thus the stress control is necessary for the assembly process of high density packages using lead free solder and low-k layer. It is effective to use no-flow underfill (NUF) with local reflow process using a flip chip bonder (FCB). This process can realize an assembly with lower stress compared with capillary flow underfill (CUF) reflow process, because the organic substrate should not be exposed to a high temperature and is controlled not to expand much. NUF characteristics for local reflow process are investigated. At first, NUF curability and the influence of flux-ability for the solder connection were evaluated using NUF which was based on the epoxy resin and different kinds of hardeners. It was confirmed that solder connection was affected by NUF curability and the flux-ability were influenced by the hardener type. Then filler loading level was optimized to reinforce the solder joint. We improved the mismatch between IC chip and substrate in the C.T.E (coefficient of thermal expansion). NUF of various filler contents were evaluated under reliability tests such as moisture reflow test, temperature cycle test, and high temperature/high humidity test. Finally the package stress with a low stress NUF was evaluated by shadow moire technique. As a result, it was confirmed that the package by local reflow process had a lower stress than the package by conventional process
{"title":"Fundamental Research of No-Flow UF for Low Stress Flip-Chip Package","authors":"S. Kawamoto, O. Suzuki, Y. Abe, H. Yoshii, T. Fujiki, F. Tanaka","doi":"10.1109/HDP.2005.251388","DOIUrl":"https://doi.org/10.1109/HDP.2005.251388","url":null,"abstract":"Recently, most of semiconductor companies are developing high density packages using lead free solder and low-k layer. The melting temperature of lead free solder is higher than the eutectic solder. Therefore, the reflow profile for lead free solder is higher approximately 30 degrees C than the conventional profile. When a high temperature profile is used, the organic substrate is expanded and the package stress becomes higher. Furthermore, bump cracking by the package stress is concerned, because lead free solder is very fragile. In addition, it is easy to destroy the low-k layer by the package stress such as the package's warpage. Thus the stress control is necessary for the assembly process of high density packages using lead free solder and low-k layer. It is effective to use no-flow underfill (NUF) with local reflow process using a flip chip bonder (FCB). This process can realize an assembly with lower stress compared with capillary flow underfill (CUF) reflow process, because the organic substrate should not be exposed to a high temperature and is controlled not to expand much. NUF characteristics for local reflow process are investigated. At first, NUF curability and the influence of flux-ability for the solder connection were evaluated using NUF which was based on the epoxy resin and different kinds of hardeners. It was confirmed that solder connection was affected by NUF curability and the flux-ability were influenced by the hardener type. Then filler loading level was optimized to reinforce the solder joint. We improved the mismatch between IC chip and substrate in the C.T.E (coefficient of thermal expansion). NUF of various filler contents were evaluated under reliability tests such as moisture reflow test, temperature cycle test, and high temperature/high humidity test. Finally the package stress with a low stress NUF was evaluated by shadow moire technique. As a result, it was confirmed that the package by local reflow process had a lower stress than the package by conventional process","PeriodicalId":282857,"journal":{"name":"2005 Conference on High Density Microsystem Design and Packaging and Component Failure Analysis","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128526412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The delamination of five-die stacked package with high humidity and high temperature processes was studied by experiments and finite element analysis in the paper. The package were tested by 85degC/85H/196hr condition and followed by solder reflow process. The testing results showed that the delamination was prevalent in samples. Combing the failure analysis of the stack-die package, the finite element analysis was carried out to explain the moisture assist delamination in stacked-die package. The steam pressure in defect void was accounted for in the computations and the energy release rate involving thermal and moisture concentration was discussed as well
{"title":"Moisture assist delamination in multiple die stacked package","authors":"Jun Wang, Jing Gu, Lei Jiang, F. Xiao, B. Shao","doi":"10.1109/HDP.2005.251401","DOIUrl":"https://doi.org/10.1109/HDP.2005.251401","url":null,"abstract":"The delamination of five-die stacked package with high humidity and high temperature processes was studied by experiments and finite element analysis in the paper. The package were tested by 85degC/85H/196hr condition and followed by solder reflow process. The testing results showed that the delamination was prevalent in samples. Combing the failure analysis of the stack-die package, the finite element analysis was carried out to explain the moisture assist delamination in stacked-die package. The steam pressure in defect void was accounted for in the computations and the energy release rate involving thermal and moisture concentration was discussed as well","PeriodicalId":282857,"journal":{"name":"2005 Conference on High Density Microsystem Design and Packaging and Component Failure Analysis","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129011819","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The static partitioning algorithm and assigning were generally researched respectively, which has largely resulted in the deficiency in the workload balance of the static partitioning. A new partitioning scheme of parallel VHDL simulation is presented in the paper. Partitioning and assigning both are processed just before the simulation in the scheme, and are included in the running phase. Because of this, it strictly requests that the time complexity of partitioning algorithm is minimum. A new static partitioning algorithm, fan-out right partitioning algorithm, which has a lower time complexity and good performance, is presented in the paper. The experiment result shows that the performance of parallel VHDL simulation is improved with this scheme and partitioning algorithm
{"title":"A New Partitioning Scheme of Parallel VHDL Simulation","authors":"Wu Yue, Jian Ling, Yang Hong-bin, L. Zongtian","doi":"10.1109/HDP.2005.251452","DOIUrl":"https://doi.org/10.1109/HDP.2005.251452","url":null,"abstract":"The static partitioning algorithm and assigning were generally researched respectively, which has largely resulted in the deficiency in the workload balance of the static partitioning. A new partitioning scheme of parallel VHDL simulation is presented in the paper. Partitioning and assigning both are processed just before the simulation in the scheme, and are included in the running phase. Because of this, it strictly requests that the time complexity of partitioning algorithm is minimum. A new static partitioning algorithm, fan-out right partitioning algorithm, which has a lower time complexity and good performance, is presented in the paper. The experiment result shows that the performance of parallel VHDL simulation is improved with this scheme and partitioning algorithm","PeriodicalId":282857,"journal":{"name":"2005 Conference on High Density Microsystem Design and Packaging and Component Failure Analysis","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124359989","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Zhou Qi-hong, He Yong-yi, Guo Shuai, Fang Ming-lun
Tension control is difficult and pivotal in lots of fields. This paper mainly discusses the design of intelligent tension controller by a novel 16-bit DSP module. DSP is designed to meet the need of control field. It can be used in some fields such as multi-lines cutting of microsystems manufacturing. Intelligent fuzzy-PID algorithm is adopted. This paper takes let-off and take-up control system of rapier loom for example and discusses how to design DSP-based intelligent tension controller. From the given experiment, test results show that the DSP-based fuzzy-PID intelligent controller has superior performance. It can be used widely to control tension in different fields
{"title":"DSP-Based Intelligent Tension Controller","authors":"Zhou Qi-hong, He Yong-yi, Guo Shuai, Fang Ming-lun","doi":"10.1109/HDP.2005.251461","DOIUrl":"https://doi.org/10.1109/HDP.2005.251461","url":null,"abstract":"Tension control is difficult and pivotal in lots of fields. This paper mainly discusses the design of intelligent tension controller by a novel 16-bit DSP module. DSP is designed to meet the need of control field. It can be used in some fields such as multi-lines cutting of microsystems manufacturing. Intelligent fuzzy-PID algorithm is adopted. This paper takes let-off and take-up control system of rapier loom for example and discusses how to design DSP-based intelligent tension controller. From the given experiment, test results show that the DSP-based fuzzy-PID intelligent controller has superior performance. It can be used widely to control tension in different fields","PeriodicalId":282857,"journal":{"name":"2005 Conference on High Density Microsystem Design and Packaging and Component Failure Analysis","volume":"2017 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128008531","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Li Jian-ping, Huo Jun-ya, Wang Fu-liang, Han Lei, Zhong Jue
The stability and the delay time of the scan working model trigger system and the interrupt working model trigger system were compared and studied by the experiment of synchronization trigger of the thermosonic flip-chip bonding. It is found that the interrupt working model trigger system's stability was better than the scan working model trigger system's. It's biggest delay time, average delay time and the standard deviation of the delay time were all shorter than the scan working model trigger system's, especially the standard deviation just as small as 0.5mus. The result indicates that the delay time of the interrupt working model trigger system is 9mus less than a time cycle of the thermosonic and it's every time's delay time is invariableness. The interrupt working model trigger system is superior to the scan working model trigger system. It is also confirmed that the interrupt working model trigger system can used as a precise synchronization trigger system by triggering the thermosonic flip-chip bonding's data acquisition system, the press measure system and the polytec vibration measure system
{"title":"Synchronization Trigger System Design of the Thermosonic Flip-chip Bonding","authors":"Li Jian-ping, Huo Jun-ya, Wang Fu-liang, Han Lei, Zhong Jue","doi":"10.1109/HDP.2005.251377","DOIUrl":"https://doi.org/10.1109/HDP.2005.251377","url":null,"abstract":"The stability and the delay time of the scan working model trigger system and the interrupt working model trigger system were compared and studied by the experiment of synchronization trigger of the thermosonic flip-chip bonding. It is found that the interrupt working model trigger system's stability was better than the scan working model trigger system's. It's biggest delay time, average delay time and the standard deviation of the delay time were all shorter than the scan working model trigger system's, especially the standard deviation just as small as 0.5mus. The result indicates that the delay time of the interrupt working model trigger system is 9mus less than a time cycle of the thermosonic and it's every time's delay time is invariableness. The interrupt working model trigger system is superior to the scan working model trigger system. It is also confirmed that the interrupt working model trigger system can used as a precise synchronization trigger system by triggering the thermosonic flip-chip bonding's data acquisition system, the press measure system and the polytec vibration measure system","PeriodicalId":282857,"journal":{"name":"2005 Conference on High Density Microsystem Design and Packaging and Component Failure Analysis","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128081354","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Shen, T. Koivisto, T. Peltonen, Lirong Zheng, E. Tjukanoff, H. Tenhunen
In this paper, we designed an impulse-based ultra wideband (UWB) radio module (low band) for wireless intelligent system applications such as radio frequency identification (RFID) and wireless sensor networks (WSN). The UWB radio module includes transceiver block, baseband process unit and power management block. The transceiver circuits include Gaussian pulse generator, wideband low noise amplifier (LNA), multiplier, integrator and timing circuits, which use 0.18mum, 1P6M CMOS technology. The wideband LNA has a power gain of 10dB and minimum noise figure of 2.7dB. For UWB transceiver, the power consumption of transmitter is lower than 1mW while the receiver is about 23mW. The liquid-crystal-polymer (LCP)-based system-on-package (SoP) technology is used to implement the UWB radio module for low power, low cost and small size
{"title":"UWB Radio Module Design for Wireless Intelligent Systems-From Specification to Implementation","authors":"M. Shen, T. Koivisto, T. Peltonen, Lirong Zheng, E. Tjukanoff, H. Tenhunen","doi":"10.1109/HDP.2005.251423","DOIUrl":"https://doi.org/10.1109/HDP.2005.251423","url":null,"abstract":"In this paper, we designed an impulse-based ultra wideband (UWB) radio module (low band) for wireless intelligent system applications such as radio frequency identification (RFID) and wireless sensor networks (WSN). The UWB radio module includes transceiver block, baseband process unit and power management block. The transceiver circuits include Gaussian pulse generator, wideband low noise amplifier (LNA), multiplier, integrator and timing circuits, which use 0.18mum, 1P6M CMOS technology. The wideband LNA has a power gain of 10dB and minimum noise figure of 2.7dB. For UWB transceiver, the power consumption of transmitter is lower than 1mW while the receiver is about 23mW. The liquid-crystal-polymer (LCP)-based system-on-package (SoP) technology is used to implement the UWB radio module for low power, low cost and small size","PeriodicalId":282857,"journal":{"name":"2005 Conference on High Density Microsystem Design and Packaging and Component Failure Analysis","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128146853","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Chen Wenwei, Zhang Jinyi, Li Jiao, R. Xiaojun, L. Jiwei
The demands for more powerful products and the huge capacity of today' s silicon technology move system-on-chip (SoC) designs from the leading-age to mainstream design practice. The one at the very top of the list of challenges to be solved for SoC design is verification. General agreement among many observers is that verification consumes at least 70 percent of whole design percent. SoC verification involves in multi-levels: IP level verification, chip level verification, and hardware/software (HW/SW) co-verification. The last one is the key point to the whole verification process, and some of EDA vendors have provided several EDA tools for HW/SW co-verification. In this paper, the author analyses the architecture of co-verification and the weakness of existing EDA tools, then presents a practical verification strategy based on FPGA, which is more flexible and convenient, and more efficient than traditional verification methods whose hardware and software verification are separate. An experimental result, VAD (video add data) SoC verification, is given as well finally
{"title":"Study On a Mixed Verification Strategy for IP-Based SoC Design","authors":"Chen Wenwei, Zhang Jinyi, Li Jiao, R. Xiaojun, L. Jiwei","doi":"10.1109/HDP.2005.251451","DOIUrl":"https://doi.org/10.1109/HDP.2005.251451","url":null,"abstract":"The demands for more powerful products and the huge capacity of today' s silicon technology move system-on-chip (SoC) designs from the leading-age to mainstream design practice. The one at the very top of the list of challenges to be solved for SoC design is verification. General agreement among many observers is that verification consumes at least 70 percent of whole design percent. SoC verification involves in multi-levels: IP level verification, chip level verification, and hardware/software (HW/SW) co-verification. The last one is the key point to the whole verification process, and some of EDA vendors have provided several EDA tools for HW/SW co-verification. In this paper, the author analyses the architecture of co-verification and the weakness of existing EDA tools, then presents a practical verification strategy based on FPGA, which is more flexible and convenient, and more efficient than traditional verification methods whose hardware and software verification are separate. An experimental result, VAD (video add data) SoC verification, is given as well finally","PeriodicalId":282857,"journal":{"name":"2005 Conference on High Density Microsystem Design and Packaging and Component Failure Analysis","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125455691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Yingjun Cheng, Gaowei Xu, Dapeng Zhu, Wei Xu, L. Luo
By applying vacuum physics to typical solder reflow vacuum packaging process of MEMS devices, the mathematical and physical model of the vacuum degree change of the cavity to be sealed in related with the gas absorption, desorption, penetration, flowage through little pipe and vapour pressure of materials was established and its arithmetic was ascertained with numerical simulation method. A software module with friendly interface was developed by Visual C++ programming, which comprises results view and parameters input interfaces such as gas parameters input, packaging structure input, reflow time and heating profile input and gas discharging performance input. The veracity of the simulation results was validated by a simulated vacuum packaging experiment, and the effects of the size of capillary pipe and heating profile of solder reflow process on vacuum degree were analyzed based on the simulation results. The parametrical modeling, simulation and optimization design of vacuum packaging process of MEMS devices was realized
{"title":"Vacuum Packaging Process Simulation for MEMS Devices","authors":"Yingjun Cheng, Gaowei Xu, Dapeng Zhu, Wei Xu, L. Luo","doi":"10.1109/HDP.2005.251444","DOIUrl":"https://doi.org/10.1109/HDP.2005.251444","url":null,"abstract":"By applying vacuum physics to typical solder reflow vacuum packaging process of MEMS devices, the mathematical and physical model of the vacuum degree change of the cavity to be sealed in related with the gas absorption, desorption, penetration, flowage through little pipe and vapour pressure of materials was established and its arithmetic was ascertained with numerical simulation method. A software module with friendly interface was developed by Visual C++ programming, which comprises results view and parameters input interfaces such as gas parameters input, packaging structure input, reflow time and heating profile input and gas discharging performance input. The veracity of the simulation results was validated by a simulated vacuum packaging experiment, and the effects of the size of capillary pipe and heating profile of solder reflow process on vacuum degree were analyzed based on the simulation results. The parametrical modeling, simulation and optimization design of vacuum packaging process of MEMS devices was realized","PeriodicalId":282857,"journal":{"name":"2005 Conference on High Density Microsystem Design and Packaging and Component Failure Analysis","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131609516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：