Pub Date : 2001-06-13DOI: 10.1109/EMRTS.2001.934009
I. Broster, A. Burns
The presence of network errors such as electrical interference affects the timing properties of a CAN (Controller Area Network) bus. In hard real-time systems it is often better to not receive a message than to receive it too late. Aborting late messages is a form of real-time error confinement which prevents late messages affecting the timeliness of other messages and processes. This can be used to help guarantee hard real-time performance in a distributed system using CAN in the presence of unbounded network errors.
{"title":"Timely use of the CAN protocol in critical hard real-time systems with faults","authors":"I. Broster, A. Burns","doi":"10.1109/EMRTS.2001.934009","DOIUrl":"https://doi.org/10.1109/EMRTS.2001.934009","url":null,"abstract":"The presence of network errors such as electrical interference affects the timing properties of a CAN (Controller Area Network) bus. In hard real-time systems it is often better to not receive a message than to receive it too late. Aborting late messages is a form of real-time error confinement which prevents late messages affecting the timeliness of other messages and processes. This can be used to help guarantee hard real-time performance in a distributed system using CAN in the presence of unbounded network errors.","PeriodicalId":292136,"journal":{"name":"Proceedings 13th Euromicro Conference on Real-Time Systems","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123636255","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-06-13DOI: 10.1109/EMRTS.2001.934004
James H. Anderson, A. Srinivasan
In this paper, we prove that a simplified variant of the PD Pfair algorithm, called PD/sup 2/, is optimal for scheduling any mix of early-release and non-early-release asynchronous tasks on a multiprocessor. This result breaks new ground by incorporating both early-release and non-early-release tasks under a common framework. In addition, all prior work on optimal multiprocessor Pfair scheduling algorithms has been limited to synchronous periodic task systems.
{"title":"Mixed Pfair/ERfair scheduling of asynchronous periodic tasks","authors":"James H. Anderson, A. Srinivasan","doi":"10.1109/EMRTS.2001.934004","DOIUrl":"https://doi.org/10.1109/EMRTS.2001.934004","url":null,"abstract":"In this paper, we prove that a simplified variant of the PD Pfair algorithm, called PD/sup 2/, is optimal for scheduling any mix of early-release and non-early-release asynchronous tasks on a multiprocessor. This result breaks new ground by incorporating both early-release and non-early-release tasks under a common framework. In addition, all prior work on optimal multiprocessor Pfair scheduling algorithms has been limited to synchronous periodic task systems.","PeriodicalId":292136,"journal":{"name":"Proceedings 13th Euromicro Conference on Real-Time Systems","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126236355","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-06-13DOI: 10.1109/EMRTS.2001.933993
R. Kirner, P. Puschner
Performing worst-case execution time (WCET) analysis on machine code with program path annotation provided at high-level source code level requires the transformation of path annotations from the source-code level to assembly/object-code level. This path-information transformation can be done outside or integrated into the compiler during code compilation. The first approach is easier to implement but lacks for the support of strong code optimizations performed by the compiler because the external tool would have to make guesses about optimizations. In this paper we present an approach for the program code compilation that integrates the transformation of program path information into the compiler. Path information is transformed through all compiler stages to the adequate path information for the corresponding assembly code level. The WCET analysis tool processes the program at assembly code level with the correctly transformed program-path information to obtain accurate runtime bounds. Several experiments were performed to demonstrate the importance of supporting the transformation of path-information in aggressively optimizing compilers.
{"title":"Transformation of path information for WCET analysis during compilation","authors":"R. Kirner, P. Puschner","doi":"10.1109/EMRTS.2001.933993","DOIUrl":"https://doi.org/10.1109/EMRTS.2001.933993","url":null,"abstract":"Performing worst-case execution time (WCET) analysis on machine code with program path annotation provided at high-level source code level requires the transformation of path annotations from the source-code level to assembly/object-code level. This path-information transformation can be done outside or integrated into the compiler during code compilation. The first approach is easier to implement but lacks for the support of strong code optimizations performed by the compiler because the external tool would have to make guesses about optimizations. In this paper we present an approach for the program code compilation that integrates the transformation of program path information into the compiler. Path information is transformed through all compiler stages to the adequate path information for the corresponding assembly code level. The WCET analysis tool processes the program at assembly code level with the correctly transformed program-path information to obtain accurate runtime bounds. Several experiments were performed to demonstrate the importance of supporting the transformation of path-information in aggressively optimizing compilers.","PeriodicalId":292136,"journal":{"name":"Proceedings 13th Euromicro Conference on Real-Time Systems","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131567775","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-06-13DOI: 10.1109/EMRTS.2001.934007
C. Drosos, M. Zayadine, D. Metafas
The rising complexity of communication protocols forces designers to work with efficient high level software design tools to increase the level of abstraction at which they work. For the purposes of the software development of a DECT/GSM protocol implementation for an embedded system a novel SDL based framework was followed. The embedded real time system on chip is based on a multiprocessor architecture, featuring an ARM and a DSP core. Complete system's architecture is presented along with the architecture of the software parts. Final protocol stack code was automatically generated from the SDL tool. A new advanced RTOS-SDL integration method was utilised to integrate the generated code with the functions and services of the RTOS. The results of this integration method were quite promising and the produced system met the initial specifications within the development time limits.
{"title":"Real-time communication protocol development using SDL for an embedded system on chip based on ARM microcontroller","authors":"C. Drosos, M. Zayadine, D. Metafas","doi":"10.1109/EMRTS.2001.934007","DOIUrl":"https://doi.org/10.1109/EMRTS.2001.934007","url":null,"abstract":"The rising complexity of communication protocols forces designers to work with efficient high level software design tools to increase the level of abstraction at which they work. For the purposes of the software development of a DECT/GSM protocol implementation for an embedded system a novel SDL based framework was followed. The embedded real time system on chip is based on a multiprocessor architecture, featuring an ARM and a DSP core. Complete system's architecture is presented along with the architecture of the software parts. Final protocol stack code was automatically generated from the SDL tool. A new advanced RTOS-SDL integration method was utilised to integrate the generated code with the functions and services of the RTOS. The results of this integration method were quite promising and the produced system met the initial specifications within the development time limits.","PeriodicalId":292136,"journal":{"name":"Proceedings 13th Euromicro Conference on Real-Time Systems","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127950393","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-06-13DOI: 10.1109/EMRTS.2001.933998
P. Puschner, G. Bernat
Traditional worst-case execution-time analysis (WCET analysis) computes upper bounds for the execution times of code. This analysis uses knowledge about the execution contest of the code and about the target architecture. In contrast, the WCET analysis for reusable and portable code has to abstract from parameters that are unknown until the code is finally used. The analysis is done in two steps. The first step computes abstract WCET information to support the reuse and portability of the WCET information. The second step uses the abstract WCET information to compute concrete WCET bounds when the application context and the timing parameters of the target system are known. The paper describes each of the two analysis steps. It demonstrates how WCET information can be made portable and reusable.
{"title":"WCET analysis of reusable portable code","authors":"P. Puschner, G. Bernat","doi":"10.1109/EMRTS.2001.933998","DOIUrl":"https://doi.org/10.1109/EMRTS.2001.933998","url":null,"abstract":"Traditional worst-case execution-time analysis (WCET analysis) computes upper bounds for the execution times of code. This analysis uses knowledge about the execution contest of the code and about the target architecture. In contrast, the WCET analysis for reusable and portable code has to abstract from parameters that are unknown until the code is finally used. The analysis is done in two steps. The first step computes abstract WCET information to support the reuse and portability of the WCET information. The second step uses the abstract WCET information to compute concrete WCET bounds when the application context and the timing parameters of the target system are known. The paper describes each of the two analysis steps. It demonstrates how WCET information can be made portable and reusable.","PeriodicalId":292136,"journal":{"name":"Proceedings 13th Euromicro Conference on Real-Time Systems","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122748189","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-06-13DOI: 10.1109/EMRTS.2001.934003
J. López, J. L. Díaz, D. F. García
This paper deals with the problem of finding utilization bounds for multiprocessor rate monotonic scheduling with partitioning. The minimum and maximum utilization bounds among all the reasonable allocation algorithms are calculated. We prove that the utilization bound associated with the reasonable allocation heuristic Worst Fit (WF) is equal to that minimum. In addition, we prove that the utilization bound associated with the heuristics First Fit Decreasing (FFD) and Best Fit Decreasing (BFD) is equal to the maximum, of value (n+1)(2/sup 1/2/-1), where n is the number of processors.
{"title":"Minimum and maximum utilization bounds for multiprocessor RM scheduling","authors":"J. López, J. L. Díaz, D. F. García","doi":"10.1109/EMRTS.2001.934003","DOIUrl":"https://doi.org/10.1109/EMRTS.2001.934003","url":null,"abstract":"This paper deals with the problem of finding utilization bounds for multiprocessor rate monotonic scheduling with partitioning. The minimum and maximum utilization bounds among all the reasonable allocation algorithms are calculated. We prove that the utilization bound associated with the reasonable allocation heuristic Worst Fit (WF) is equal to that minimum. In addition, we prove that the utilization bound associated with the heuristics First Fit Decreasing (FFD) and Best Fit Decreasing (BFD) is equal to the maximum, of value (n+1)(2/sup 1/2/-1), where n is the number of processors.","PeriodicalId":292136,"journal":{"name":"Proceedings 13th Euromicro Conference on Real-Time Systems","volume":"21 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125888922","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-06-13DOI: 10.1109/EMRTS.2001.934025
G. Logothetis, K. Schneider
We present a new temporal logic for the specification and verification of real-time systems. This logic is defined on discrete time transition systems which are interpreted in an abstract manner instead of the usual stuttering interpretation. Our approach directly allows the abstraction of real-time systems by ignoring irrelevant qualitative properties, but without loosing any quantitative information.
{"title":"A new approach to the specification and verification of real-time systems","authors":"G. Logothetis, K. Schneider","doi":"10.1109/EMRTS.2001.934025","DOIUrl":"https://doi.org/10.1109/EMRTS.2001.934025","url":null,"abstract":"We present a new temporal logic for the specification and verification of real-time systems. This logic is defined on discrete time transition systems which are interpreted in an abstract manner instead of the usual stuttering interpretation. Our approach directly allows the abstraction of real-time systems by ignoring irrelevant qualitative properties, but without loosing any quantitative information.","PeriodicalId":292136,"journal":{"name":"Proceedings 13th Euromicro Conference on Real-Time Systems","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128078464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-06-13DOI: 10.1109/EMRTS.2001.933991
Sorin Manolache, P. Eles, Zebo Peng
This paper presents an efficient way to analyse the performance of task sets, where the task execution time is specified as a generalized continuous probability distribution. We consider fixed task sets of periodic, possibly dependent, non-pre-emptable tasks with deadlines less than or equal to the period. Our method is not restricted to any specific scheduling policy and supports policies with both dynamic and static priorities. An algorithm to construct the underlying stochastic process in a memory and time efficient way is presented. We discuss the impact of various parameters on complexity, in terms of analysis time and required memory. Experimental results show the efficiency of the proposed approach.
{"title":"Memory and time-efficient schedulability analysis of task sets with stochastic execution time","authors":"Sorin Manolache, P. Eles, Zebo Peng","doi":"10.1109/EMRTS.2001.933991","DOIUrl":"https://doi.org/10.1109/EMRTS.2001.933991","url":null,"abstract":"This paper presents an efficient way to analyse the performance of task sets, where the task execution time is specified as a generalized continuous probability distribution. We consider fixed task sets of periodic, possibly dependent, non-pre-emptable tasks with deadlines less than or equal to the period. Our method is not restricted to any specific scheduling policy and supports policies with both dynamic and static priorities. An algorithm to construct the underlying stochastic process in a memory and time efficient way is presented. We discuss the impact of various parameters on complexity, in terms of analysis time and required memory. Experimental results show the efficiency of the proposed approach.","PeriodicalId":292136,"journal":{"name":"Proceedings 13th Euromicro Conference on Real-Time Systems","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132006450","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-06-13DOI: 10.1109/EMRTS.2001.934028
M. Bennett, N. Audsley
Conventionally, the use of virtual memory in safety-critical real-time systems has been avoided, one reason being the difficulties it provides to timing analysis. The difficulties arise due to the Memory Management Unit (MMU) on commercial processors being optimised to improve average performance, to the detriment of simple worst-case analysis. However within safety-critical systems, there is a move towards implementations where processes of differing integrity levels are allocated to the same processor. This requires adequate partitioning between processes of different integrity levels. One method for achieving this in the context of commercial processor is via use of the MMU and its support for virtual memory. The focus of this paper is upon the provision of virtual memory for processes of all integrity levels without complicating the timing analysis of safety-critical processes with hard deadlines. Also, for lower integrity processes without hard deadlines, the flexibility of the virtual memory provided does not restrict the process functionality, The virtual memory system proposed is generic and can be implemented on many commercial architectures e.g. PowerPC, ARM and MIPS. This paper details the PowerPC implementation.
{"title":"Predictable and efficient virtual addressing for safety-critical real-time systems","authors":"M. Bennett, N. Audsley","doi":"10.1109/EMRTS.2001.934028","DOIUrl":"https://doi.org/10.1109/EMRTS.2001.934028","url":null,"abstract":"Conventionally, the use of virtual memory in safety-critical real-time systems has been avoided, one reason being the difficulties it provides to timing analysis. The difficulties arise due to the Memory Management Unit (MMU) on commercial processors being optimised to improve average performance, to the detriment of simple worst-case analysis. However within safety-critical systems, there is a move towards implementations where processes of differing integrity levels are allocated to the same processor. This requires adequate partitioning between processes of different integrity levels. One method for achieving this in the context of commercial processor is via use of the MMU and its support for virtual memory. The focus of this paper is upon the provision of virtual memory for processes of all integrity levels without complicating the timing analysis of safety-critical processes with hard deadlines. Also, for lower integrity processes without hard deadlines, the flexibility of the virtual memory provided does not restrict the process functionality, The virtual memory system proposed is generic and can be implemented on many commercial architectures e.g. PowerPC, ARM and MIPS. This paper details the PowerPC implementation.","PeriodicalId":292136,"journal":{"name":"Proceedings 13th Euromicro Conference on Real-Time Systems","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115176027","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-06-13DOI: 10.1109/EMRTS.2001.933989
J. Real, A. Crespo
In multi-moded real-time systems there may exist a different set of tasks per mode. During its mission, the system may switch to a new operating mode, which will involve completing running old-mode tasks and starting new-mode tasks. This represents a transient, bounded overload, which may not be schedulable unless some new-mode tasks are delayed until the old-mode load has decreased. Although this idea has already been proposed elsewhere, a method for obtaining the shortest offsets that make a transition schedulable has not yet been devised. The management of shared resources during the transition represents an added problem to tackle. This paper presents a new mode change protocol and an algorithm to calculate the necessary offsets to schedule mode changes according to a set of requirements and in the presence of shared resources.
{"title":"Offsets for scheduling mode changes","authors":"J. Real, A. Crespo","doi":"10.1109/EMRTS.2001.933989","DOIUrl":"https://doi.org/10.1109/EMRTS.2001.933989","url":null,"abstract":"In multi-moded real-time systems there may exist a different set of tasks per mode. During its mission, the system may switch to a new operating mode, which will involve completing running old-mode tasks and starting new-mode tasks. This represents a transient, bounded overload, which may not be schedulable unless some new-mode tasks are delayed until the old-mode load has decreased. Although this idea has already been proposed elsewhere, a method for obtaining the shortest offsets that make a transition schedulable has not yet been devised. The management of shared resources during the transition represents an added problem to tackle. This paper presents a new mode change protocol and an algorithm to calculate the necessary offsets to schedule mode changes according to a set of requirements and in the presence of shared resources.","PeriodicalId":292136,"journal":{"name":"Proceedings 13th Euromicro Conference on Real-Time Systems","volume":"1233 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124955759","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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