Pub Date : 2016-12-01DOI: 10.1109/ICEMELEC.2016.8074564
J. Aditya, Shaik Sadulla, R. Vaddi
Achieving wide frequency tuning range without sacrificing phase noise and power consumption with CMOS voltage controlled ring oscillators (VCRO) at scaled supply voltages is a big challenge. In this paper, we explore a double gate hetero-junction TFET (HTFET) based VCRO for the first time exploiting the steep subthreshold characteristics of TFETs at scaled supply voltages down to 150mV. It has been demonstrated that TFET based VCRO design achieves wide frequency tuning range for very low power consumption with satisfactory phase noise characteristics, making them suitable for wide frequency range on-chip clock generators/PLLs used in ultra-low power wireless sensor nodes for IoT.
{"title":"Exploiting the steep subthreshold slope characteristics of tunnel transistors for wide tuning range voltage controlled ring oscillator (VCRO) design at scaled supply voltages down to 150mV","authors":"J. Aditya, Shaik Sadulla, R. Vaddi","doi":"10.1109/ICEMELEC.2016.8074564","DOIUrl":"https://doi.org/10.1109/ICEMELEC.2016.8074564","url":null,"abstract":"Achieving wide frequency tuning range without sacrificing phase noise and power consumption with CMOS voltage controlled ring oscillators (VCRO) at scaled supply voltages is a big challenge. In this paper, we explore a double gate hetero-junction TFET (HTFET) based VCRO for the first time exploiting the steep subthreshold characteristics of TFETs at scaled supply voltages down to 150mV. It has been demonstrated that TFET based VCRO design achieves wide frequency tuning range for very low power consumption with satisfactory phase noise characteristics, making them suitable for wide frequency range on-chip clock generators/PLLs used in ultra-low power wireless sensor nodes for IoT.","PeriodicalId":301889,"journal":{"name":"2016 3rd International Conference on Emerging Electronics (ICEE)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121806194","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/ICEMELEC.2016.8074627
Sugandha B. Sharma, A. Kapoor
This study traces the effect of cadmium doping on structural and optical properties of ZnO in order to tailor energy band gap of cadmium doped ZnO thin films for solar cell applications. Sol-gel spin coating method has been deployed to deposit nanocrystalline films of cadmium doped ZnO on glass substrates at room temperature. These films were thermally annealed at 773 K in order to enhance crystallinity. High resolution X-ray diffraction studies facilitate phase analysis, while optical absorbance and transmittance studies suggest a decrease in energy band gap with increasing cadmium content. Maximum dopant concentration of 30% Cd in as-deposited films induced lowering of band gap from 3.29 eV to 2.85 eV.
{"title":"Structural and optical studies of cadmium doped zinc oxide thin films for solar cells","authors":"Sugandha B. Sharma, A. Kapoor","doi":"10.1109/ICEMELEC.2016.8074627","DOIUrl":"https://doi.org/10.1109/ICEMELEC.2016.8074627","url":null,"abstract":"This study traces the effect of cadmium doping on structural and optical properties of ZnO in order to tailor energy band gap of cadmium doped ZnO thin films for solar cell applications. Sol-gel spin coating method has been deployed to deposit nanocrystalline films of cadmium doped ZnO on glass substrates at room temperature. These films were thermally annealed at 773 K in order to enhance crystallinity. High resolution X-ray diffraction studies facilitate phase analysis, while optical absorbance and transmittance studies suggest a decrease in energy band gap with increasing cadmium content. Maximum dopant concentration of 30% Cd in as-deposited films induced lowering of band gap from 3.29 eV to 2.85 eV.","PeriodicalId":301889,"journal":{"name":"2016 3rd International Conference on Emerging Electronics (ICEE)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126188420","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/ICEMELEC.2016.8074565
S. Panda, Rakhi Sharma, K. P. Pradhan, P. K. Sahu
In this paper we have presented a Junctionless GAA nanowire in the 20nm technology node. Junctionless are an alternative to inversion mode transistors. Nowadays device dimensions are miniaturized to achieve better functionalities and high packing density. However, the fabrication challenges are escalating in each advancement of technology nodes due to the precision ion implantation and optimized lithography process steps in such Nano-scale ranges. This work demonstrates both n-type and p-type Junctionless nanowire transistors, which predict impressive performances with high immunity towards short channel effects (SCEs). Further, the devices are integrated to investigate the CMOS circuit application and the results show a desired functionality with respect to ideal Sub-threshold slope(SS), low leakage current (Ioff), high on-off current ratio (Ion/Ioff), and a noise margin about 40% of the supply voltage.
{"title":"Junctionless GAA nanowire transistor: Towards circuit application","authors":"S. Panda, Rakhi Sharma, K. P. Pradhan, P. K. Sahu","doi":"10.1109/ICEMELEC.2016.8074565","DOIUrl":"https://doi.org/10.1109/ICEMELEC.2016.8074565","url":null,"abstract":"In this paper we have presented a Junctionless GAA nanowire in the 20nm technology node. Junctionless are an alternative to inversion mode transistors. Nowadays device dimensions are miniaturized to achieve better functionalities and high packing density. However, the fabrication challenges are escalating in each advancement of technology nodes due to the precision ion implantation and optimized lithography process steps in such Nano-scale ranges. This work demonstrates both n-type and p-type Junctionless nanowire transistors, which predict impressive performances with high immunity towards short channel effects (SCEs). Further, the devices are integrated to investigate the CMOS circuit application and the results show a desired functionality with respect to ideal Sub-threshold slope(SS), low leakage current (Ioff), high on-off current ratio (Ion/Ioff), and a noise margin about 40% of the supply voltage.","PeriodicalId":301889,"journal":{"name":"2016 3rd International Conference on Emerging Electronics (ICEE)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126608859","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/ICEMELEC.2016.8074582
Manish Gupta, A. Kranti
In this work, we investigate the impact of sidewall spacer thickness on the subthreshold swing (5-swing) in symmetrical double gate (DG) Silicon (Si) and Germanium (Ge) junctionless (JL) transistor. It has shown that impact ionization (II) can be enhanced by an optimized narrow spacer whereas the use of non-optimized wider spacer lowers the degree of II by the influence of fringing field. The work demonstrates new opportunities to trigger II at lower drain bias by using Ge as channel material in JL devices with an optimized sidewall spacer.
{"title":"Influence of sidewall spacer thickness on steep switching in Ge junctionless MOSFETs","authors":"Manish Gupta, A. Kranti","doi":"10.1109/ICEMELEC.2016.8074582","DOIUrl":"https://doi.org/10.1109/ICEMELEC.2016.8074582","url":null,"abstract":"In this work, we investigate the impact of sidewall spacer thickness on the subthreshold swing (5-swing) in symmetrical double gate (DG) Silicon (Si) and Germanium (Ge) junctionless (JL) transistor. It has shown that impact ionization (II) can be enhanced by an optimized narrow spacer whereas the use of non-optimized wider spacer lowers the degree of II by the influence of fringing field. The work demonstrates new opportunities to trigger II at lower drain bias by using Ge as channel material in JL devices with an optimized sidewall spacer.","PeriodicalId":301889,"journal":{"name":"2016 3rd International Conference on Emerging Electronics (ICEE)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114418016","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/ICEMELEC.2016.8074588
Hema Mehta, H. Kaur
In this work high temperature performance of Elliptical Gate Ferroelectric Junctionless Transistor has been theoretically investigated and a temperature dependent analytical model has been developed to examine the effect of elliptical cross section along with negative capacitance (NC) phenomenon on junctionless devices. The electrical characteristics of Elliptical Gate Ferroelectric Junctionless Transistor have been studied for temperature range 300K to 360K and Strontium Bismuth Tantalate (SBT), a ferroelectric material has been considered as the gate insulator. The impact of temperature variation along with change in aspect ratio has been examined on various electrical parameters such as surface potential, gain, gate capacitance and subthreshold slope. It has been observed that voltage upconversion achieved due to NC phenomenon exhibited by ferroelectric material is less for device with aspect ratio<1 which further decreases with gradual increase in temperature. Also, at high temperature (360K) values of gain and minimum point subthreshold slope observed are 3 and 23mV/dec respectively for aspect ratio > 1, thereby, signifying its suitability for high temperature energy efficient applications.
{"title":"High temperature performance investigation of elliptical gate ferroelectric junctionless transistor","authors":"Hema Mehta, H. Kaur","doi":"10.1109/ICEMELEC.2016.8074588","DOIUrl":"https://doi.org/10.1109/ICEMELEC.2016.8074588","url":null,"abstract":"In this work high temperature performance of Elliptical Gate Ferroelectric Junctionless Transistor has been theoretically investigated and a temperature dependent analytical model has been developed to examine the effect of elliptical cross section along with negative capacitance (NC) phenomenon on junctionless devices. The electrical characteristics of Elliptical Gate Ferroelectric Junctionless Transistor have been studied for temperature range 300K to 360K and Strontium Bismuth Tantalate (SBT), a ferroelectric material has been considered as the gate insulator. The impact of temperature variation along with change in aspect ratio has been examined on various electrical parameters such as surface potential, gain, gate capacitance and subthreshold slope. It has been observed that voltage upconversion achieved due to NC phenomenon exhibited by ferroelectric material is less for device with aspect ratio<1 which further decreases with gradual increase in temperature. Also, at high temperature (360K) values of gain and minimum point subthreshold slope observed are 3 and 23mV/dec respectively for aspect ratio > 1, thereby, signifying its suitability for high temperature energy efficient applications.","PeriodicalId":301889,"journal":{"name":"2016 3rd International Conference on Emerging Electronics (ICEE)","volume":"137 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128666010","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/ICEMELEC.2016.8074625
A. Sharma, Hardik Kalasua, S. Kumbhar, K. L. Narasimhan, B. Arora
Photoluminescence imaging under different bias conditions is used to obtain maps of the local series resistance and the local ideality factor in large area industrial silicon solar cells. The variation in series resistance correlates with the variations in emitter sheet resistance.
{"title":"Imaging of series resistance and ideality factor in c-Si solar cells","authors":"A. Sharma, Hardik Kalasua, S. Kumbhar, K. L. Narasimhan, B. Arora","doi":"10.1109/ICEMELEC.2016.8074625","DOIUrl":"https://doi.org/10.1109/ICEMELEC.2016.8074625","url":null,"abstract":"Photoluminescence imaging under different bias conditions is used to obtain maps of the local series resistance and the local ideality factor in large area industrial silicon solar cells. The variation in series resistance correlates with the variations in emitter sheet resistance.","PeriodicalId":301889,"journal":{"name":"2016 3rd International Conference on Emerging Electronics (ICEE)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115440790","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/ICEMELEC.2016.8074610
M. Vinchurkar, M. Ashwin, A. Joshi, Archana Singh, P. Tayalia, V. Rao
Combining a single step biofunctionalization method with a low cost polymeric MEMS platform, an efficient label free aptasensor is developed for direct detection of cancer cells. Utilizing the high binding affinity and specificity of the aptamer AS1411 for the cancer cell marker protein Nucleolin, we could detect as low as 800 cancer cells. Till date there is no report on a label free cancer cell biosensor with an integrated piezoresistive transduction.
{"title":"MEMS aptasensor for label-free detection of cancer cells","authors":"M. Vinchurkar, M. Ashwin, A. Joshi, Archana Singh, P. Tayalia, V. Rao","doi":"10.1109/ICEMELEC.2016.8074610","DOIUrl":"https://doi.org/10.1109/ICEMELEC.2016.8074610","url":null,"abstract":"Combining a single step biofunctionalization method with a low cost polymeric MEMS platform, an efficient label free aptasensor is developed for direct detection of cancer cells. Utilizing the high binding affinity and specificity of the aptamer AS1411 for the cancer cell marker protein Nucleolin, we could detect as low as 800 cancer cells. Till date there is no report on a label free cancer cell biosensor with an integrated piezoresistive transduction.","PeriodicalId":301889,"journal":{"name":"2016 3rd International Conference on Emerging Electronics (ICEE)","volume":"136 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124545240","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/ICEMELEC.2016.8074419
Sneha N. Ved, Arjun Gour, Aparna Arya, Joycee Mekie
Router architectures advocating the use of static as well as dynamic virtual channel allocation have been proposed in the literature. However, the comparisons between the two have primarily focused on simulation set-up, largely using synthetic benchmarks. In this work, we present an apple-to-apple comparison of the dynamic and static VC allocation based routers for network performance. We compare the static VC allocation and dynamic VC allocation based routers for real and synthetic benchmarks as well as their implementations. The performance of the two routers has been compared for different routing algorithms, topologies, packet sizes and input port configurations. We observe that for all synthetic traffic patterns, except uniform traffic, static VC allocation based router outperforms the dynamic VC allocation based router. We also observe that in almost all PARSEC benchmark applications, except Blackscholes and Bodytrack with DOR routing, the simplified EVA router outperforms the dynamic VC allocating router. In our ASIC implementation, we observe a clock frequency improvement of 20.2% and power reduction of 19.6% for the static VC allocation based router over the dynamic VC allocation based router.
{"title":"A holistic comparison of static VC allocation versus dynamic VC allocation based NoC routers","authors":"Sneha N. Ved, Arjun Gour, Aparna Arya, Joycee Mekie","doi":"10.1109/ICEMELEC.2016.8074419","DOIUrl":"https://doi.org/10.1109/ICEMELEC.2016.8074419","url":null,"abstract":"Router architectures advocating the use of static as well as dynamic virtual channel allocation have been proposed in the literature. However, the comparisons between the two have primarily focused on simulation set-up, largely using synthetic benchmarks. In this work, we present an apple-to-apple comparison of the dynamic and static VC allocation based routers for network performance. We compare the static VC allocation and dynamic VC allocation based routers for real and synthetic benchmarks as well as their implementations. The performance of the two routers has been compared for different routing algorithms, topologies, packet sizes and input port configurations. We observe that for all synthetic traffic patterns, except uniform traffic, static VC allocation based router outperforms the dynamic VC allocation based router. We also observe that in almost all PARSEC benchmark applications, except Blackscholes and Bodytrack with DOR routing, the simplified EVA router outperforms the dynamic VC allocating router. In our ASIC implementation, we observe a clock frequency improvement of 20.2% and power reduction of 19.6% for the static VC allocation based router over the dynamic VC allocation based router.","PeriodicalId":301889,"journal":{"name":"2016 3rd International Conference on Emerging Electronics (ICEE)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114497653","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/ICEMELEC.2016.8074591
Shubhi Bansal, P. Sen
This work deals with the study of a liquid interface segment as a micromechanical resonator. For free droplet oscillations, reducing the size of the oscillating droplet increases its natural frequency of oscillation. Reducing the size of the droplet for practical applications is, however, limited by issues like evaporation and deposition accuracy. Thus, we investigated local actuation by oscillating a small segment of a liquid interface using AC electrowetting with patterned inplane electrodes. Scaling the “interface length” of an oscillating liquid interface should maximize the resonant frequency. However, we observed overdamped interface oscillations for frequencies 10Hz-1 KHz due to losses and damping mechanisms at small scale dimensions. We also observed contact line patterns pertaining to higher modes upon actuation with higher voltage. This study helps to understand the dynamics of oscillating liquid interface which governs speed and efficiency of liquid switches, liquid lens, lab-on-chip devices and several other applications.
{"title":"Frequency response of a liquid interface segment actuated using AC EWOD","authors":"Shubhi Bansal, P. Sen","doi":"10.1109/ICEMELEC.2016.8074591","DOIUrl":"https://doi.org/10.1109/ICEMELEC.2016.8074591","url":null,"abstract":"This work deals with the study of a liquid interface segment as a micromechanical resonator. For free droplet oscillations, reducing the size of the oscillating droplet increases its natural frequency of oscillation. Reducing the size of the droplet for practical applications is, however, limited by issues like evaporation and deposition accuracy. Thus, we investigated local actuation by oscillating a small segment of a liquid interface using AC electrowetting with patterned inplane electrodes. Scaling the “interface length” of an oscillating liquid interface should maximize the resonant frequency. However, we observed overdamped interface oscillations for frequencies 10Hz-1 KHz due to losses and damping mechanisms at small scale dimensions. We also observed contact line patterns pertaining to higher modes upon actuation with higher voltage. This study helps to understand the dynamics of oscillating liquid interface which governs speed and efficiency of liquid switches, liquid lens, lab-on-chip devices and several other applications.","PeriodicalId":301889,"journal":{"name":"2016 3rd International Conference on Emerging Electronics (ICEE)","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114941666","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/ICEMELEC.2016.8074607
K. Khanum, Pritom J. Bora, K. Vinoy, Praveen C Ramamurthy
In this work, excellent electromagnetic interference (EMI) shielding using a ternary blend of Poly(3,4-ethylenedioxythiophene) Polystyrene sulfonate (PEDOT: PSS) is demonstrated. Electromagnetic interference shielding of up to 26 dB in the X-band (8.2–12.4 GHz) and 28 dB in Ku-band (12.4–18GHz) is achieved. The ternary blend being PEDOT: PSS-PEO-PVA in the ratio of 85:7.5:7.5 wherein PEDOT: PSS is a conducting polymer widely known for its high conductivity with atmospheric stability. The drop casted ternary blend film measured thickness of 42±2 μm. The EMI shielding measurements are further repeated in the interval of 30 days, and the values are observed to be unaltered. Thus, this PEDOT: PSS blend study elucidates the EMI shielding properties along with effective shielding stability.
{"title":"Evaluation of electromagnetic interference shielding using Poly(3,4-ethylenedioxythiophene) Polystyrene sulfonate blend","authors":"K. Khanum, Pritom J. Bora, K. Vinoy, Praveen C Ramamurthy","doi":"10.1109/ICEMELEC.2016.8074607","DOIUrl":"https://doi.org/10.1109/ICEMELEC.2016.8074607","url":null,"abstract":"In this work, excellent electromagnetic interference (EMI) shielding using a ternary blend of Poly(3,4-ethylenedioxythiophene) Polystyrene sulfonate (PEDOT: PSS) is demonstrated. Electromagnetic interference shielding of up to 26 dB in the X-band (8.2–12.4 GHz) and 28 dB in Ku-band (12.4–18GHz) is achieved. The ternary blend being PEDOT: PSS-PEO-PVA in the ratio of 85:7.5:7.5 wherein PEDOT: PSS is a conducting polymer widely known for its high conductivity with atmospheric stability. The drop casted ternary blend film measured thickness of 42±2 μm. The EMI shielding measurements are further repeated in the interval of 30 days, and the values are observed to be unaltered. Thus, this PEDOT: PSS blend study elucidates the EMI shielding properties along with effective shielding stability.","PeriodicalId":301889,"journal":{"name":"2016 3rd International Conference on Emerging Electronics (ICEE)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127974780","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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