Pub Date : 2017-06-25DOI: 10.1109/PVSC.2017.8366231
R. Vasudevan, Isabella Poli, D. Deligiannis, M. Zeman, A. Smets
Light-induced effects on the minority carrier lifetime of silicon heterojunction structures are studied through multiple exposure photoconductance decay (MEPCD). MEPCD monitors the effect of the measurement flash from a PCD setup on a sample over thousands of measurements. Varying the microstructure of the intrinsic hydrogenated amorphous silicon (a-Si:H) used for passivation of n-type crystalline silicon (cSi) showed that passivating films rich in voids produce light induced improvement, while denser films result in samples that are susceptible to light induced degradation. Light-induced degradation linked to an increase in dangling bond density at the a-Si:H/c-Si interface while light-induced improvements are linked to charging at the a-Si:H/c-Si interface. Furthermore doped a-Si:H is added to make samples with an emitter and back surface field (BSF). These doped layers have a significant effect on the light-induced kinetics on minority carrier lifetime. Emitter samples exhibit consistent light-induced improvement while BSF samples exhibit light-induced degradation. This is explained through negative charging at the BSF and positive charging at the emitter. Full precursors with a BSF and emitter exhibit different kinetics based on which side is being illuminated. This suggests that the light-induced charging at the a-Si:H/c-Si interface can only occur when a-Si:H has sufficient generation.
{"title":"Light-induced effects on the a-Si:H/c-Si heterointerface","authors":"R. Vasudevan, Isabella Poli, D. Deligiannis, M. Zeman, A. Smets","doi":"10.1109/PVSC.2017.8366231","DOIUrl":"https://doi.org/10.1109/PVSC.2017.8366231","url":null,"abstract":"Light-induced effects on the minority carrier lifetime of silicon heterojunction structures are studied through multiple exposure photoconductance decay (MEPCD). MEPCD monitors the effect of the measurement flash from a PCD setup on a sample over thousands of measurements. Varying the microstructure of the intrinsic hydrogenated amorphous silicon (a-Si:H) used for passivation of n-type crystalline silicon (cSi) showed that passivating films rich in voids produce light induced improvement, while denser films result in samples that are susceptible to light induced degradation. Light-induced degradation linked to an increase in dangling bond density at the a-Si:H/c-Si interface while light-induced improvements are linked to charging at the a-Si:H/c-Si interface. Furthermore doped a-Si:H is added to make samples with an emitter and back surface field (BSF). These doped layers have a significant effect on the light-induced kinetics on minority carrier lifetime. Emitter samples exhibit consistent light-induced improvement while BSF samples exhibit light-induced degradation. This is explained through negative charging at the BSF and positive charging at the emitter. Full precursors with a BSF and emitter exhibit different kinetics based on which side is being illuminated. This suggests that the light-induced charging at the a-Si:H/c-Si interface can only occur when a-Si:H has sufficient generation.","PeriodicalId":314399,"journal":{"name":"2017 IEEE 44th Photovoltaic Specialist Conference (PVSC)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127278597","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-06-25DOI: 10.1109/PVSC.2017.8521518
Nicholas A. Engerer, Jamie M. Bright, S. Killinger
High resolution, next generation satellites such as Himawari-8 show great promise for the provision of accurate estimations of Behind-the-Meter (BtM) solar PV power production. This paper presents a methodology that produces real-time PV power estimates as derived from Himawari-8 satellite imagery, validating them against seven Australian radiation monitoring sites and 78 small-scale BtM solar PV sites in Canberra, Australia. We report an MBE of −7 W m-2 and RMSE of 55 W m-2 for global horizontal radiation values $(G_{h})$ and an MBE of 0.04 W/Wp and RMSE of 0.15 W/Wp for estimated actuals at the PV sites. As a capstone, we apply this satellite based radiation modeling tool to a distribution network level distributed PV simulation in a single case-study using 15,500 PV sites.
高分辨率的下一代卫星，如Himawari-8，在提供准确的BtM (Behind-the-Meter)太阳能光伏发电估算方面显示出巨大的希望。本文提出了一种基于Himawari-8卫星图像的实时光伏发电估算方法，并将其与澳大利亚7个辐射监测点和澳大利亚堪培拉的78个小型BtM太阳能光伏电站进行了验证。我们报告了全球水平辐射值$(G_{h})$的MBE为- 7 W m-2, RMSE为55 W m-2, PV站点估计的实际MBE为0.04 W/Wp, RMSE为0.15 W/Wp。作为一个顶点，我们将这种基于卫星的辐射建模工具应用于配电网级分布式光伏模拟，在一个使用15,500个光伏站点的单一案例研究中。
{"title":"Himawari-8 Enabled Real-Time Distributed Pv Simulations for Distribution Networks","authors":"Nicholas A. Engerer, Jamie M. Bright, S. Killinger","doi":"10.1109/PVSC.2017.8521518","DOIUrl":"https://doi.org/10.1109/PVSC.2017.8521518","url":null,"abstract":"High resolution, next generation satellites such as Himawari-8 show great promise for the provision of accurate estimations of Behind-the-Meter (BtM) solar PV power production. This paper presents a methodology that produces real-time PV power estimates as derived from Himawari-8 satellite imagery, validating them against seven Australian radiation monitoring sites and 78 small-scale BtM solar PV sites in Canberra, Australia. We report an MBE of −7 W m-2 and RMSE of 55 W m-2 for global horizontal radiation values $(G_{h})$ and an MBE of 0.04 W/Wp and RMSE of 0.15 W/Wp for estimated actuals at the PV sites. As a capstone, we apply this satellite based radiation modeling tool to a distribution network level distributed PV simulation in a single case-study using 15,500 PV sites.","PeriodicalId":314399,"journal":{"name":"2017 IEEE 44th Photovoltaic Specialist Conference (PVSC)","volume":"2016 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128078453","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-06-25DOI: 10.1109/PVSC.2017.8521558
A. Onno, M. Tang, Mu Wang, Y. Maidaniuk, M. Benamara, Y. Mazur, G. Salamo, L. Oberbeck, Jiang Wu, Huiyun Liu
Metamorphic epitaxial growth of III-V solar cells on Si has attracted significant interest for the development of III-V/Si photovoltaic architectures. In this work, we present an alternative pathway - using MBE growth techniques -based on the direct nucleation of AlxGa1-xAs materials on Si, followed by the growth of a 1.7eV Al0.2Ga0.8As or a 1.42eV GaAs solar cell. Dislocation Filter Layers (DFLs), in conjunction with Thermal Cycle Annealing (TCA), have been used to reduce the Threading Dislocation Density (TDD) below 107cm−2 in the base of the cell; close to the best results demonstrated with metamorphic buffers.
{"title":"MBE growth of 1.7eV Al0.2Ga0.8As and 1.42eV GaAs solar cells on Si using dislocations filters: an alternative pathway toward III-V/ Si solar cells architectures","authors":"A. Onno, M. Tang, Mu Wang, Y. Maidaniuk, M. Benamara, Y. Mazur, G. Salamo, L. Oberbeck, Jiang Wu, Huiyun Liu","doi":"10.1109/PVSC.2017.8521558","DOIUrl":"https://doi.org/10.1109/PVSC.2017.8521558","url":null,"abstract":"Metamorphic epitaxial growth of III-V solar cells on Si has attracted significant interest for the development of III-V/Si photovoltaic architectures. In this work, we present an alternative pathway - using MBE growth techniques -based on the direct nucleation of Al<inf>x</inf>Ga<inf>1-x</inf>As materials on Si, followed by the growth of a 1.7eV Al<inf>0.2</inf>Ga<inf>0.8</inf>As or a 1.42eV GaAs solar cell. Dislocation Filter Layers (DFLs), in conjunction with Thermal Cycle Annealing (TCA), have been used to reduce the Threading Dislocation Density (TDD) below 10<sup>7</sup>cm<sup>−2</sup> in the base of the cell; close to the best results demonstrated with metamorphic buffers.","PeriodicalId":314399,"journal":{"name":"2017 IEEE 44th Photovoltaic Specialist Conference (PVSC)","volume":"155 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133949122","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-06-25DOI: 10.1109/PVSC.2017.8366872
B. Kafle, Timo Freund, J. Schön, S. Werner, A. Wolf, A. Lorenz, P. Saint‐Cast, L. Clochard, E. Duffy, M. Hofmann, J. Rentsch
In this paper, we study the effect of various emitter diffusion profiles on the electrical characteristics of nanotextured surfaces formed by an inline plasma-less and mask- less dry-chemical etching process. We modify the emitter diffusion profiles in order to reach reasonably low emitter saturation current densities by using either SiNx (joe, min ≈96 fA/cm2) or AlOx/SiNx((j0e,min ≈50 fA/cm2) on these surfaces diffused with phosphorous emitter. In order to understand the nature of screen printed front side silver contacts on nanotextured surfaces, we perform macroscopic measurement of contact resistivity combined with microscopic analysis of the contact areas. We show that the depths of nanostructures do not seem to influence the contact formation process. Instead, we observe that numerous metal-semiconductor direct contact points formed mainly on the peak and the plateaus of the nanostructures are most possibly responsible for the low contact resistances (ρc,min ≈ 1.2 mΩ cm2) achievable in these surfaces.
{"title":"On the nature of emitter diffusion and screen-printing contact formation on nanostructured silicon surfaces","authors":"B. Kafle, Timo Freund, J. Schön, S. Werner, A. Wolf, A. Lorenz, P. Saint‐Cast, L. Clochard, E. Duffy, M. Hofmann, J. Rentsch","doi":"10.1109/PVSC.2017.8366872","DOIUrl":"https://doi.org/10.1109/PVSC.2017.8366872","url":null,"abstract":"In this paper, we study the effect of various emitter diffusion profiles on the electrical characteristics of nanotextured surfaces formed by an inline plasma-less and mask- less dry-chemical etching process. We modify the emitter diffusion profiles in order to reach reasonably low emitter saturation current densities by using either SiN<inf>x</inf> (j<inf>oe, min</inf> ≈96 fA/cm<sup>2</sup>) or AlO<inf>x</inf>/SiN<inf>x</inf>((j<inf>0e</inf>,<inf>min</inf> ≈50 fA/cm<sup>2</sup>) on these surfaces diffused with phosphorous emitter. In order to understand the nature of screen printed front side silver contacts on nanotextured surfaces, we perform macroscopic measurement of contact resistivity combined with microscopic analysis of the contact areas. We show that the depths of nanostructures do not seem to influence the contact formation process. Instead, we observe that numerous metal-semiconductor direct contact points formed mainly on the peak and the plateaus of the nanostructures are most possibly responsible for the low contact resistances (ρ<inf>c,min</inf> ≈ 1.2 mΩ cm<sup>2</sup>) achievable in these surfaces.","PeriodicalId":314399,"journal":{"name":"2017 IEEE 44th Photovoltaic Specialist Conference (PVSC)","volume":"1969 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130013035","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-06-25DOI: 10.1109/PVSC.2017.8521509
Cristina S. Polo Lόpez, P. Bonomo, F. Frontini, V. Medici, L. Nespoli
In this study, a comparative outdoor test of an innovative BIPV solar tile with a well-established market product is conducted. Two mock-up structures have been built to generate further insights into BIPV efficiency as a function of operative temperatures and back-module ventilation. The two small-scale installations include a complete roof construction package on which the BIPV modules are integrated as a full-roof solution. The test-stands are equipped with a monitoring system aimed to assess the operating conditions both in terms of temperatures and PV performances. Along with the thermal and yield monitoring, the effect of temperature and natural ventilation on the PV production is studied through the identification of a thermal model and the simulation for one of the studied configurations.
{"title":"Performance assessment of a BIPV Roofing Tile in outdoor testing","authors":"Cristina S. Polo Lόpez, P. Bonomo, F. Frontini, V. Medici, L. Nespoli","doi":"10.1109/PVSC.2017.8521509","DOIUrl":"https://doi.org/10.1109/PVSC.2017.8521509","url":null,"abstract":"In this study, a comparative outdoor test of an innovative BIPV solar tile with a well-established market product is conducted. Two mock-up structures have been built to generate further insights into BIPV efficiency as a function of operative temperatures and back-module ventilation. The two small-scale installations include a complete roof construction package on which the BIPV modules are integrated as a full-roof solution. The test-stands are equipped with a monitoring system aimed to assess the operating conditions both in terms of temperatures and PV performances. Along with the thermal and yield monitoring, the effect of temperature and natural ventilation on the PV production is studied through the identification of a thermal model and the simulation for one of the studied configurations.","PeriodicalId":314399,"journal":{"name":"2017 IEEE 44th Photovoltaic Specialist Conference (PVSC)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128438851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-06-25DOI: 10.1109/PVSC.2017.8521505
S. Misra, C. E. Hahn, V. Palekis, C. Ferekides, M. Scarpulla
Photon absorption is a critical process for photovoltaic operation, yet the effect of illumination on semiconductor growth and processing is rarely investigated. In this work we investigate the effect of illumination during the cadmium chloride (CdCl2) annealing treatment of cadmium telluride (CdTe) thin films for photovoltaic applications while keeping the sample temperature constant. Illumination at 808 nm with varying intensity (0, 0.5, 1 and 1.5 W) when incident on CdTe during thermal CdCl2treatment of CdTe lead to enhancement of grain size and optoelectronic properties of CdTe. However photo-assisted etching of the CdTe surface is also observed at illuminations sufficiently low that the sample temperature was barely affected during annealing. Additionally, annealing under high illumination sufficient to drive CdCl2annealing in the absence of a furnace has no such effect on the CdTe surface. We attempt to reconcile these observations and provide rationale for further experiments.
{"title":"Effect of Illumination on Thermal CdCl2Treatment of CdTe","authors":"S. Misra, C. E. Hahn, V. Palekis, C. Ferekides, M. Scarpulla","doi":"10.1109/PVSC.2017.8521505","DOIUrl":"https://doi.org/10.1109/PVSC.2017.8521505","url":null,"abstract":"Photon absorption is a critical process for photovoltaic operation, yet the effect of illumination on semiconductor growth and processing is rarely investigated. In this work we investigate the effect of illumination during the cadmium chloride (CdCl2) annealing treatment of cadmium telluride (CdTe) thin films for photovoltaic applications while keeping the sample temperature constant. Illumination at 808 nm with varying intensity (0, 0.5, 1 and 1.5 W) when incident on CdTe during thermal CdCl2treatment of CdTe lead to enhancement of grain size and optoelectronic properties of CdTe. However photo-assisted etching of the CdTe surface is also observed at illuminations sufficiently low that the sample temperature was barely affected during annealing. Additionally, annealing under high illumination sufficient to drive CdCl2annealing in the absence of a furnace has no such effect on the CdTe surface. We attempt to reconcile these observations and provide rationale for further experiments.","PeriodicalId":314399,"journal":{"name":"2017 IEEE 44th Photovoltaic Specialist Conference (PVSC)","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123846632","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-06-01DOI: 10.1109/PVSC.2017.8366438
E. Perl, J. Simon, J. Geisz, M. Lee, D. Friedman, M. Steiner
In this work, we study the performance of 2.0 eV Al0.12Ga0.39In0.49P and 1.4 eV GaAs solar cells over a temperature range of 25–400°C. The temperature-dependent J01 and J02 dark currents are extracted by fitting current-voltage measurements to a two-diode model. We find that the intrinsic carrier concentration, ni, dominates the temperature dependence of the dark currents, open circuit voltage, and cell efficiency. To study the impact of temperature on the photocurrent and bandgap of the solar cells, we measure the quantum efficiency and illuminated current-voltage characteristics of the devices up to 400°C. As the temperature is increased, we observe no degradation to the internal quantum efficiency and a decrease in the bandgap. These two factors drive an increase in the short-circuit current density at high temperatures. Finally, we measure the devices at concentrations ranging from ∼30–1500 suns, and observe n=1 recombination characteristics across the entire temperature range. These findings should be a valuable guide to the design of any system that requires high-temperature solar cell operation.
在这项工作中，我们研究了2.0 eV Al0.12Ga0.39In0.49P和1.4 eV GaAs太阳能电池在25-400°C温度范围内的性能。通过将电流-电压测量值拟合到双二极管模型中，提取出与温度相关的J01和J02暗电流。我们发现，固有载流子浓度ni主导了暗电流、开路电压和电池效率的温度依赖性。为了研究温度对太阳能电池光电流和带隙的影响，我们测量了器件高达400°C的量子效率和照明电流电压特性。随着温度的升高，我们观察到内部量子效率没有下降，带隙减小。这两个因素导致高温下短路电流密度增大。最后，我们在~ 30-1500太阳的浓度范围内测量了这些器件，并观察了整个温度范围内n=1的重组特性。这些发现对于设计任何需要高温太阳能电池操作的系统都是有价值的指导。
{"title":"Measurements and modeling of III-V solar cells at high temperatures up to 400°C","authors":"E. Perl, J. Simon, J. Geisz, M. Lee, D. Friedman, M. Steiner","doi":"10.1109/PVSC.2017.8366438","DOIUrl":"https://doi.org/10.1109/PVSC.2017.8366438","url":null,"abstract":"In this work, we study the performance of 2.0 eV Al0.12Ga0.39In0.49P and 1.4 eV GaAs solar cells over a temperature range of 25–400°C. The temperature-dependent J01 and J02 dark currents are extracted by fitting current-voltage measurements to a two-diode model. We find that the intrinsic carrier concentration, ni, dominates the temperature dependence of the dark currents, open circuit voltage, and cell efficiency. To study the impact of temperature on the photocurrent and bandgap of the solar cells, we measure the quantum efficiency and illuminated current-voltage characteristics of the devices up to 400°C. As the temperature is increased, we observe no degradation to the internal quantum efficiency and a decrease in the bandgap. These two factors drive an increase in the short-circuit current density at high temperatures. Finally, we measure the devices at concentrations ranging from ∼30–1500 suns, and observe n=1 recombination characteristics across the entire temperature range. These findings should be a valuable guide to the design of any system that requires high-temperature solar cell operation.","PeriodicalId":314399,"journal":{"name":"2017 IEEE 44th Photovoltaic Specialist Conference (PVSC)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116963772","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-06-01DOI: 10.1109/PVSC.2017.8366201
A. Morishige, M. Jensen, D. B. Needleman, K. Nakayashiki, J. Hofstetter, T. Li, T. Buonassisi
When untreated, light-induced degradation (LID) of p-type multicrystalline silicon-based PERC modules can reduce power output by up to 10% relative during sun-soaking under open-circuit conditions. Identifying the root cause of this form of LID has been the subject of several recent investigations. Injection-dependent lifetime spectroscopy (IDLS) analysis may offer insight into the root-cause defect(s). In this contribution, to illustrate the root-case defect identification method, we apply IDLS to intentionally Cr-contaminated mc-Si. Then, we apply the method to p-type mc-Si that exhibits LID in PERC devices. We quantify the concentrations of several candidate impurities and the uncertainty in the defect capture cross-section ratio of 28.5 + 5.5 identified with this method.
{"title":"Lifetime spectroscopy investigation of light-induced degradation in p-type multicrystalline silicon PERC","authors":"A. Morishige, M. Jensen, D. B. Needleman, K. Nakayashiki, J. Hofstetter, T. Li, T. Buonassisi","doi":"10.1109/PVSC.2017.8366201","DOIUrl":"https://doi.org/10.1109/PVSC.2017.8366201","url":null,"abstract":"When untreated, light-induced degradation (LID) of p-type multicrystalline silicon-based PERC modules can reduce power output by up to 10% relative during sun-soaking under open-circuit conditions. Identifying the root cause of this form of LID has been the subject of several recent investigations. Injection-dependent lifetime spectroscopy (IDLS) analysis may offer insight into the root-cause defect(s). In this contribution, to illustrate the root-case defect identification method, we apply IDLS to intentionally Cr-contaminated mc-Si. Then, we apply the method to p-type mc-Si that exhibits LID in PERC devices. We quantify the concentrations of several candidate impurities and the uncertainty in the defect capture cross-section ratio of 28.5 + 5.5 identified with this method.","PeriodicalId":314399,"journal":{"name":"2017 IEEE 44th Photovoltaic Specialist Conference (PVSC)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125158984","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-06-01DOI: 10.1109/PVSC.2017.8366186
H. Hiroi, Y. Iwata, H. Sugimoto, A. Yamada
Previously, open circuit voltage of 960mV was reported on Se-free Cu(In,Ga)S2 solar cell with CdS buffer layer. In this paper, we report our latest progress toward 1000mV on Se-free Cu(In,Ga)S2 solar cell with Cd-free buffer layer. Highest open circuit voltage of 973mV was demonstrated by rapid thermal annealing and Zn1−xMgxO buffer layer application.
{"title":"Progress toward 1000mV open-circuit voltage on chalcopyrite solar cell","authors":"H. Hiroi, Y. Iwata, H. Sugimoto, A. Yamada","doi":"10.1109/PVSC.2017.8366186","DOIUrl":"https://doi.org/10.1109/PVSC.2017.8366186","url":null,"abstract":"Previously, open circuit voltage of 960mV was reported on Se-free Cu(In,Ga)S<inf>2</inf> solar cell with CdS buffer layer. In this paper, we report our latest progress toward 1000mV on Se-free Cu(In,Ga)S<inf>2</inf> solar cell with Cd-free buffer layer. Highest open circuit voltage of 973mV was demonstrated by rapid thermal annealing and Zn<inf>1−x</inf>Mg<inf>x</inf>O buffer layer application.","PeriodicalId":314399,"journal":{"name":"2017 IEEE 44th Photovoltaic Specialist Conference (PVSC)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116597866","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-06-01DOI: 10.1109/PVSC.2017.8366267
J. Wong, Samuel Raj, J. Ho, Jianqiang Wang, Jiaji Lin
While it is relatively easy to analyze the optical and recombination losses contributing to a solar cell's short circuit current, there are many nuanced effects that lead to the solar cell's voltage at the maximum power point and at open circuit. This paper analyzes the impact of some commonly considered factors, such as series resistance, as well as some hard- to-discern factors like localized recombination at the wafer periphery and metal busbars, on the solar cell's open-circuit voltage, maximum power point and fill factor. A series of samples related to an n-type bifacial solar cell are chosen as an example.
{"title":"Voltage loss analysis for bifacial silicon solar cells: Case for two-dimensional large-area modelling","authors":"J. Wong, Samuel Raj, J. Ho, Jianqiang Wang, Jiaji Lin","doi":"10.1109/PVSC.2017.8366267","DOIUrl":"https://doi.org/10.1109/PVSC.2017.8366267","url":null,"abstract":"While it is relatively easy to analyze the optical and recombination losses contributing to a solar cell's short circuit current, there are many nuanced effects that lead to the solar cell's voltage at the maximum power point and at open circuit. This paper analyzes the impact of some commonly considered factors, such as series resistance, as well as some hard- to-discern factors like localized recombination at the wafer periphery and metal busbars, on the solar cell's open-circuit voltage, maximum power point and fill factor. A series of samples related to an n-type bifacial solar cell are chosen as an example.","PeriodicalId":314399,"journal":{"name":"2017 IEEE 44th Photovoltaic Specialist Conference (PVSC)","volume":"123 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124597845","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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