This paper analyzes the relationship between BGP convergence and the power-law of the Internet. The inter-domain routing system is classified into three hierarchies based on the power-law and commercial relations of autonomous systems. The relation of network topology and three convergence parameters-convergence time T, affected ASs set Nc and affected paths factor mu is presented for all sorts of convergence events in different layers. The result shows that the power-law nature of network influences the BGP convergence greatly
{"title":"The Hierarchy of BGP Convergence on the Self-Organized Internet","authors":"Jinjing Zhao, Peidong Zhu, Xicheng Lu, Feng Zhao","doi":"10.1109/PRDC.2006.60","DOIUrl":"https://doi.org/10.1109/PRDC.2006.60","url":null,"abstract":"This paper analyzes the relationship between BGP convergence and the power-law of the Internet. The inter-domain routing system is classified into three hierarchies based on the power-law and commercial relations of autonomous systems. The relation of network topology and three convergence parameters-convergence time T, affected ASs set Nc and affected paths factor mu is presented for all sorts of convergence events in different layers. The result shows that the power-law nature of network influences the BGP convergence greatly","PeriodicalId":314915,"journal":{"name":"2006 12th Pacific Rim International Symposium on Dependable Computing (PRDC'06)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131557440","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This study is motivated by the unexpected failure of a network-based system during the performance of corrective maintenance. This incident highlights the importance of incorporating network connectivity analysis in maintenance planning. This study shows that it is crucial to consider network connectivity when planning maintenance. Procedures to conduct maintenance planning with network connectivity consideration is proposed and discussed
{"title":"Incorporating Network Connectivity Analysis in Maintenance Planning","authors":"Meng-Lai Yin, R. Arellano","doi":"10.1109/PRDC.2006.40","DOIUrl":"https://doi.org/10.1109/PRDC.2006.40","url":null,"abstract":"This study is motivated by the unexpected failure of a network-based system during the performance of corrective maintenance. This incident highlights the importance of incorporating network connectivity analysis in maintenance planning. This study shows that it is crucial to consider network connectivity when planning maintenance. Procedures to conduct maintenance planning with network connectivity consideration is proposed and discussed","PeriodicalId":314915,"journal":{"name":"2006 12th Pacific Rim International Symposium on Dependable Computing (PRDC'06)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116703347","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Owing to the rapid advance in semiconductor fabrication technology, a large number of transistors can be incorporated onto a single chip. However, this will reduce the controllability and observability of the chip significantly. Consequently, testing such highly complex and dense circuits becomes very difficult and expensive. Therefore, we propose an efficient design-for-testability technique based on M-testability conditions for the 2D systolic DCT/IDCT processors in this paper. The cell fault model is adopted. For chip testing consideration, we modify the processing elements of the 2D array and make the module function bijective. The proposed DFT technique is also suitable for BIST implementation. The test pattern generator is simply a binary counter. Moreover, the adders and registers in each processing element can be combined as signature analyzers to perform accumulation and compression operations to evaluate the signatures during different test sessions. The signatures for each test session are stored in each processing element and propagated to the primary outputs when the test session is finished. An experimental chip is designed and implemented with Synopsys synthesis tools. Experimental results show that the hardware overhead of the BIST architecture for 2D DCT/IDCT architectures is less than 10%. The fault coverage of each processing element can achieve 98.18%
{"title":"Efficient Built-In Self-Test Schemes for Video Coding Cores: a Case Study on DCT/IDCT Circuits","authors":"Shyue-Kung Lu, Ting-Yu Chen, Wei-Yuan Liu","doi":"10.1109/PRDC.2006.31","DOIUrl":"https://doi.org/10.1109/PRDC.2006.31","url":null,"abstract":"Owing to the rapid advance in semiconductor fabrication technology, a large number of transistors can be incorporated onto a single chip. However, this will reduce the controllability and observability of the chip significantly. Consequently, testing such highly complex and dense circuits becomes very difficult and expensive. Therefore, we propose an efficient design-for-testability technique based on M-testability conditions for the 2D systolic DCT/IDCT processors in this paper. The cell fault model is adopted. For chip testing consideration, we modify the processing elements of the 2D array and make the module function bijective. The proposed DFT technique is also suitable for BIST implementation. The test pattern generator is simply a binary counter. Moreover, the adders and registers in each processing element can be combined as signature analyzers to perform accumulation and compression operations to evaluate the signatures during different test sessions. The signatures for each test session are stored in each processing element and propagated to the primary outputs when the test session is finished. An experimental chip is designed and implemented with Synopsys synthesis tools. Experimental results show that the hardware overhead of the BIST architecture for 2D DCT/IDCT architectures is less than 10%. The fault coverage of each processing element can achieve 98.18%","PeriodicalId":314915,"journal":{"name":"2006 12th Pacific Rim International Symposium on Dependable Computing (PRDC'06)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116809615","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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