In this paper we present an algorithm to synthesize a finite place/transition Petri net (p/t-net) from a finite set of labeled partial orders (a finite partial language). This p/t-net has minimal non-sequential behavior including the specified partial language. Consequently, either this net has exactly the non-sequential behavior specified by the partial language, or there is no such p/t-net. We finally develop an algorithm to test whether the synthesized net has exactly the non-sequential behavior specified by the partial language. The algorithms are based on the theory of regions for partial languages developed by Lorenz and Juhas. Thus, this paper shows the applicability of this concept and, for the first time, provides an effective algorithm for the synthesis of system models from partial languages.
{"title":"Synthesis of Petri Nets from Finite Partial Languages","authors":"R. Bergenthum, J. Desel, R. Lorenz, S. Mauser","doi":"10.1109/ACSD.2007.72","DOIUrl":"https://doi.org/10.1109/ACSD.2007.72","url":null,"abstract":"In this paper we present an algorithm to synthesize a finite place/transition Petri net (p/t-net) from a finite set of labeled partial orders (a finite partial language). This p/t-net has minimal non-sequential behavior including the specified partial language. Consequently, either this net has exactly the non-sequential behavior specified by the partial language, or there is no such p/t-net. We finally develop an algorithm to test whether the synthesized net has exactly the non-sequential behavior specified by the partial language. The algorithms are based on the theory of regions for partial languages developed by Lorenz and Juhas. Thus, this paper shows the applicability of this concept and, for the first time, provides an effective algorithm for the synthesis of system models from partial languages.","PeriodicalId":323657,"journal":{"name":"Seventh International Conference on Application of Concurrency to System Design (ACSD 2007)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123724072","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
I. Budinská, V. Oravec, E. Gatial, M. Laclavik, Martin Seleng, Z. Balogh, B. Frankovic, R. Forgác, I. Mokris, L. Hluchý
The paper describes a knowledge support system for administrative workflow processes. The RAPORT system is based on ontology and e-mail communication. The description of architecture and basic functionalities and components of the RAPORT system are provided in this paper.
{"title":"RAPORT - a knowledge support system for administrative workflow processes","authors":"I. Budinská, V. Oravec, E. Gatial, M. Laclavik, Martin Seleng, Z. Balogh, B. Frankovic, R. Forgác, I. Mokris, L. Hluchý","doi":"10.1109/ACSD.2007.60","DOIUrl":"https://doi.org/10.1109/ACSD.2007.60","url":null,"abstract":"The paper describes a knowledge support system for administrative workflow processes. The RAPORT system is based on ontology and e-mail communication. The description of architecture and basic functionalities and components of the RAPORT system are provided in this paper.","PeriodicalId":323657,"journal":{"name":"Seventh International Conference on Application of Concurrency to System Design (ACSD 2007)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121580747","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Signal Transition Graphs (STG) are a formalism for the description of asynchronous circuit behaviour. In this paper we propose (and justify) a formal semantics of nondeterministic STGs with dummies and OR-causality. For this, we introduce the concept of output-determinacy, which is a relaxation of determinism, and argue that it is reasonable and useful in the speed-independent context. With our theory we improve an STG decomposition algorithm, which can alleviate state explosion.
{"title":"Output-Determinacy and Asynchronous Circuit Synthesis","authors":"Victor Khomenko, Mark Schäfer, W. Vogler","doi":"10.1109/ACSD.2007.57","DOIUrl":"https://doi.org/10.1109/ACSD.2007.57","url":null,"abstract":"Signal Transition Graphs (STG) are a formalism for the description of asynchronous circuit behaviour. In this paper we propose (and justify) a formal semantics of nondeterministic STGs with dummies and OR-causality. For this, we introduce the concept of output-determinacy, which is a relaxation of determinism, and argue that it is reasonable and useful in the speed-independent context. With our theory we improve an STG decomposition algorithm, which can alleviate state explosion.","PeriodicalId":323657,"journal":{"name":"Seventh International Conference on Application of Concurrency to System Design (ACSD 2007)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115704716","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Software architecture has been introduced with promise of better re-use of software, greater flexibility, scalability and higher quality of software services. Software architecture uses components as the basic building blocks of software systems. Components represent high-level software models; they must be generic enough to work in a variety of contexts and in cooperation with other components, but they also must be specific enough to provide easy reuse. To be composable with other (third-party) components, a component needs to be sufficiently self-contained. Also, it needs a clear specification of what it requires and what it provides. In other words, a component needs to encapsulate its implementation and interact with its environment by means of well-defined interfaces.
{"title":"Multicomponent Compatibility and its Verification","authors":"D. Craig, W. M. Zuberek","doi":"10.1109/ACSD.2007.56","DOIUrl":"https://doi.org/10.1109/ACSD.2007.56","url":null,"abstract":"Software architecture has been introduced with promise of better re-use of software, greater flexibility, scalability and higher quality of software services. Software architecture uses components as the basic building blocks of software systems. Components represent high-level software models; they must be generic enough to work in a variety of contexts and in cooperation with other components, but they also must be specific enough to provide easy reuse. To be composable with other (third-party) components, a component needs to be sufficiently self-contained. Also, it needs a clear specification of what it requires and what it provides. In other words, a component needs to encapsulate its implementation and interact with its environment by means of well-defined interfaces.","PeriodicalId":323657,"journal":{"name":"Seventh International Conference on Application of Concurrency to System Design (ACSD 2007)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115899018","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper we introduce executions of place/transition Petri nets with weighted inhibitor arcs (PTI-net) as enabled labeled stratified order structures (LSOs) and present a polynomial algorithm to decide, whether a scenario given by an LSO is an execution of a given PTI-net. The algorithm is based on an equivalent characterization of enabled LSOs called token flow property. Although the definition of the token flow property involves exponentially many objects in the size of the LSO, there is a nontrivial transformation into a flow optimization problem which can be solved in polynomial time.
{"title":"Testing the executability of scenarios in general inhibitor nets","authors":"R. Lorenz, S. Mauser, R. Bergenthum","doi":"10.1109/ACSD.2007.73","DOIUrl":"https://doi.org/10.1109/ACSD.2007.73","url":null,"abstract":"In this paper we introduce executions of place/transition Petri nets with weighted inhibitor arcs (PTI-net) as enabled labeled stratified order structures (LSOs) and present a polynomial algorithm to decide, whether a scenario given by an LSO is an execution of a given PTI-net. The algorithm is based on an equivalent characterization of enabled LSOs called token flow property. Although the definition of the token flow property involves exponentially many objects in the size of the LSO, there is a nontrivial transformation into a flow optimization problem which can be solved in polynomial time.","PeriodicalId":323657,"journal":{"name":"Seventh International Conference on Application of Concurrency to System Design (ACSD 2007)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125529875","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We introduce two emptiness checks for buchi automata whose states represent sets that may include each other. The first is equivalent to a traditional emptiness check but uses inclusion tests to direct the on-the-fly construction of the automaton. The second is impressively faster but may return false negatives. We illustrate and benchmark the improvement on a symmetry-based reduction.
{"title":"Emptiness Check of Powerset Buchi Automata using Inclusion Tests","authors":"S. Baarir, A. Duret-Lutz","doi":"10.1109/ACSD.2007.49","DOIUrl":"https://doi.org/10.1109/ACSD.2007.49","url":null,"abstract":"We introduce two emptiness checks for buchi automata whose states represent sets that may include each other. The first is equivalent to a traditional emptiness check but uses inclusion tests to direct the on-the-fly construction of the automaton. The second is impressively faster but may return false negatives. We illustrate and benchmark the improvement on a symmetry-based reduction.","PeriodicalId":323657,"journal":{"name":"Seventh International Conference on Application of Concurrency to System Design (ACSD 2007)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121862173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A real-time process algebra is presented that features stochastic delays governed by general distributions. In a setting of weak choice, dependent and independent alternative and parallel composition are distinguished. This enables an expansion law for the parallel operator, as well as modular process definitions. The interplay of real-time, stochastic delays and immediate actions is illustrated by a modeling of the G/G/1/infin queue.
{"title":"Real-Time Process Algebra with Stochastic Delays","authors":"J. Markovski, E. Vink","doi":"10.1109/ACSD.2007.61","DOIUrl":"https://doi.org/10.1109/ACSD.2007.61","url":null,"abstract":"A real-time process algebra is presented that features stochastic delays governed by general distributions. In a setting of weak choice, dependent and independent alternative and parallel composition are distinguished. This enables an expansion law for the parallel operator, as well as modular process definitions. The interplay of real-time, stochastic delays and immediate actions is illustrated by a modeling of the G/G/1/infin queue.","PeriodicalId":323657,"journal":{"name":"Seventh International Conference on Application of Concurrency to System Design (ACSD 2007)","volume":"33 7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123143857","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
With the advance in semiconductor technology we are able to pack more and more devices on a single chip. However, the threat comes from the long interconnect wires whose delays dominate in deep-submicron (DSM) CMOS. To handle the increased latency due the long interconnects, we require the IP cores to be latency-insensitive (LI). Design and validation of LI design is studied in L.P. Cartoni, et al., (1999), L.P. Cartoni, et al.,(2001), and T. Chelcea, et al., (2004). Generalised latency-insensitive systems, design of connecting FIFOs and other communication protocols appear in T. Chelcea, et al.,(2006), S. Dasgupta, et al., (2006), D. Potop-Butucaru, et al., (2006), and M. Singh, et al., (2003). Process algebras provide a well-studied framework for modelling and verifying concurrent systems. In this work we try to address the problem of long interconnects by modelling the latency insensitive protocol in the discrete time version of CSP. Time is modelled in terms of events occurring at regular intervals, modelled by the event took.
{"title":"Modelling Latency-Insensitive Systems in CSP","authors":"H. Kapoor","doi":"10.1109/ACSD.2007.54","DOIUrl":"https://doi.org/10.1109/ACSD.2007.54","url":null,"abstract":"With the advance in semiconductor technology we are able to pack more and more devices on a single chip. However, the threat comes from the long interconnect wires whose delays dominate in deep-submicron (DSM) CMOS. To handle the increased latency due the long interconnects, we require the IP cores to be latency-insensitive (LI). Design and validation of LI design is studied in L.P. Cartoni, et al., (1999), L.P. Cartoni, et al.,(2001), and T. Chelcea, et al., (2004). Generalised latency-insensitive systems, design of connecting FIFOs and other communication protocols appear in T. Chelcea, et al.,(2006), S. Dasgupta, et al., (2006), D. Potop-Butucaru, et al., (2006), and M. Singh, et al., (2003). Process algebras provide a well-studied framework for modelling and verifying concurrent systems. In this work we try to address the problem of long interconnects by modelling the latency insensitive protocol in the discrete time version of CSP. Time is modelled in terms of events occurring at regular intervals, modelled by the event took.","PeriodicalId":323657,"journal":{"name":"Seventh International Conference on Application of Concurrency to System Design (ACSD 2007)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123956099","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We survey research works on asynchronous systems synthesis, including PN synthesis and control synthesis.
综述了异步系统综合的研究进展，包括PN综合和控制综合。
{"title":"Synthesis and Control of Asynchronous and Distributed Systems","authors":"P. Darondeau","doi":"10.1109/ACSD.2007.71","DOIUrl":"https://doi.org/10.1109/ACSD.2007.71","url":null,"abstract":"We survey research works on asynchronous systems synthesis, including PN synthesis and control synthesis.","PeriodicalId":323657,"journal":{"name":"Seventh International Conference on Application of Concurrency to System Design (ACSD 2007)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126779663","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Sufficient conditions are given for effective model-checking of parameterized ring networks of isomorphic finite-state processes. Unlike others appearing in the literature, the present sufficient conditions do not restrict the mechanism whereby processes interact with one another, but rather the structure of the processes themselves. The results provide "cutoffs" for systems of "piecewise recognizable" processes, and show that all ring networks based on a given piecewise recognizable template fall into a finite number of weak trace equivalence classes. This result is then extended to three other finer equivalence relations: complete trace equivalence, weak failure equivalence and weak possible-futures equivalence. The paper also formalizes a notion of processes whose actions affect only a bounded number of other processes, using the property of "shuffled processes"; if a ring segment is a shuffled process, then all ring networks fall into a finite number of "weak bisimilarity" classes. It is also shown that each of the above equivalence relations preserve a subset of "observable modal logic" formulas.
{"title":"Structural Conditions for Model-checking of Parameterized Networks","authors":"S. Nazari, J. G. Thistle","doi":"10.1109/ACSD.2007.70","DOIUrl":"https://doi.org/10.1109/ACSD.2007.70","url":null,"abstract":"Sufficient conditions are given for effective model-checking of parameterized ring networks of isomorphic finite-state processes. Unlike others appearing in the literature, the present sufficient conditions do not restrict the mechanism whereby processes interact with one another, but rather the structure of the processes themselves. The results provide \"cutoffs\" for systems of \"piecewise recognizable\" processes, and show that all ring networks based on a given piecewise recognizable template fall into a finite number of weak trace equivalence classes. This result is then extended to three other finer equivalence relations: complete trace equivalence, weak failure equivalence and weak possible-futures equivalence. The paper also formalizes a notion of processes whose actions affect only a bounded number of other processes, using the property of \"shuffled processes\"; if a ring segment is a shuffled process, then all ring networks fall into a finite number of \"weak bisimilarity\" classes. It is also shown that each of the above equivalence relations preserve a subset of \"observable modal logic\" formulas.","PeriodicalId":323657,"journal":{"name":"Seventh International Conference on Application of Concurrency to System Design (ACSD 2007)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134451792","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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