Pub Date : 2017-11-02DOI: 10.1109/ECCTD.2017.8093257
S. Maheshwari, V. A. Bartlett, I. Kale
We propose novel resettable adiabatic buffers for five adiabatic logic families namely; Efficient Adiabatic Charge Recovery Logic (EACRL), Improved Efficient Charge Recovery Logic (IECRL), Positive Feedback Adiabatic Logic (PFAL), Complementary Pass-transistor Adiabatic Logic (CPAL) and Clocked Adiabatic Logic (CAL). We present the design of resettable flip-flops using the proposed buffers. The proposed flip-flops alleviate the problem of increased energy and area consumption incurred by the existing mux-based resettable flip-flops. We then design the 3-bit up-down counters and extended our comparison beyond energy dissipation using the above five adiabatic logic families. PFAL based sequential circuit designs gives the best performance trade-offs in terms of complexity, energy, speed and area compared to the other adiabatic designs.
{"title":"Adiabatic flip-flops and sequential circuit design using novel resettable adiabatic buffers","authors":"S. Maheshwari, V. A. Bartlett, I. Kale","doi":"10.1109/ECCTD.2017.8093257","DOIUrl":"https://doi.org/10.1109/ECCTD.2017.8093257","url":null,"abstract":"We propose novel resettable adiabatic buffers for five adiabatic logic families namely; Efficient Adiabatic Charge Recovery Logic (EACRL), Improved Efficient Charge Recovery Logic (IECRL), Positive Feedback Adiabatic Logic (PFAL), Complementary Pass-transistor Adiabatic Logic (CPAL) and Clocked Adiabatic Logic (CAL). We present the design of resettable flip-flops using the proposed buffers. The proposed flip-flops alleviate the problem of increased energy and area consumption incurred by the existing mux-based resettable flip-flops. We then design the 3-bit up-down counters and extended our comparison beyond energy dissipation using the above five adiabatic logic families. PFAL based sequential circuit designs gives the best performance trade-offs in terms of complexity, energy, speed and area compared to the other adiabatic designs.","PeriodicalId":324679,"journal":{"name":"2017 European Conference on Circuit Theory and Design (ECCTD)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128426723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-02DOI: 10.1109/ECCTD.2017.8093326
M. Siddique, Enrico Roverato, M. Kosunen, J. Ryynänen
Ihis paper evaluates the pertormance ot dynamic element matching (DEM) in digital-to-analog-converters, when the unit conversion cells of the converter have finite output resistance. DEM is already known to be effective against the static amplitude, timing and pulse shaped mismatches. However, the effect of output resistance and its mismatches has not been studied. A comprehensive code-dependent output resistance model for the current-steering DAC is presented. System level simulations show that the non-linearity caused by the output resistance, in the absence of mismatches, is not shaped by the DEM encoder since the output resistance is same for all the conversion cells. In this paper we demonstrate that, in the presence of mismatches, the DEM encoder is able to shape the non-linearity they cause since the output resistance now varies among different conversion cells.
{"title":"Dynamic element matching in digital-to-analog converters with code-dependent output resistance","authors":"M. Siddique, Enrico Roverato, M. Kosunen, J. Ryynänen","doi":"10.1109/ECCTD.2017.8093326","DOIUrl":"https://doi.org/10.1109/ECCTD.2017.8093326","url":null,"abstract":"Ihis paper evaluates the pertormance ot dynamic element matching (DEM) in digital-to-analog-converters, when the unit conversion cells of the converter have finite output resistance. DEM is already known to be effective against the static amplitude, timing and pulse shaped mismatches. However, the effect of output resistance and its mismatches has not been studied. A comprehensive code-dependent output resistance model for the current-steering DAC is presented. System level simulations show that the non-linearity caused by the output resistance, in the absence of mismatches, is not shaped by the DEM encoder since the output resistance is same for all the conversion cells. In this paper we demonstrate that, in the presence of mismatches, the DEM encoder is able to shape the non-linearity they cause since the output resistance now varies among different conversion cells.","PeriodicalId":324679,"journal":{"name":"2017 European Conference on Circuit Theory and Design (ECCTD)","volume":"2009 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125621893","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-31DOI: 10.1109/ECCTD.2017.8093316
A. Kushnerov, T. Liang, A. Yakovlev
The paper proposes a method to use the Fibonacci numbers with odd and even indices for synthesis of switched capacitor converters (SCCs) with multiphase control. As in the previously developed method using high-radix positional numeral systems, the capacitors in the proposed method can be connected in parallel. For this purpose, a special two-dimensional (2D) array of switches is introduced. Thus, all the available earlier target voltages as well as those defined by the Fibonacci numbers with odd and even indices, can be obtained using the same array of switches. Owing to small distance between the neighboring target voltages, the total SCC efficiency can be increased. The theoretical results were verified by simulations.
{"title":"Multiphase ternary Fibonacci 2D switched capacitor converters","authors":"A. Kushnerov, T. Liang, A. Yakovlev","doi":"10.1109/ECCTD.2017.8093316","DOIUrl":"https://doi.org/10.1109/ECCTD.2017.8093316","url":null,"abstract":"The paper proposes a method to use the Fibonacci numbers with odd and even indices for synthesis of switched capacitor converters (SCCs) with multiphase control. As in the previously developed method using high-radix positional numeral systems, the capacitors in the proposed method can be connected in parallel. For this purpose, a special two-dimensional (2D) array of switches is introduced. Thus, all the available earlier target voltages as well as those defined by the Fibonacci numbers with odd and even indices, can be obtained using the same array of switches. Owing to small distance between the neighboring target voltages, the total SCC efficiency can be increased. The theoretical results were verified by simulations.","PeriodicalId":324679,"journal":{"name":"2017 European Conference on Circuit Theory and Design (ECCTD)","volume":"7 12","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120858990","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-10-31DOI: 10.1109/ECCTD.2017.8093234
Debashis Dhar, Paul T. M. van Zeijl, D. Milosevic, Hao Gao, P. Baltus
Noise of the charge pump degrades the in-band phase noise of charge pump phase-locked loop (CPPLL). This paper analyzes the noise mechanism of a bipolar junction transistor based charge pump and validates the analysis through simulation, providing necessary insight into the design of low-noise charge pump for CPPLL-based frequency synthesizers. A simple model for bipolar transistor noise is utilized to carry out the noise analysis. The scaling effects of the duty cycle and the rise/fall time of the input signals on the charge pump noise are also analyzed in detail. The analysis reveals that increased charge pump current reduces the PLL phase noise and that a trade-off exists between the area and the noise of the charge pump.
{"title":"Noise analysis of a BJT-based charge pump for low-noise PLL applications","authors":"Debashis Dhar, Paul T. M. van Zeijl, D. Milosevic, Hao Gao, P. Baltus","doi":"10.1109/ECCTD.2017.8093234","DOIUrl":"https://doi.org/10.1109/ECCTD.2017.8093234","url":null,"abstract":"Noise of the charge pump degrades the in-band phase noise of charge pump phase-locked loop (CPPLL). This paper analyzes the noise mechanism of a bipolar junction transistor based charge pump and validates the analysis through simulation, providing necessary insight into the design of low-noise charge pump for CPPLL-based frequency synthesizers. A simple model for bipolar transistor noise is utilized to carry out the noise analysis. The scaling effects of the duty cycle and the rise/fall time of the input signals on the charge pump noise are also analyzed in detail. The analysis reveals that increased charge pump current reduces the PLL phase noise and that a trade-off exists between the area and the noise of the charge pump.","PeriodicalId":324679,"journal":{"name":"2017 European Conference on Circuit Theory and Design (ECCTD)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129848682","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-09-04DOI: 10.1109/ECCTD.2017.8093273
N. Herencsar, A. Kartci, J. Koton, G. Tsirimokou, C. Psychalinos
The paper presents a new active building block (ABB) called minus-type voltage gain-controlled third-generation current conveyor (VGC-CCIII-) in which the voltage gain between Y to X terminal can be controlled. The usefulness of the tunable feature in the presented ABB is demonstrated in current-mode {0.3rd; 0.5th; 0.7th; Ist}-order all-pass filter (APF) employing single VGC-CCIII-, one capacitor, and one resistor. The theoretical results of the integer- and fractional-order APF are verified by SPICE simulations based on readily available IC OPA860 macromodel, which can also be used in experiments.
{"title":"Voltage gain-controlled third-generation current conveyor and its all-pass filter verification","authors":"N. Herencsar, A. Kartci, J. Koton, G. Tsirimokou, C. Psychalinos","doi":"10.1109/ECCTD.2017.8093273","DOIUrl":"https://doi.org/10.1109/ECCTD.2017.8093273","url":null,"abstract":"The paper presents a new active building block (ABB) called minus-type voltage gain-controlled third-generation current conveyor (VGC-CCIII-) in which the voltage gain between Y to X terminal can be controlled. The usefulness of the tunable feature in the presented ABB is demonstrated in current-mode {0.3rd; 0.5th; 0.7th; Ist}-order all-pass filter (APF) employing single VGC-CCIII-, one capacitor, and one resistor. The theoretical results of the integer- and fractional-order APF are verified by SPICE simulations based on readily available IC OPA860 macromodel, which can also be used in experiments.","PeriodicalId":324679,"journal":{"name":"2017 European Conference on Circuit Theory and Design (ECCTD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130332546","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-09-04DOI: 10.1109/ECCTD.2017.8093281
A. Kartci, N. Herencsar, J. Koton, C. Psychalinos
A new voltage-mode fractional-order oscillator, employing in total 12 Metal-Oxide-Semiconductor (MOS) transistors, is introduced in this paper. The proposed circuit is composed of two operational transconductance amplifiers, two inverting voltage buffers, one resistor, and two fractional-order capacitors. Compared with the corresponding already introduced fractional-order oscillators, it offers the benefit of low transistor count and, therefore, simplicity of its structure. In addition, it offers the well-known advantages of fractional-order oscillators about the capability for achieving very low and high oscillation frequencies with reasonable component values. The behavior of the proposed oscillator has been numerically studied using the MATLAB program, while its performance has been evaluated by SPICE simulations, using TSMC 0.18 μm Level-7 CMOS process parameters with ±I V supply voltages.
{"title":"Compact MOS-RC voltage-mode fractional-order oscillator design","authors":"A. Kartci, N. Herencsar, J. Koton, C. Psychalinos","doi":"10.1109/ECCTD.2017.8093281","DOIUrl":"https://doi.org/10.1109/ECCTD.2017.8093281","url":null,"abstract":"A new voltage-mode fractional-order oscillator, employing in total 12 Metal-Oxide-Semiconductor (MOS) transistors, is introduced in this paper. The proposed circuit is composed of two operational transconductance amplifiers, two inverting voltage buffers, one resistor, and two fractional-order capacitors. Compared with the corresponding already introduced fractional-order oscillators, it offers the benefit of low transistor count and, therefore, simplicity of its structure. In addition, it offers the well-known advantages of fractional-order oscillators about the capability for achieving very low and high oscillation frequencies with reasonable component values. The behavior of the proposed oscillator has been numerically studied using the MATLAB program, while its performance has been evaluated by SPICE simulations, using TSMC 0.18 μm Level-7 CMOS process parameters with ±I V supply voltages.","PeriodicalId":324679,"journal":{"name":"2017 European Conference on Circuit Theory and Design (ECCTD)","volume":"178 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123413577","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-09-01DOI: 10.1109/ECCTD.2017.8093357
M. Alanovic, D. Jurišić, G. Moschytz
A general method of determining the parameters for a well-known noise model of a second-generation current conveyor (CCII) is presented. The method is used to determine the thermal noise model parameters for two different CMOS CCII implementations. The simulation is carried out with the parameters of the AMS 0.35 μm technology using PSpice. For one of the analyzed implementations, the thermal noise model parameters are also derived analytically. They are shown to be in good agreement with the ones obtained by simulation.
{"title":"Determination of second-generation current conveyor noise-model parameters","authors":"M. Alanovic, D. Jurišić, G. Moschytz","doi":"10.1109/ECCTD.2017.8093357","DOIUrl":"https://doi.org/10.1109/ECCTD.2017.8093357","url":null,"abstract":"A general method of determining the parameters for a well-known noise model of a second-generation current conveyor (CCII) is presented. The method is used to determine the thermal noise model parameters for two different CMOS CCII implementations. The simulation is carried out with the parameters of the AMS 0.35 μm technology using PSpice. For one of the analyzed implementations, the thermal noise model parameters are also derived analytically. They are shown to be in good agreement with the ones obtained by simulation.","PeriodicalId":324679,"journal":{"name":"2017 European Conference on Circuit Theory and Design (ECCTD)","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123323933","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-09-01DOI: 10.1109/ECCTD.2017.8093283
Tuan Minh Vo, A. Matsuzawa
The adoption of charge-redistribution-technique-based successive approximation register (SAR) architecture in capacitance domain has improved the performance of the digital readout circuit used for capacitive sensor applications. The direct conversion of an off-chip sensor's capacitance to a digital value requires a large implemented capacitor array. A scale factor scaling the reference voltage is used to reduce the overall value of the capacitor array, though at the price of increasing power consumption due to a multi-level voltage divider is required. Moreover, the scale factor is adjusted manually which is not acceptable in practice. To overcome this problem, we propose an innovative algorithm which adapts automatically and exactly the off-chip capacitance to the implemented capacitance without using the multi-level voltage divider. The proposed algorithm is operated fully in digital domain which is straightforward for implementation. The effectiveness of the automatic dynamic range adaptation scheme is demonstrated via behavioral-level simulations of a differential capacitance/digital converter.
{"title":"An automatic dynamic range adaptation algorithm for capacitive sensor interface circuits","authors":"Tuan Minh Vo, A. Matsuzawa","doi":"10.1109/ECCTD.2017.8093283","DOIUrl":"https://doi.org/10.1109/ECCTD.2017.8093283","url":null,"abstract":"The adoption of charge-redistribution-technique-based successive approximation register (SAR) architecture in capacitance domain has improved the performance of the digital readout circuit used for capacitive sensor applications. The direct conversion of an off-chip sensor's capacitance to a digital value requires a large implemented capacitor array. A scale factor scaling the reference voltage is used to reduce the overall value of the capacitor array, though at the price of increasing power consumption due to a multi-level voltage divider is required. Moreover, the scale factor is adjusted manually which is not acceptable in practice. To overcome this problem, we propose an innovative algorithm which adapts automatically and exactly the off-chip capacitance to the implemented capacitance without using the multi-level voltage divider. The proposed algorithm is operated fully in digital domain which is straightforward for implementation. The effectiveness of the automatic dynamic range adaptation scheme is demonstrated via behavioral-level simulations of a differential capacitance/digital converter.","PeriodicalId":324679,"journal":{"name":"2017 European Conference on Circuit Theory and Design (ECCTD)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114949798","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-09-01DOI: 10.1109/ECCTD.2017.8093341
A. D. Grasso, M. Vaiana, G. Bruno
This paper presents a trimming correction technique to calibrate the offset in capacitive readout circuits of MEMS sensors. The technique relies on a N-bit digital voltage divider which allows to implement an equivalent variable capacitor with sub-femto Farad step variations. To reduce area occupation, a hybrid approach entailing both resistive and capacitor voltage dividers is introduced. Design equations showing the tradeoff between linearity and area occupation versus relative mismatch of capacitors and resistors are derived. Design examples are reported showing a reduction of area occupation greater than 60% while preserving linearity performance.
{"title":"Area-optimized sub-fF offset trimming circuit for capacitive MEMS interfaces","authors":"A. D. Grasso, M. Vaiana, G. Bruno","doi":"10.1109/ECCTD.2017.8093341","DOIUrl":"https://doi.org/10.1109/ECCTD.2017.8093341","url":null,"abstract":"This paper presents a trimming correction technique to calibrate the offset in capacitive readout circuits of MEMS sensors. The technique relies on a N-bit digital voltage divider which allows to implement an equivalent variable capacitor with sub-femto Farad step variations. To reduce area occupation, a hybrid approach entailing both resistive and capacitor voltage dividers is introduced. Design equations showing the tradeoff between linearity and area occupation versus relative mismatch of capacitors and resistors are derived. Design examples are reported showing a reduction of area occupation greater than 60% while preserving linearity performance.","PeriodicalId":324679,"journal":{"name":"2017 European Conference on Circuit Theory and Design (ECCTD)","volume":"127 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115550366","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-09-01DOI: 10.1109/ECCTD.2017.8093287
D. Vodenicarevic, A. Mizrahi, N. Locatelli, J. Grollier, D. Querlioz
Spintronic nanodevices — which exploit both the magnetic and electric properties of electrons — are a major break-through for nanoelectronics. The flagship device of spintronics, the magnetic tunnel junction, naturally provides a binary memristive device with outstanding endurance, high speed and low energy consumption. Interestingly, relying on the same physics as their use as memristive devices, magnetic tunnel junctions may also be used as a type of voltage controlled oscillators: at a given voltage, oscillations in their electrical resistance and currents can be observed. Depending on the tuning of the devices geometrical and magnetic properties, the oscillations can be slow and stochastic, or fast and quasi-harmonic. In this work, we introduce experimentally validated models for these two regimes. We discuss the synchronization potential of these oscillators, as well as their possible use in unconventional circuits. Prospects for bioinspired systems are given. This work raises important questions regarding the use of nanooscillators in circuits, which we discuss in conclusion.
{"title":"Spintronic nanoscillators for unconventional circuits","authors":"D. Vodenicarevic, A. Mizrahi, N. Locatelli, J. Grollier, D. Querlioz","doi":"10.1109/ECCTD.2017.8093287","DOIUrl":"https://doi.org/10.1109/ECCTD.2017.8093287","url":null,"abstract":"Spintronic nanodevices — which exploit both the magnetic and electric properties of electrons — are a major break-through for nanoelectronics. The flagship device of spintronics, the magnetic tunnel junction, naturally provides a binary memristive device with outstanding endurance, high speed and low energy consumption. Interestingly, relying on the same physics as their use as memristive devices, magnetic tunnel junctions may also be used as a type of voltage controlled oscillators: at a given voltage, oscillations in their electrical resistance and currents can be observed. Depending on the tuning of the devices geometrical and magnetic properties, the oscillations can be slow and stochastic, or fast and quasi-harmonic. In this work, we introduce experimentally validated models for these two regimes. We discuss the synchronization potential of these oscillators, as well as their possible use in unconventional circuits. Prospects for bioinspired systems are given. This work raises important questions regarding the use of nanooscillators in circuits, which we discuss in conclusion.","PeriodicalId":324679,"journal":{"name":"2017 European Conference on Circuit Theory and Design (ECCTD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130374844","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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