Pub Date : 2015-06-08DOI: 10.1109/SIES.2015.7185035
N. Mahmud, C. Seceleanu, Oscar Ljungkrantz
Automotive systems are developed using multi-leveled architectural abstractions in an attempt to manage the increasing complexity and criticality of automotive functions. Consequently, well-structured and unambiguously specified requirements are needed on all levels of abstraction, in order to enable early detection of possible design errors. However, automotive industry often relies on requirements specified in ambiguous natural language, sometimes in large and incomprehensible documents. Semi-formal requirements specification approaches (e.g., requirement boilerplates, pattern-based specifications, etc.) aim to reduce requirements ambiguity, without altering their readability and expressiveness. Nevertheless, such approaches do not offer support for specifying requirements in terms of multi-leveled architectural concepts, nor do they provide means for early-stage rigorous analysis of the specified requirements. In this paper, we propose a language, called ReSA, which allows requirements specification at various levels of abstraction, modeled in the architectural language of EAST-ADL. ReSA uses an automotive systems' ontology that offers typing and syntactic axioms for the specification. Besides enforcing structure and more rigor in specifying requirements, our approach enables checking refinement as well as consistency of requirements, by proving ordinary boolean implications. To illustrate ReSA's applicability, we show how to specify some requirements of the Adjustable Speed Limiter, which is a complex, safety-critical Volvo Trucks user function.
{"title":"ReSA: An ontology-based requirement specification language tailored to automotive systems","authors":"N. Mahmud, C. Seceleanu, Oscar Ljungkrantz","doi":"10.1109/SIES.2015.7185035","DOIUrl":"https://doi.org/10.1109/SIES.2015.7185035","url":null,"abstract":"Automotive systems are developed using multi-leveled architectural abstractions in an attempt to manage the increasing complexity and criticality of automotive functions. Consequently, well-structured and unambiguously specified requirements are needed on all levels of abstraction, in order to enable early detection of possible design errors. However, automotive industry often relies on requirements specified in ambiguous natural language, sometimes in large and incomprehensible documents. Semi-formal requirements specification approaches (e.g., requirement boilerplates, pattern-based specifications, etc.) aim to reduce requirements ambiguity, without altering their readability and expressiveness. Nevertheless, such approaches do not offer support for specifying requirements in terms of multi-leveled architectural concepts, nor do they provide means for early-stage rigorous analysis of the specified requirements. In this paper, we propose a language, called ReSA, which allows requirements specification at various levels of abstraction, modeled in the architectural language of EAST-ADL. ReSA uses an automotive systems' ontology that offers typing and syntactic axioms for the specification. Besides enforcing structure and more rigor in specifying requirements, our approach enables checking refinement as well as consistency of requirements, by proving ordinary boolean implications. To illustrate ReSA's applicability, we show how to specify some requirements of the Adjustable Speed Limiter, which is a complex, safety-critical Volvo Trucks user function.","PeriodicalId":328716,"journal":{"name":"10th IEEE International Symposium on Industrial Embedded Systems (SIES)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117234633","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-06-08DOI: 10.1109/SIES.2015.7185042
M. Cheminod, L. Durante, L. Seno, A. Valenzano
The increasing adoption of networked embedded devices in the industrial scenario demands for new techniques and computer-aided tools that could help in designing, deploying and maintaining large and complex systems. This is true, in particular, when access control is considered, since the hardware and software characteristics of many industrial embedded devices prevent the introduction of policies enforcement mechanisms at a global system level. This paper deals with our experience in analyzing the correct implementation of access policies in a medium-sized real-world system. Our approach is based on an innovative type of model and software analyzer, which is able to compare two different views of the target system, described at different abstraction levels.
{"title":"Analysis of access control policies in networked embedded systems: A case study","authors":"M. Cheminod, L. Durante, L. Seno, A. Valenzano","doi":"10.1109/SIES.2015.7185042","DOIUrl":"https://doi.org/10.1109/SIES.2015.7185042","url":null,"abstract":"The increasing adoption of networked embedded devices in the industrial scenario demands for new techniques and computer-aided tools that could help in designing, deploying and maintaining large and complex systems. This is true, in particular, when access control is considered, since the hardware and software characteristics of many industrial embedded devices prevent the introduction of policies enforcement mechanisms at a global system level. This paper deals with our experience in analyzing the correct implementation of access policies in a medium-sized real-world system. Our approach is based on an innovative type of model and software analyzer, which is able to compare two different views of the target system, described at different abstraction levels.","PeriodicalId":328716,"journal":{"name":"10th IEEE International Symposium on Industrial Embedded Systems (SIES)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126177290","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-06-08DOI: 10.1109/SIES.2015.7185036
Simon Gansel, Stephan Schnitzer, Riccardo Cecolin, Frank Dürr, K. Rothermel, Christian Maihöfer
The relevance of graphical functions in vehicular applications has increased significantly during the last years. Modern cars are equipped with multiple displays used by different applications such as speedometer, navigation system, or media players. The rendered output of the applications is stored in so-called off-screen buffers and then bitblitted to the screen buffer at the respective window sizes and positions. To guarantee the visibility of the potentially overlapping windows, the compositing has to match the z-order of the windows. To this end, two common compositing strategies Tile compositing and Full compositing are used, each having performance issues depending on how windows overlap. Since automotive embedded platforms are restricted in power consumption, installation space, and hardware cost, their performance is limited which effectuates the need for highly efficient bitblitting. In order to increase the performance in compositing the windows, we propose Hybrid Compositing which predicts the required bitblitting time and chooses the most efficient strategy for each pair of overlapping windows. Using various scenarios we show that our approach is faster than the other strategies. In addition, we propose CacheHybrid Compositing which reduces the CPU execution time of our approach by up to 66 %. In case of an automotive scenario we show that our optimized approach saves up to 51% bitblitting time compared to existing approaches.
{"title":"Efficient compositing strategies for automotive HMI systems","authors":"Simon Gansel, Stephan Schnitzer, Riccardo Cecolin, Frank Dürr, K. Rothermel, Christian Maihöfer","doi":"10.1109/SIES.2015.7185036","DOIUrl":"https://doi.org/10.1109/SIES.2015.7185036","url":null,"abstract":"The relevance of graphical functions in vehicular applications has increased significantly during the last years. Modern cars are equipped with multiple displays used by different applications such as speedometer, navigation system, or media players. The rendered output of the applications is stored in so-called off-screen buffers and then bitblitted to the screen buffer at the respective window sizes and positions. To guarantee the visibility of the potentially overlapping windows, the compositing has to match the z-order of the windows. To this end, two common compositing strategies Tile compositing and Full compositing are used, each having performance issues depending on how windows overlap. Since automotive embedded platforms are restricted in power consumption, installation space, and hardware cost, their performance is limited which effectuates the need for highly efficient bitblitting. In order to increase the performance in compositing the windows, we propose Hybrid Compositing which predicts the required bitblitting time and chooses the most efficient strategy for each pair of overlapping windows. Using various scenarios we show that our approach is faster than the other strategies. In addition, we propose CacheHybrid Compositing which reduces the CPU execution time of our approach by up to 66 %. In case of an automotive scenario we show that our optimized approach saves up to 51% bitblitting time compared to existing approaches.","PeriodicalId":328716,"journal":{"name":"10th IEEE International Symposium on Industrial Embedded Systems (SIES)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123970472","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-06-08DOI: 10.1109/SIES.2015.7185045
Dinh-Khanh Dang, A. Mifdaoui
With the technological progress of wireless technologies, an alternative avionic communication architecture based on wireless connectivity has been proposed to cope with the emerging avionics issues, i.e., reducing weight and costs. The performance analysis of such a proposal is conducted herein to quantify the impact of unreliable wireless links on transmission delays, and the efficiency of retransmission-based mechanisms to enhance the system reliability. First, an adequate system modeling, based on Stochastic Network Calculus, to capture the loss process of unreliable links is detailed. Then, stochastic end-to-end delay bounds are analyzed. Finally, the introduced approach is illustrated through a representative avionics case study. Numerical results show the efficiency of such a proposal to enhance the system's reliability and scalability.
{"title":"Stochastic delay analysis of a wireless safety-critical avionics network","authors":"Dinh-Khanh Dang, A. Mifdaoui","doi":"10.1109/SIES.2015.7185045","DOIUrl":"https://doi.org/10.1109/SIES.2015.7185045","url":null,"abstract":"With the technological progress of wireless technologies, an alternative avionic communication architecture based on wireless connectivity has been proposed to cope with the emerging avionics issues, i.e., reducing weight and costs. The performance analysis of such a proposal is conducted herein to quantify the impact of unreliable wireless links on transmission delays, and the efficiency of retransmission-based mechanisms to enhance the system reliability. First, an adequate system modeling, based on Stochastic Network Calculus, to capture the loss process of unreliable links is detailed. Then, stochastic end-to-end delay bounds are analyzed. Finally, the introduced approach is illustrated through a representative avionics case study. Numerical results show the efficiency of such a proposal to enhance the system's reliability and scalability.","PeriodicalId":328716,"journal":{"name":"10th IEEE International Symposium on Industrial Embedded Systems (SIES)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126430789","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-06-08DOI: 10.1109/SIES.2015.7185068
Wei Sun, A. Girault, G. Delaval
We demonstrate the feasibility of a complete workflow to synthesize and implement correct-by-construction fault tolerant distributed embedded systems consisting of real-time periodic tasks. Correct-by-construction is provided by the use of discrete controller synthesis (DCS), a formal method thanks to which we are able to guarantee that the synthesized controlled system guarantees the functionality of its tasks even in the presence of processor failures. For this step, our workflow uses the Heptagon domain specific language and the Sigali DCS tool. The correct implementation of the resulting distributed system is a challenge, all the more since the controller itself must be tolerant to the processor failures. We achieve this step thanks to the libDGALS realtime library (1) to generate the glue code that will migrate the tasks upon processor failures, maintaining their internal state through migration, and (2) to make the synthesized controller itself fault-tolerant.
{"title":"A formal approach for the synthesis and implementation of fault-tolerant industrial embedded systems","authors":"Wei Sun, A. Girault, G. Delaval","doi":"10.1109/SIES.2015.7185068","DOIUrl":"https://doi.org/10.1109/SIES.2015.7185068","url":null,"abstract":"We demonstrate the feasibility of a complete workflow to synthesize and implement correct-by-construction fault tolerant distributed embedded systems consisting of real-time periodic tasks. Correct-by-construction is provided by the use of discrete controller synthesis (DCS), a formal method thanks to which we are able to guarantee that the synthesized controlled system guarantees the functionality of its tasks even in the presence of processor failures. For this step, our workflow uses the Heptagon domain specific language and the Sigali DCS tool. The correct implementation of the resulting distributed system is a challenge, all the more since the controller itself must be tolerant to the processor failures. We achieve this step thanks to the libDGALS realtime library (1) to generate the glue code that will migrate the tasks upon processor failures, maintaining their internal state through migration, and (2) to make the synthesized controller itself fault-tolerant.","PeriodicalId":328716,"journal":{"name":"10th IEEE International Symposium on Industrial Embedded Systems (SIES)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132203449","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-06-08DOI: 10.1109/SIES.2015.7185064
Dominik Reinhardt, Maximilian Güntner, M. Kucera, T. Waas, Winfried E. Kühnhauser
Intelligent driver assistance systems and new infotainment innovations cause a rapidly growing demand of computing power. To satisfy that demand, the quantity of electronic control units in cars has increased dramatically. OEMs tackle that trend by consolidating software on powerful multicore hardware platforms. However, current software solutions are mostly static and designed to run on limited platforms. As promising operating system for automotive, Linux comes into consideration, which seems to scale better than already existing solutions. To ease the migration process of older software parts and guarantee freedom from interference according to ISO26262 between single software partitions, embedded hypervisors can achieve that requirements. Up to now, automotive systems are not developed to run within virtualized environments. Within this paper, we present an approach to map communication channels of virtual automotive ECUs and connect them with their already existing CAN interfaces. For our analysis, we use the Xen hypervisor. The focus for interaction between virtual machines is to use SocketCAN and given paravirtualized Ethernet drivers. Our goal is a non-intrusive software integration methodology. We keep the source code within software partitions as unmodified as possible. To benchmark our studies, we evaluate our implementation on the Intel i7 and the.
{"title":"Mapping CAN-to-ethernet communication channels within virtualized embedded environments","authors":"Dominik Reinhardt, Maximilian Güntner, M. Kucera, T. Waas, Winfried E. Kühnhauser","doi":"10.1109/SIES.2015.7185064","DOIUrl":"https://doi.org/10.1109/SIES.2015.7185064","url":null,"abstract":"Intelligent driver assistance systems and new infotainment innovations cause a rapidly growing demand of computing power. To satisfy that demand, the quantity of electronic control units in cars has increased dramatically. OEMs tackle that trend by consolidating software on powerful multicore hardware platforms. However, current software solutions are mostly static and designed to run on limited platforms. As promising operating system for automotive, Linux comes into consideration, which seems to scale better than already existing solutions. To ease the migration process of older software parts and guarantee freedom from interference according to ISO26262 between single software partitions, embedded hypervisors can achieve that requirements. Up to now, automotive systems are not developed to run within virtualized environments. Within this paper, we present an approach to map communication channels of virtual automotive ECUs and connect them with their already existing CAN interfaces. For our analysis, we use the Xen hypervisor. The focus for interaction between virtual machines is to use SocketCAN and given paravirtualized Ethernet drivers. Our goal is a non-intrusive software integration methodology. We keep the source code within software partitions as unmodified as possible. To benchmark our studies, we evaluate our implementation on the Intel i7 and the.","PeriodicalId":328716,"journal":{"name":"10th IEEE International Symposium on Industrial Embedded Systems (SIES)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128378162","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-06-08DOI: 10.1109/SIES.2015.7185062
Matthias Becker, N. Khalilzad, R. J. Bril, Thomas Nolte
Fixed Priority Scheduling (FPS) is the de facto standard in industry and it is the scheduling algorithm used in OSEK/AUTOSAR. Applications in such systems are compositions of so-called runnables, the functional entities of the system. Runnables are mapped to operating system tasks during system synthesis. In order to improve system performance it is proposed to execute runnables non-preemptively while varying the tasks threshold between runnables. This allows simpler resource access, which can reduce the stack usage of the system and improve the schedulability of the task sets. FPDS*, as a special case of fixed-priority scheduling with deferred preemptions, executes subjobs non-preemptively and preemption points have preemption thresholds, providing exactly the proposed behavior. However OSEK/AUTOSAR-conform systems cannot execute such schedules. In this paper we present an approach allowing the execution of FPDS* schedules. In our approach we exploit pseudo resources in order to implement FPDS*. It is further shown that our optimal algorithm produces a minimum number of resource accesses. In addition, a simulation-based evaluation is presented in which the number of resource accesses as well as the number of required pseudo-resources by the proposed algorithms are investigated. Finally, we report the overhead of resource access primitives using our measurements performed on an AUTOSAR-compliant operating system.
{"title":"Extended support for limited preemption fixed priority scheduling for OSEK/AUTOSAR-compliant operating systems","authors":"Matthias Becker, N. Khalilzad, R. J. Bril, Thomas Nolte","doi":"10.1109/SIES.2015.7185062","DOIUrl":"https://doi.org/10.1109/SIES.2015.7185062","url":null,"abstract":"Fixed Priority Scheduling (FPS) is the de facto standard in industry and it is the scheduling algorithm used in OSEK/AUTOSAR. Applications in such systems are compositions of so-called runnables, the functional entities of the system. Runnables are mapped to operating system tasks during system synthesis. In order to improve system performance it is proposed to execute runnables non-preemptively while varying the tasks threshold between runnables. This allows simpler resource access, which can reduce the stack usage of the system and improve the schedulability of the task sets. FPDS*, as a special case of fixed-priority scheduling with deferred preemptions, executes subjobs non-preemptively and preemption points have preemption thresholds, providing exactly the proposed behavior. However OSEK/AUTOSAR-conform systems cannot execute such schedules. In this paper we present an approach allowing the execution of FPDS* schedules. In our approach we exploit pseudo resources in order to implement FPDS*. It is further shown that our optimal algorithm produces a minimum number of resource accesses. In addition, a simulation-based evaluation is presented in which the number of resource accesses as well as the number of required pseudo-resources by the proposed algorithms are investigated. Finally, we report the overhead of resource access primitives using our measurements performed on an AUTOSAR-compliant operating system.","PeriodicalId":328716,"journal":{"name":"10th IEEE International Symposium on Industrial Embedded Systems (SIES)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130036468","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-06-08DOI: 10.1109/SIES.2015.7185054
Christian Scholer, Rene Krenz-Baath, Ayman Murshed, R. Obermaisser
Many embedded systems are deployed with multi-core platforms where processor cores are interconnected by networks-on-a-chip. Time-triggered networks-on-a-chip are ideal for safety-critical systems due to the inherent fault isolation and temporal predictability. However, a communication schedule is required that determines for each message the points in time for the injection of messages at the network interface as well as conflict-free paths through the network-on-a-chip. The schedule ensures that at a given point in time only one flit traverses the physical link between two router ports, thereby avoiding the need for dynamic arbitration and improving temporal predictability. This paper introduces an optimal scheduler based on a Boolean SAT solver for a time-triggered network-on-a-chip. By adopting this solver technique from the area of Electronic Design Automation (EDA) we have observed a significant reduction of the computation time for optimal schedules in several example scenarios. The evaluation was performed by comparing the SAT-based scheduler with an optimal scheduler using Mixed Integer Linear Programming (MILP). Due to the low computational time, we expect that the scheduling algorithm can replace heuristics in many applications.
{"title":"Optimal SAT-based scheduler for time-triggered networks-on-a-chip","authors":"Christian Scholer, Rene Krenz-Baath, Ayman Murshed, R. Obermaisser","doi":"10.1109/SIES.2015.7185054","DOIUrl":"https://doi.org/10.1109/SIES.2015.7185054","url":null,"abstract":"Many embedded systems are deployed with multi-core platforms where processor cores are interconnected by networks-on-a-chip. Time-triggered networks-on-a-chip are ideal for safety-critical systems due to the inherent fault isolation and temporal predictability. However, a communication schedule is required that determines for each message the points in time for the injection of messages at the network interface as well as conflict-free paths through the network-on-a-chip. The schedule ensures that at a given point in time only one flit traverses the physical link between two router ports, thereby avoiding the need for dynamic arbitration and improving temporal predictability. This paper introduces an optimal scheduler based on a Boolean SAT solver for a time-triggered network-on-a-chip. By adopting this solver technique from the area of Electronic Design Automation (EDA) we have observed a significant reduction of the computation time for optimal schedules in several example scenarios. The evaluation was performed by comparing the SAT-based scheduler with an optimal scheduler using Mixed Integer Linear Programming (MILP). Due to the low computational time, we expect that the scheduling algorithm can replace heuristics in many applications.","PeriodicalId":328716,"journal":{"name":"10th IEEE International Symposium on Industrial Embedded Systems (SIES)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130907389","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-06-08DOI: 10.1109/SIES.2015.7185059
D. Müller, A. Burns
We propose a new method to compute period choice restrictions based on a given maximum number of tasks in a task set, some pre-set period values, and a goal utilization bound ensuring the meeting of all deadlines under preemptive Rate-monotonic Scheduling (RMS) on a uniprocessor. The new approach is motivated by demonstrating that a safe utilization bound can be significantly increased by taking period configuration data into account. The two well-known approaches of the period-independent Liu/Layland bound and the harmonic chain method restriction which enforces new periods to be integer multiples or parts of pre-set periods are discussed. It will turn out that our new approach can serve as a trade-off balancing the two goals of a weak period choice restriction and a high utilization bound. Subsequently, we justify and demonstrate it by several examples and derive some rules of thumb.
{"title":"Deriving period restrictions from a given utilization bound under RMS","authors":"D. Müller, A. Burns","doi":"10.1109/SIES.2015.7185059","DOIUrl":"https://doi.org/10.1109/SIES.2015.7185059","url":null,"abstract":"We propose a new method to compute period choice restrictions based on a given maximum number of tasks in a task set, some pre-set period values, and a goal utilization bound ensuring the meeting of all deadlines under preemptive Rate-monotonic Scheduling (RMS) on a uniprocessor. The new approach is motivated by demonstrating that a safe utilization bound can be significantly increased by taking period configuration data into account. The two well-known approaches of the period-independent Liu/Layland bound and the harmonic chain method restriction which enforces new periods to be integer multiples or parts of pre-set periods are discussed. It will turn out that our new approach can serve as a trade-off balancing the two goals of a weak period choice restriction and a high utilization bound. Subsequently, we justify and demonstrate it by several examples and derive some rules of thumb.","PeriodicalId":328716,"journal":{"name":"10th IEEE International Symposium on Industrial Embedded Systems (SIES)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130237076","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-06-08DOI: 10.1109/SIES.2015.7185067
Papa Issa Diallo, Seyed-Hosein Attarzadeh-Niaki, Francesco Robino, I. Sander, J. Champeau, Johnny Öberg
With the growing complexity of Real-Time Embedded Systems (RTES), there is a huge interest in using modeling languages such as the Unified Modeling Language (UML), and other Model-Driven Engineering (MDE) techniques targeting RTES system design. These approaches provide language abstractions for system design, allowing to focus on their relevant properties. Unfortunately, such approaches still suffer from several shortcomings including the lack of well-defined semantics. Therefore, it remains difficult to connect the MDE specification tools and the design tools that are based on formal grounds and well-defined semantics to perform analysis, validation or system synthesis for RTES. This paper presents a top-down RTES design flow aiming to reduce the gap between MDE and formal design approaches. We present the connection between a framework dedicated to the enrichment of modeling languages such as UML with formal semantics, a framework based on formal models of computation supporting validation by simulation, and a system synthesis tool targeting a flexible platform with well-defined execution services. Our purpose is to cover several system design phases from specification, simulation down to implementation on a platform. As a case study, a JPEG Encoder application was realized following the different design steps of the tool-chain.
{"title":"A formal, model-driven design flow for system simulation and multi-core implementation","authors":"Papa Issa Diallo, Seyed-Hosein Attarzadeh-Niaki, Francesco Robino, I. Sander, J. Champeau, Johnny Öberg","doi":"10.1109/SIES.2015.7185067","DOIUrl":"https://doi.org/10.1109/SIES.2015.7185067","url":null,"abstract":"With the growing complexity of Real-Time Embedded Systems (RTES), there is a huge interest in using modeling languages such as the Unified Modeling Language (UML), and other Model-Driven Engineering (MDE) techniques targeting RTES system design. These approaches provide language abstractions for system design, allowing to focus on their relevant properties. Unfortunately, such approaches still suffer from several shortcomings including the lack of well-defined semantics. Therefore, it remains difficult to connect the MDE specification tools and the design tools that are based on formal grounds and well-defined semantics to perform analysis, validation or system synthesis for RTES. This paper presents a top-down RTES design flow aiming to reduce the gap between MDE and formal design approaches. We present the connection between a framework dedicated to the enrichment of modeling languages such as UML with formal semantics, a framework based on formal models of computation supporting validation by simulation, and a system synthesis tool targeting a flexible platform with well-defined execution services. Our purpose is to cover several system design phases from specification, simulation down to implementation on a platform. As a case study, a JPEG Encoder application was realized following the different design steps of the tool-chain.","PeriodicalId":328716,"journal":{"name":"10th IEEE International Symposium on Industrial Embedded Systems (SIES)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127019402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：