Pub Date : 2019-10-01DOI: 10.23919/cycon.2018.8405002
Piotr Jasiński
This document specifies Metalink/HTTP: Mirrors and Cryptographic Hashes in HTTP header fields, a different way to get information that is usually contained in the Metalink XML-based download description format. Metalink/HTTP describes multiple download locations (mirrors), Peer-to-Peer, cryptographic hashes, digital signatures, and other information using existing standards for HTTP header fields. Metalink clients can use this information to make file transfers more robust and reliable. Normative requirements for Metalink/HTTP clients and servers are described here.
{"title":"Copyright notice","authors":"Piotr Jasiński","doi":"10.23919/cycon.2018.8405002","DOIUrl":"https://doi.org/10.23919/cycon.2018.8405002","url":null,"abstract":"This document specifies Metalink/HTTP: Mirrors and Cryptographic Hashes in HTTP header fields, a different way to get information that is usually contained in the Metalink XML-based download description format. Metalink/HTTP describes multiple download locations (mirrors), Peer-to-Peer, cryptographic hashes, digital signatures, and other information using existing standards for HTTP header fields. Metalink clients can use this information to make file transfers more robust and reliable. Normative requirements for Metalink/HTTP clients and servers are described here.","PeriodicalId":329807,"journal":{"name":"2017 21st European Microelectronics and Packaging Conference (EMPC) & Exhibition","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128611260","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-03DOI: 10.4071/ISOM-2017-WP52_085
Kotoku Inoue, Tsubasa Fujimura, M. Takayama, Shigeo Onitake
Glass is widely used as a material for various devices such as various reflection mirrors, photomasks, magnetic disks, ITO glass substrates and the like. Recently, the advantages of high quality glass substrate material for high performance, next-generation electronic devices have been widely reported. Especially, the glass substrate provides a low dielectric loss at higher signal frequencies, high heat resistance and almost the same dimension stability as that for Si chip[1]-[7]. Conventionally, dry method such as sputtering is the mainstream method for forming a metal film on a glass surface. This study reports our novel metallization technology to obtain good adhesion without degrading glass properties and Cu conductivity. Metal circuit patterns were created without roughening the surface of glass substrate by wet plating process with subtractive process. The TGV glass surface was cleaned by irradiation of ultra-violet (UV) light and alkaline degreasing with complex agent. UV light and alkaline degreasing make the surface of the glass clean and the copper adhesion to glass improves with minimal stress to the glass itself. Conventional catalyzing treatment was performed after the surface cleaning, and electroless copper was deposited, followed by copper electroplating as a seed layer for the entire surface of the glass including front, back, and TGV sidewalls. We have successfully demonstrated direct copper plating on TGV with conformal plating for the substrate with better performance, including copper-glass adhesion of 0.42kN/m. Conformal copper seed layer was observed by X-ray computed tomography. This technology is further optimized for glass interposer with the capability of thick copper metallization directly on TGV glass for the first time in 300mm × 400mm × 0.1mm (thick) panel, aiming to reduce cost and achieve high throughput TGV metallization (Table 1). It suggests to us that glass will be a very promising material for next generation high-speed network.
{"title":"Direct copper metallization on TGV (Thru-Glass-Via) for high performance glass substrate","authors":"Kotoku Inoue, Tsubasa Fujimura, M. Takayama, Shigeo Onitake","doi":"10.4071/ISOM-2017-WP52_085","DOIUrl":"https://doi.org/10.4071/ISOM-2017-WP52_085","url":null,"abstract":"Glass is widely used as a material for various devices such as various reflection mirrors, photomasks, magnetic disks, ITO glass substrates and the like. Recently, the advantages of high quality glass substrate material for high performance, next-generation electronic devices have been widely reported. Especially, the glass substrate provides a low dielectric loss at higher signal frequencies, high heat resistance and almost the same dimension stability as that for Si chip[1]-[7]. Conventionally, dry method such as sputtering is the mainstream method for forming a metal film on a glass surface. This study reports our novel metallization technology to obtain good adhesion without degrading glass properties and Cu conductivity. Metal circuit patterns were created without roughening the surface of glass substrate by wet plating process with subtractive process. The TGV glass surface was cleaned by irradiation of ultra-violet (UV) light and alkaline degreasing with complex agent. UV light and alkaline degreasing make the surface of the glass clean and the copper adhesion to glass improves with minimal stress to the glass itself. Conventional catalyzing treatment was performed after the surface cleaning, and electroless copper was deposited, followed by copper electroplating as a seed layer for the entire surface of the glass including front, back, and TGV sidewalls. We have successfully demonstrated direct copper plating on TGV with conformal plating for the substrate with better performance, including copper-glass adhesion of 0.42kN/m. Conformal copper seed layer was observed by X-ray computed tomography. This technology is further optimized for glass interposer with the capability of thick copper metallization directly on TGV glass for the first time in 300mm × 400mm × 0.1mm (thick) panel, aiming to reduce cost and achieve high throughput TGV metallization (Table 1). It suggests to us that glass will be a very promising material for next generation high-speed network.","PeriodicalId":329807,"journal":{"name":"2017 21st European Microelectronics and Packaging Conference (EMPC) & Exhibition","volume":"127 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121178120","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-03DOI: 10.4071/ISOM-2017-THA26_146
Emmanuelle Guéné
Flux consumption for wave soldering tends to decrease, mainly due to its gradual replacement by reflow soldering methods (i.e. pin-in-paste) in many electronics applications. However, in several cases, wave soldering still remains a must, with an increasing share of “selective” soldering processes, either using wave frames with dedicated apertures or solder fountains. Such processes are more challenging for the fluxes in terms of reliability under operation, since some chemistries remaining on the printed circuit boards after soldering may promote corrosion. Thus, flux manufacturers had to adapt their formulations to minimize such issues while keeping an efficient activation level, with several types of alloys (tin-lead, tin-silver-copper and low/no-silver) and associated with the numerous types of finishes encountered. The paper will cover the types of flux used in the electronic industry according to their chemistry and activation level (rosin-based, halides, alcohol-based or water-based flux…), and their characteristics with reference to standards. The limits of current standards will be discussed in regards to the last generation solder fluxes. Then, the development of two low-residue new generation fluxes, an alcohol-based flux and a true VOC-free flux, will be described, according to requirements: the lab tests results (surface tension, spread tests, wettability tests.) will be presented and discussed. Reliability will be especially investigated through surface insulation resistance, electro-chemical migration test, ionic contamination as well as Bono tests to determine the candidates able to provide high processability combined with chemical inertness of residues. Finally, the performance of flux will be assessed through customer tests, involving several types of boards, finishes and different solder alloys and wave equipment.
{"title":"Solderability and reliability evolution of no clean solder fluxes for selective soldering","authors":"Emmanuelle Guéné","doi":"10.4071/ISOM-2017-THA26_146","DOIUrl":"https://doi.org/10.4071/ISOM-2017-THA26_146","url":null,"abstract":"Flux consumption for wave soldering tends to decrease, mainly due to its gradual replacement by reflow soldering methods (i.e. pin-in-paste) in many electronics applications. However, in several cases, wave soldering still remains a must, with an increasing share of “selective” soldering processes, either using wave frames with dedicated apertures or solder fountains. Such processes are more challenging for the fluxes in terms of reliability under operation, since some chemistries remaining on the printed circuit boards after soldering may promote corrosion. Thus, flux manufacturers had to adapt their formulations to minimize such issues while keeping an efficient activation level, with several types of alloys (tin-lead, tin-silver-copper and low/no-silver) and associated with the numerous types of finishes encountered. The paper will cover the types of flux used in the electronic industry according to their chemistry and activation level (rosin-based, halides, alcohol-based or water-based flux…), and their characteristics with reference to standards. The limits of current standards will be discussed in regards to the last generation solder fluxes. Then, the development of two low-residue new generation fluxes, an alcohol-based flux and a true VOC-free flux, will be described, according to requirements: the lab tests results (surface tension, spread tests, wettability tests.) will be presented and discussed. Reliability will be especially investigated through surface insulation resistance, electro-chemical migration test, ionic contamination as well as Bono tests to determine the candidates able to provide high processability combined with chemical inertness of residues. Finally, the performance of flux will be assessed through customer tests, involving several types of boards, finishes and different solder alloys and wave equipment.","PeriodicalId":329807,"journal":{"name":"2017 21st European Microelectronics and Packaging Conference (EMPC) & Exhibition","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131042979","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-09-10DOI: 10.23919/EMPC.2017.8346867
M. Balmont, I. Bord-Majek, Y. Ousten
The printed circuit assembly market has been interested in embedded component technology for the last two decades in order to increase both integration density and performance of electronic boards. The objective of this technology is to integrate components, actives and passives, in internal layers of printed circuit boards (PCBs). In addition to the RF performances, the electromagnetic compatibility (EMC) characteristics are improved and the reliability increase. New opportunities in the miniaturization of devices emerge with embedded components technology in a wide range of business areas, as automotive or aeronautics sector. If the embedding of thin film passives in PCBs is now well known, few studies have been performed on active components. The manufacturing process results in stresses on embedded chips due to the assembling method, the temperature and material properties. In the present work, simulations based on Finite Element Method (FEM) have been performed to study the thermo-mechanical behavior of such embedded active components during its operating lifetime. In particular the strain energy density is estimated using a dedicated model for solder joint fatigue based on the Darveaux's methodology. The objective of the present study is to compare the estimated lifetime of solder joints of a surface mounted active component and the same embedded active according to the thermoplastic resin substrate used (for PCB). The influence in operating lifetime of main thermo-mechanical properties, as CTE (Coefficient of thermal expansion) and Young's Modulus, of the resin in embedded package allow to determinate the relevance of use very low CTE resin substrate.
{"title":"Comparative FEM thermo-mechanical simulations for built-in reliability: Surface mounted technology versus embedded technology for silicon dies","authors":"M. Balmont, I. Bord-Majek, Y. Ousten","doi":"10.23919/EMPC.2017.8346867","DOIUrl":"https://doi.org/10.23919/EMPC.2017.8346867","url":null,"abstract":"The printed circuit assembly market has been interested in embedded component technology for the last two decades in order to increase both integration density and performance of electronic boards. The objective of this technology is to integrate components, actives and passives, in internal layers of printed circuit boards (PCBs). In addition to the RF performances, the electromagnetic compatibility (EMC) characteristics are improved and the reliability increase. New opportunities in the miniaturization of devices emerge with embedded components technology in a wide range of business areas, as automotive or aeronautics sector. If the embedding of thin film passives in PCBs is now well known, few studies have been performed on active components. The manufacturing process results in stresses on embedded chips due to the assembling method, the temperature and material properties. In the present work, simulations based on Finite Element Method (FEM) have been performed to study the thermo-mechanical behavior of such embedded active components during its operating lifetime. In particular the strain energy density is estimated using a dedicated model for solder joint fatigue based on the Darveaux's methodology. The objective of the present study is to compare the estimated lifetime of solder joints of a surface mounted active component and the same embedded active according to the thermoplastic resin substrate used (for PCB). The influence in operating lifetime of main thermo-mechanical properties, as CTE (Coefficient of thermal expansion) and Young's Modulus, of the resin in embedded package allow to determinate the relevance of use very low CTE resin substrate.","PeriodicalId":329807,"journal":{"name":"2017 21st European Microelectronics and Packaging Conference (EMPC) & Exhibition","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131543089","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-09-10DOI: 10.23919/EMPC.2017.8346839
Camilla Kärnfelt, F. Gallée, V. Castel, Malika Tlili, Maina Sinou, Pascal Coant
Since 2009, Lab-STICC has established an LTCC prototyping laboratory where we, to this day, have worked on microwave devices, devices based on gaped waveguide technology for millimeter-wave/fluidic applications (60 GHz), grooved laminated waveguides (30 to 170 GHz), grid array antennas (145 GHz), spintronic devices as well as more basic subjects as design kit and design rule check development, passive component design, and most recently LTCC cooling implementation. This paper presents an overview of the aforementioned devices from simulation, fabrication and measurement phases as well as our fabrication possibilities and limitations.
{"title":"Experimental LTCC platform for millimeter-wave applications","authors":"Camilla Kärnfelt, F. Gallée, V. Castel, Malika Tlili, Maina Sinou, Pascal Coant","doi":"10.23919/EMPC.2017.8346839","DOIUrl":"https://doi.org/10.23919/EMPC.2017.8346839","url":null,"abstract":"Since 2009, Lab-STICC has established an LTCC prototyping laboratory where we, to this day, have worked on microwave devices, devices based on gaped waveguide technology for millimeter-wave/fluidic applications (60 GHz), grooved laminated waveguides (30 to 170 GHz), grid array antennas (145 GHz), spintronic devices as well as more basic subjects as design kit and design rule check development, passive component design, and most recently LTCC cooling implementation. This paper presents an overview of the aforementioned devices from simulation, fabrication and measurement phases as well as our fabrication possibilities and limitations.","PeriodicalId":329807,"journal":{"name":"2017 21st European Microelectronics and Packaging Conference (EMPC) & Exhibition","volume":"261 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122760738","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-09-01DOI: 10.23919/empc.2017.8346903
Keith Bryant, R. Vaga
Taking x-ray images goes back over 100 years. Since then, there have been numerous advances in x-ray technology and these have been increasingly applied in helping the manufacturing of electronic components and assemblies, as well as in their failure analysis. Most recently, this has been rapidly driven by the reduction in device and feature size and the movement to using newer, lower density materials within the structures, such as copper wire replacing gold wire as the interconnection material of choice within components. Another driver for developments is the engineering of single 3D packages with multiple chips stacked vertically one on top of the other, which results in smaller and more efficient packaging of devices. In order to meet these challenges and those in the future, there have been a number of recent key improvements to the vital components within x-ray systems. The choice of available technologies, however, means selecting the tube/detector combination, which is optimum for a particular electronics inspection application, is no longer so clear-cut. For example, one configuration may provide certain benefits that are applicable for one area of electronics inspection, whilst being less valid for others. This paper will review the various x-ray tube and detector types that are available and explain the implications of these choices for electronics inspection in terms of what they provide for inspection regarding image resolution, magnification, tube power, detector pixel size and the effects of detector radiation damage, amongst others. This paper will also look in detail at the capabilities of high end CT systems to inspect wafer bumps, copper pillars and TSV's, new designs are reducing key dimensions of all of these interconnections challenging x-ray systems to produce clear images.
{"title":"Advances in X-ray for semicon applications","authors":"Keith Bryant, R. Vaga","doi":"10.23919/empc.2017.8346903","DOIUrl":"https://doi.org/10.23919/empc.2017.8346903","url":null,"abstract":"Taking x-ray images goes back over 100 years. Since then, there have been numerous advances in x-ray technology and these have been increasingly applied in helping the manufacturing of electronic components and assemblies, as well as in their failure analysis. Most recently, this has been rapidly driven by the reduction in device and feature size and the movement to using newer, lower density materials within the structures, such as copper wire replacing gold wire as the interconnection material of choice within components. Another driver for developments is the engineering of single 3D packages with multiple chips stacked vertically one on top of the other, which results in smaller and more efficient packaging of devices. In order to meet these challenges and those in the future, there have been a number of recent key improvements to the vital components within x-ray systems. The choice of available technologies, however, means selecting the tube/detector combination, which is optimum for a particular electronics inspection application, is no longer so clear-cut. For example, one configuration may provide certain benefits that are applicable for one area of electronics inspection, whilst being less valid for others. This paper will review the various x-ray tube and detector types that are available and explain the implications of these choices for electronics inspection in terms of what they provide for inspection regarding image resolution, magnification, tube power, detector pixel size and the effects of detector radiation damage, amongst others. This paper will also look in detail at the capabilities of high end CT systems to inspect wafer bumps, copper pillars and TSV's, new designs are reducing key dimensions of all of these interconnections challenging x-ray systems to produce clear images.","PeriodicalId":329807,"journal":{"name":"2017 21st European Microelectronics and Packaging Conference (EMPC) & Exhibition","volume":"132 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116649427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-09-01DOI: 10.23919/EMPC.2017.8346855
M. Fischer, M. Stubenrauch, A. Naber, N. Gutzeit, M. Klett, S. Singh, A. Schober, H. Witte, J. Müller
A miniaturized ceramic atmospheric plasma source for the utilization in life sciences has been developed. It is manufactured in LTCC-technology (low temperature cofired ceramic). The plasma generation is based on buried electrodes which lead to a Dielectric Barrier Discharge (DBD). The employed technology allows small feature sizes (electrode width 150 μm, barrier thickness 40μm etc.) as well as precision in the μm range, resulting in a very low power consumption of the system (approx. 5 W). Thus, the maximum temperature at the point of use can be kept below 40 °C. The flexibility of the manufacturing process (layer lamination, screen printing, patterning with picosecond laser etc.) offers additional features like robust fluidic structures (channels, chambers, gas distribution etc.) as well as the direct implementation of electronic components. The technology concept as well as the design of the ceramic parts and the handhold matched to the multi-well plate format is demonstrated. The plasma of the system can be tuned depending on the assembly of the system and the electric excitation. To prove the biocompatibility and the experimental compatibility with cell cultures (low temperature at the point of use), a method for temperature measurements on the bottom of a multi-well plate was developed. First results of the impact of the plasma source on cell cultures are presented. The effects occurring in the plasma, as well as their effects on the cell cultures (ozone formation, ultraviolet radiation etc.) are separately considered. Furthermore, the cell tolerability of the treatment with the micro-plasma source is investigated with L929 fibroblast cells.
{"title":"LTCC-based micro plasma source for the selective treatment of cell cultures","authors":"M. Fischer, M. Stubenrauch, A. Naber, N. Gutzeit, M. Klett, S. Singh, A. Schober, H. Witte, J. Müller","doi":"10.23919/EMPC.2017.8346855","DOIUrl":"https://doi.org/10.23919/EMPC.2017.8346855","url":null,"abstract":"A miniaturized ceramic atmospheric plasma source for the utilization in life sciences has been developed. It is manufactured in LTCC-technology (low temperature cofired ceramic). The plasma generation is based on buried electrodes which lead to a Dielectric Barrier Discharge (DBD). The employed technology allows small feature sizes (electrode width 150 μm, barrier thickness 40μm etc.) as well as precision in the μm range, resulting in a very low power consumption of the system (approx. 5 W). Thus, the maximum temperature at the point of use can be kept below 40 °C. The flexibility of the manufacturing process (layer lamination, screen printing, patterning with picosecond laser etc.) offers additional features like robust fluidic structures (channels, chambers, gas distribution etc.) as well as the direct implementation of electronic components. The technology concept as well as the design of the ceramic parts and the handhold matched to the multi-well plate format is demonstrated. The plasma of the system can be tuned depending on the assembly of the system and the electric excitation. To prove the biocompatibility and the experimental compatibility with cell cultures (low temperature at the point of use), a method for temperature measurements on the bottom of a multi-well plate was developed. First results of the impact of the plasma source on cell cultures are presented. The effects occurring in the plasma, as well as their effects on the cell cultures (ozone formation, ultraviolet radiation etc.) are separately considered. Furthermore, the cell tolerability of the treatment with the micro-plasma source is investigated with L929 fibroblast cells.","PeriodicalId":329807,"journal":{"name":"2017 21st European Microelectronics and Packaging Conference (EMPC) & Exhibition","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116769631","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-09-01DOI: 10.23919/EMPC.2017.8346927
Laura Jasińska, Jan Macioszczyk, K. Malecha, P. Słobodzian
Systems, which operate in microwave range and are made on LTCC (Low Temperature Co-fired Ceramic) substrates have been known for several decades. However, when it comes to the process of developing microwave circuits, one of the most significant factors is the knowledge of the electrical parameters of the substrate. Usually, different manufacturers provide LTCC materials with different electrical parameters. Even if those materials have precise specification their final electrical parameters can change during further processing. In this article, electrical characterization of various LTCC substrates using SPDR (Split Post Dielectric Resonator) method for a given lamination process is presented. The following LTCC materials were put into characterization: CeramTape GC, ESL41020 and KEKO SK47.
{"title":"Dielectric characterization of selected LTCC materials for microwave applications","authors":"Laura Jasińska, Jan Macioszczyk, K. Malecha, P. Słobodzian","doi":"10.23919/EMPC.2017.8346927","DOIUrl":"https://doi.org/10.23919/EMPC.2017.8346927","url":null,"abstract":"Systems, which operate in microwave range and are made on LTCC (Low Temperature Co-fired Ceramic) substrates have been known for several decades. However, when it comes to the process of developing microwave circuits, one of the most significant factors is the knowledge of the electrical parameters of the substrate. Usually, different manufacturers provide LTCC materials with different electrical parameters. Even if those materials have precise specification their final electrical parameters can change during further processing. In this article, electrical characterization of various LTCC substrates using SPDR (Split Post Dielectric Resonator) method for a given lamination process is presented. The following LTCC materials were put into characterization: CeramTape GC, ESL41020 and KEKO SK47.","PeriodicalId":329807,"journal":{"name":"2017 21st European Microelectronics and Packaging Conference (EMPC) & Exhibition","volume":"58 7","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120934225","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-09-01DOI: 10.23919/EMPC.2017.8346862
I. Panchenko, M. Boettcher, J. Wolf, M. Kunz, L. Lehmann, Tanya A. Atanasova, M. Wieland
The vertical assembly between chip and interposer (2.5D) is mainly done by micro interconnects based on Cu pillars (diameter <50 μm, height <75 μm). These are typically manufactured via electroplating, which includes the sequential deposition of the Cu pillar itself and its solder cap (typically SnAg or Sn). In order to improve the yield of the subsequent assembly process as well as the overall reliability of these interconnects it is crucial to obtain information about their post process characteristics such as geometry (e.g. height and diameter, as well variations over the whole Si wafer), roughness, undercut, contamination level etc. Therefore it is important to introduce reliable metrology tools for wafer processing control. This study provides a detailed overview on important pillar characteristics and possible metrology solutions for their measurement, ranging from destructive failure analysis to promising in-line techniques. Furthermore, challenges and limits of the found solutions for various important pillar characteristics will be discussed. Derived from the provided overview on Cu pillar characteristics, this study will focus in detail on the measurement of the pillar sidewall loss and its roughness, the pillar undercut, the roughness of the insulator layer surrounding the pillar and the bottom critical dimension (CD). The sidewall parameters and the undercut of the pillar are difficult to characterize because of the geometrical arrangement and the associated inaccessibility by common measurement techniques (e.g. optical widefleld microscopy). The application of confocal microscopy with high resolution will be described in detail which enabled successful measurements of most of the described parameters (except undercut). The results will be discussed in terms of applicability for even smaller pillars (down to 25 μm) and in-line metrology capabilities.
{"title":"In-line metrology for Cu pillar applications in interposer based packages for 2.5D integration","authors":"I. Panchenko, M. Boettcher, J. Wolf, M. Kunz, L. Lehmann, Tanya A. Atanasova, M. Wieland","doi":"10.23919/EMPC.2017.8346862","DOIUrl":"https://doi.org/10.23919/EMPC.2017.8346862","url":null,"abstract":"The vertical assembly between chip and interposer (2.5D) is mainly done by micro interconnects based on Cu pillars (diameter <50 μm, height <75 μm). These are typically manufactured via electroplating, which includes the sequential deposition of the Cu pillar itself and its solder cap (typically SnAg or Sn). In order to improve the yield of the subsequent assembly process as well as the overall reliability of these interconnects it is crucial to obtain information about their post process characteristics such as geometry (e.g. height and diameter, as well variations over the whole Si wafer), roughness, undercut, contamination level etc. Therefore it is important to introduce reliable metrology tools for wafer processing control. This study provides a detailed overview on important pillar characteristics and possible metrology solutions for their measurement, ranging from destructive failure analysis to promising in-line techniques. Furthermore, challenges and limits of the found solutions for various important pillar characteristics will be discussed. Derived from the provided overview on Cu pillar characteristics, this study will focus in detail on the measurement of the pillar sidewall loss and its roughness, the pillar undercut, the roughness of the insulator layer surrounding the pillar and the bottom critical dimension (CD). The sidewall parameters and the undercut of the pillar are difficult to characterize because of the geometrical arrangement and the associated inaccessibility by common measurement techniques (e.g. optical widefleld microscopy). The application of confocal microscopy with high resolution will be described in detail which enabled successful measurements of most of the described parameters (except undercut). The results will be discussed in terms of applicability for even smaller pillars (down to 25 μm) and in-line metrology capabilities.","PeriodicalId":329807,"journal":{"name":"2017 21st European Microelectronics and Packaging Conference (EMPC) & Exhibition","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127086078","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-09-01DOI: 10.23919/EMPC.2017.8346841
H. Bartsch, Dirk Stöpel, Jens Müller, A. Rydosz
Gas sensor technology requires a heating element, which has a good thermal coupling to the active layer, providing thus a high local temperature increase without affecting the surrounding package. The use of Low Temperature Cofired Ceramics (LTCC) based packages allows the assembly of buried heaters in the near vicinity of the sensing layer. The heater must meet various requirements. Its resistance value should be in a reasonable range in order to allow the use of common power supply and the tolerances should be narrow to guarantee a stable working point without the need of additional control circuits. LTCC technology provides two ways for manufacturing of heaters: screen printing of thick film resistors or conducting lines formed as meander. For the first approach, a variety of pastes is available, but thick film resistors entail tolerances of 20% or more due to printing result and firing. Conducting lines are more stable with regard to tolerances, but their low sheet resistance results in low heater resistance if the area is limited. The use of resinate pastes as a potential solution of this problem is investigated in this work. These pastes have high organic portion and the resulting layers achieve a thickness in the range of few hundred nanometers after firing. As consequence, the sheet resistance of the conductor paths is increased and reasonable heater resistance values are achievable at small areas. The used of this pastes as an alternative approach for heater integration in LTCC packages will be discussed.
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