Complementary Metal Oxide Semiconductor (CMOS) is a technology used to produce integrated circuit. CMOS circuits are found in several types of electronic components, including microprocessors, batteries and digital camera image sensors. The MOS in CMOS refers to the transistor in a CMOS component called MOSFETs (metal oxide semiconductor field-effect transistors). In the project we are going to design novel CCCCTA, developed in CMOS technology using Advanced Design System (ADS). Current conveyors are unity gain active building block having high linearity, wide dynamic range and provide higher gain-bandwidth product. The current conveyors operate at low voltage supplies and consume less power. It has high input impedance, low output impedance, high CMRR and high slew rate. The current mode circuits such as Current conveyors have emerged as an important class of circuits in the field of analog electronics. The new structured CCCCTA the balanced differential-pair structure is used instead of the trans-linear structure as in the original CCCCTA and our proposed block are the requirements of bias current which is used to control the parasitic resistance at the input current port and the number of MOSFETs.
{"title":"CURRENT CONTROLLED TRANSCONDUCTANCE AMPLIFIER (CCTA) USING ADVANCED DESIGN SYSTEM","authors":"M. A. Deshmukh, U. Kshirsagar","doi":"10.21917/ijme.2020.0145","DOIUrl":"https://doi.org/10.21917/ijme.2020.0145","url":null,"abstract":"Complementary Metal Oxide Semiconductor (CMOS) is a technology used to produce integrated circuit. CMOS circuits are found in several types of electronic components, including microprocessors, batteries and digital camera image sensors. The MOS in CMOS refers to the transistor in a CMOS component called MOSFETs (metal oxide semiconductor field-effect transistors). In the project we are going to design novel CCCCTA, developed in CMOS technology using Advanced Design System (ADS). Current conveyors are unity gain active building block having high linearity, wide dynamic range and provide higher gain-bandwidth product. The current conveyors operate at low voltage supplies and consume less power. It has high input impedance, low output impedance, high CMRR and high slew rate. The current mode circuits such as Current conveyors have emerged as an important class of circuits in the field of analog electronics. The new structured CCCCTA the balanced differential-pair structure is used instead of the trans-linear structure as in the original CCCCTA and our proposed block are the requirements of bias current which is used to control the parasitic resistance at the input current port and the number of MOSFETs.","PeriodicalId":33160,"journal":{"name":"ICTACT Journal on Microelectronics","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2020-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"48341157","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. S. Geege, P. Vimala, T. S. Arun Samuel, N. Arumugam
This paper deals with a novel Double Gate MOSFET (DG MOSFET) which is constructed by the unification of III group materials (Indium, Gallium) and V group materials (Phosphide, Arsenide) is analyzed. Due to its short channel effect immunization, leakage current reduction and higher scaling potential, DG MOSFET as one of the most comforting devices for low power applications. In this work, we investigated the effect of DG MOSFET based on Indium Phosphide (InP) and Gallium Arsenide (GaAs) on optimal performance and drain current characteristics by replacing traditional DG MOSFET based on silicon. The transistor’s channel length is set to 20 nm. Both devices have been modeled using the NanoHub simulator and characteristics has been examined using Matlab. The descriptive analysis of characteristics has been performed through the corresponding plot structures - energy band structure, I D vs V GS characteristics, I D vs V GS characteristics, transconductance. From the results provided, it has been found that the DG MOSFET device based on InP offers ON current 10 -3 A is better than the DG MOSFET device based on Silicon and Gallium Arsenide (GaAs).
本文分析了由III族材料(铟、镓)和V族材料(磷化物、砷化物)统一构成的新型双栅MOSFET (DG MOSFET)。由于其短通道效应免疫、泄漏电流减小和较高的标度电位，DG MOSFET成为低功耗应用中最舒适的器件之一。在这项工作中，我们研究了基于磷化铟(InP)和砷化镓(GaAs)的DG MOSFET取代传统的基于硅的DG MOSFET，对优化性能和漏极电流特性的影响。晶体管的通道长度设置为20nm。使用NanoHub模拟器对这两种设备进行了建模，并使用Matlab对其特性进行了检查。通过相应的图结构-能带结构、I - D vs . V - GS特性、I - D vs . V - GS特性、跨导进行了特征的描述性分析。从所提供的结果来看，基于InP的DG MOSFET器件提供的on电流为10 - 3a，优于基于硅和砷化镓(GaAs)的DG MOSFET器件。
{"title":"DESIGN AND ANALYSIS OF InP AND GaAs DOUBLE GATE MOSFET TRANSISTORS FOR LOW POWER APPLICATIONS","authors":"A. S. Geege, P. Vimala, T. S. Arun Samuel, N. Arumugam","doi":"10.21917/ijme.2020.0151","DOIUrl":"https://doi.org/10.21917/ijme.2020.0151","url":null,"abstract":"This paper deals with a novel Double Gate MOSFET (DG MOSFET) which is constructed by the unification of III group materials (Indium, Gallium) and V group materials (Phosphide, Arsenide) is analyzed. Due to its short channel effect immunization, leakage current reduction and higher scaling potential, DG MOSFET as one of the most comforting devices for low power applications. In this work, we investigated the effect of DG MOSFET based on Indium Phosphide (InP) and Gallium Arsenide (GaAs) on optimal performance and drain current characteristics by replacing traditional DG MOSFET based on silicon. The transistor’s channel length is set to 20 nm. Both devices have been modeled using the NanoHub simulator and characteristics has been examined using Matlab. The descriptive analysis of characteristics has been performed through the corresponding plot structures - energy band structure, I D vs V GS characteristics, I D vs V GS characteristics, transconductance. From the results provided, it has been found that the DG MOSFET device based on InP offers ON current 10 -3 A is better than the DG MOSFET device based on Silicon and Gallium Arsenide (GaAs).","PeriodicalId":33160,"journal":{"name":"ICTACT Journal on Microelectronics","volume":"1 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2020-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"44238633","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this topic we are going to design a compact size antenna which is used for different band using a single antenna. The term compact means the size of antenna is very less, which is 24×30mm2. In this antenna designing we are using partial ground plane and is fabricated on Roger RTduroid 5880 with thickness of 0.79mm. In this antenna we have three inverted L shaped stub and a stub of combination of inverted L shape and T shape. This antenna resonates at three frequencies 2.54/3.51/4.38/5.3GHz. So the operating range of antenna covers these frequencies so main use of this antenna is in Wi-MAX (wide interoperability for microwave access) and WLAN (wireless local area network) and radio altimeter, satellite communication, cordless telephones and weather radar systems. All the parameters and details are examined in following points.
{"title":"DESIGN AND ANALYSIS OF QUAD BAND ANTENNA FOR WIRELESS SYSTEMS","authors":"Kuldeep Galav, M. Meena","doi":"10.21917/ijme.2020.0149","DOIUrl":"https://doi.org/10.21917/ijme.2020.0149","url":null,"abstract":"In this topic we are going to design a compact size antenna which is used for different band using a single antenna. The term compact means the size of antenna is very less, which is 24×30mm2. In this antenna designing we are using partial ground plane and is fabricated on Roger RTduroid 5880 with thickness of 0.79mm. In this antenna we have three inverted L shaped stub and a stub of combination of inverted L shape and T shape. This antenna resonates at three frequencies 2.54/3.51/4.38/5.3GHz. So the operating range of antenna covers these frequencies so main use of this antenna is in Wi-MAX (wide interoperability for microwave access) and WLAN (wireless local area network) and radio altimeter, satellite communication, cordless telephones and weather radar systems. All the parameters and details are examined in following points.","PeriodicalId":33160,"journal":{"name":"ICTACT Journal on Microelectronics","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2020-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"46767874","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Planar transmission line on silicon substrate imposes certain challenges at higher frequencies and measurement of the same employing wafer probing techniques needs accurate characterization. Wafer measurement provides information related with the device performance which in turn helps to minimize parasitic related with package and assembly. Wafer probing at higher frequencies imposes certain challenges more so ever on silicon substrate. Silicon substrate due to semiconductor in nature is a lossy medium for radio frequencies and standard wafer is not suitable for the realization of RF circuits. Present article demonstrate realization of planar transmission line on high resistivity silicon substrate by employing thick oxide layer. Both simulated and measured results are presented in this article and the CPW line fabricated with the proposed process results in ~1dB loss with better than 12dB return loss at Ka-band. Measurement techniques for the line characterization are detailed in this article along with transmission line characterization at Ka-band.
{"title":"PROCESS FOR IMPLEMENTATION OF TRANSMISSION LINE ON STANDARD SILICON SUBSTRATE AND ITS CHARACTERIZATION AT KA-BAND","authors":"K. Singh, A. V. Nirmal","doi":"10.21917/ijme.2020.0150","DOIUrl":"https://doi.org/10.21917/ijme.2020.0150","url":null,"abstract":"Planar transmission line on silicon substrate imposes certain challenges at higher frequencies and measurement of the same employing wafer probing techniques needs accurate characterization. Wafer measurement provides information related with the device performance which in turn helps to minimize parasitic related with package and assembly. Wafer probing at higher frequencies imposes certain challenges more so ever on silicon substrate. Silicon substrate due to semiconductor in nature is a lossy medium for radio frequencies and standard wafer is not suitable for the realization of RF circuits. Present article demonstrate realization of planar transmission line on high resistivity silicon substrate by employing thick oxide layer. Both simulated and measured results are presented in this article and the CPW line fabricated with the proposed process results in ~1dB loss with better than 12dB return loss at Ka-band. Measurement techniques for the line characterization are detailed in this article along with transmission line characterization at Ka-band.","PeriodicalId":33160,"journal":{"name":"ICTACT Journal on Microelectronics","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2020-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"48674756","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The color sorting machines inspect grains by means of sensors and remove contaminants by a short burst of compressed air by using the color difference. Grain Sorting machines are successfully being used in the rice milling industry for long time. The color sorters are used in the grain cleaning to remove unwanted materials like dust particles, black tip, burnt, other discolored grains and other inner contaminants. Today’s advanced color sensors are robust, compact, requires less maintenance and consumes very little energy. Hence, these color sensors can be considered for inclusion in any modern grain cleaning plant. This paper aims to develop Calib_IO, Wave Generation and Clock Generation modules for grain sorting machine to remove unwanted materials like dust particles, black tip, burnt, other discolored grains and other inner contaminants and to increase its processing speed. Clock generation module is designed using Quartus II software and is implemented in Cyclone IV E (FPGA KIT) that incorporates compact color sensors for sorting grains.
彩色分选机通过传感器检测谷物，并利用色差通过短时间的压缩空气去除污染物。谷物分选机在碾米工业中成功应用已久。彩色分选机用于谷物清洁，以去除不需要的材料，如灰尘颗粒、黑色尖端、烧焦的、其他变色的谷物和其他内部污染物。当今先进的颜色传感器坚固、紧凑，需要更少的维护，并且消耗很少的能量。因此，可以考虑将这些颜色传感器包括在任何现代谷物清洁工厂中。本文旨在开发用于谷物分拣机的Calib_IO、波浪产生和时钟产生模块，以去除不需要的材料，如灰尘颗粒、黑尖、烧焦、其他变色的谷物和其他内部污染物，并提高其处理速度。时钟生成模块使用Quartus II软件设计，并在Cyclone IV E（FPGA KIT）中实现，该模块集成了用于分拣谷物的紧凑型颜色传感器。
{"title":"FPGA IMPLEMENTATION OF CALIB_IO, WAVE AND CLOCK GENERATION MODULES FOR GRAIN SORTING MACHINE","authors":"S. Sujitha, N. Augustia","doi":"10.21917/ijme.2020.0147","DOIUrl":"https://doi.org/10.21917/ijme.2020.0147","url":null,"abstract":"The color sorting machines inspect grains by means of sensors and remove contaminants by a short burst of compressed air by using the color difference. Grain Sorting machines are successfully being used in the rice milling industry for long time. The color sorters are used in the grain cleaning to remove unwanted materials like dust particles, black tip, burnt, other discolored grains and other inner contaminants. Today’s advanced color sensors are robust, compact, requires less maintenance and consumes very little energy. Hence, these color sensors can be considered for inclusion in any modern grain cleaning plant. This paper aims to develop Calib_IO, Wave Generation and Clock Generation modules for grain sorting machine to remove unwanted materials like dust particles, black tip, burnt, other discolored grains and other inner contaminants and to increase its processing speed. Clock generation module is designed using Quartus II software and is implemented in Cyclone IV E (FPGA KIT) that incorporates compact color sensors for sorting grains.","PeriodicalId":33160,"journal":{"name":"ICTACT Journal on Microelectronics","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2020-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"45945387","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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