Pub Date : 2018-03-21DOI: 10.1109/PDP2018.2018.00101
Lloyd Robert Still, L. Indrusiak
The problem of mapping hard real-time tasks onto networks-on-chip has previously been successfully addressed by genetic algorithms. However, none of the existing problem formulations consider memory constraints. State-of-the-art genetic mappers are therefore able to find fully-schedulable mappings which are incompatible with the memory limitations of realistic platforms. In this paper, we extend the problem formulation and devise a memory architecture, in the form of private local memories. We then propose three memory models of increasing complexity and realism, and evaluate the impact these additional constraints pose to the genetic search. We conduct extensive experiments using tasks and communications from a realistic benchmark application, and compare the proposed approach against a state-of-the-art baseline mapper.
{"title":"Memory-Aware Genetic Algorithms for Task Mapping on Hard Real-Time Networks-on-Chip","authors":"Lloyd Robert Still, L. Indrusiak","doi":"10.1109/PDP2018.2018.00101","DOIUrl":"https://doi.org/10.1109/PDP2018.2018.00101","url":null,"abstract":"The problem of mapping hard real-time tasks onto networks-on-chip has previously been successfully addressed by genetic algorithms. However, none of the existing problem formulations consider memory constraints. State-of-the-art genetic mappers are therefore able to find fully-schedulable mappings which are incompatible with the memory limitations of realistic platforms. In this paper, we extend the problem formulation and devise a memory architecture, in the form of private local memories. We then propose three memory models of increasing complexity and realism, and evaluate the impact these additional constraints pose to the genetic search. We conduct extensive experiments using tasks and communications from a realistic benchmark application, and compare the proposed approach against a state-of-the-art baseline mapper.","PeriodicalId":333367,"journal":{"name":"2018 26th Euromicro International Conference on Parallel, Distributed and Network-based Processing (PDP)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131462324","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-21DOI: 10.1109/PDP2018.2018.00069
E. Taylor, D. W. Chang
Today Graphics Processing Units (GPUs) are being used for more than traditional graphics processing. Large super computers such as Titan are utilizing GPUs to solve problems that have little resemblance to their original purpose. To improve the performance of these applications, GPU architects are increasing cache sizes to lower latencies of non-uniform memory references found in these programs. In this paper, we investigate an alternative approach where a victim buffer is added to the first level cache. Our studies show that a 256-line victim cache can increase L1 hit rate by 15% and improve IPC by 7.5% over the baseline. This victim cache outperforms increasing the cache size by 400% while being a less costly solution in terms of area.
{"title":"Studying Victim Caches in GPUs","authors":"E. Taylor, D. W. Chang","doi":"10.1109/PDP2018.2018.00069","DOIUrl":"https://doi.org/10.1109/PDP2018.2018.00069","url":null,"abstract":"Today Graphics Processing Units (GPUs) are being used for more than traditional graphics processing. Large super computers such as Titan are utilizing GPUs to solve problems that have little resemblance to their original purpose. To improve the performance of these applications, GPU architects are increasing cache sizes to lower latencies of non-uniform memory references found in these programs. In this paper, we investigate an alternative approach where a victim buffer is added to the first level cache. Our studies show that a 256-line victim cache can increase L1 hit rate by 15% and improve IPC by 7.5% over the baseline. This victim cache outperforms increasing the cache size by 400% while being a less costly solution in terms of area.","PeriodicalId":333367,"journal":{"name":"2018 26th Euromicro International Conference on Parallel, Distributed and Network-based Processing (PDP)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133375596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-21DOI: 10.1109/PDP2018.2018.00065
Pedro Valero-Lara, I. Martínez-Pérez, Sergi Mateo, R. Sirvent, Vicencc Beltran, X. Martorell, Jesús Labarta
Many scientific applications are in need to solve a high number of small-size independent problems. These individual problems do not provide enough parallelism and then, these must be computed as a batch. Today, vendors such as Intel and NVIDIA are developing their own suite of batch routines. Although most of the works focus on computing batches of fixed size, in real applications we can not assume a uniform size for all set of problems. We explore and analyze different strategies based on parallel for, task and taskloop OpenMP pragmas. Although these strategies are straightforward from a programmer's point of view, they have a different impact on performance. We also analyze a new prototype provided by Intel (MKL), which deals with batch operations (cblas dgemm batch). We propose a new approach called grouping. It basically groups a set of problems until filling a limit in terms of memory occupancy or number of operations. In this way, groups composed by different number of problems are distributed on cores, achieving a more balanced distribution in terms of computational cost. This strategy is able to be up to 6× faster than the Intel (MKL) batch routine.
{"title":"Variable Batched DGEMM","authors":"Pedro Valero-Lara, I. Martínez-Pérez, Sergi Mateo, R. Sirvent, Vicencc Beltran, X. Martorell, Jesús Labarta","doi":"10.1109/PDP2018.2018.00065","DOIUrl":"https://doi.org/10.1109/PDP2018.2018.00065","url":null,"abstract":"Many scientific applications are in need to solve a high number of small-size independent problems. These individual problems do not provide enough parallelism and then, these must be computed as a batch. Today, vendors such as Intel and NVIDIA are developing their own suite of batch routines. Although most of the works focus on computing batches of fixed size, in real applications we can not assume a uniform size for all set of problems. We explore and analyze different strategies based on parallel for, task and taskloop OpenMP pragmas. Although these strategies are straightforward from a programmer's point of view, they have a different impact on performance. We also analyze a new prototype provided by Intel (MKL), which deals with batch operations (cblas dgemm batch). We propose a new approach called grouping. It basically groups a set of problems until filling a limit in terms of memory occupancy or number of operations. In this way, groups composed by different number of problems are distributed on cores, achieving a more balanced distribution in terms of computational cost. This strategy is able to be up to 6× faster than the Intel (MKL) batch routine.","PeriodicalId":333367,"journal":{"name":"2018 26th Euromicro International Conference on Parallel, Distributed and Network-based Processing (PDP)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115406654","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-21DOI: 10.1109/PDP2018.2018.00055
Chao Liu, M. Leeser
With the prevalence of multicore and manycore processors, developing parallel applications to bene?t from massively parallel resources is important. In this work, we introduce a hybrid shared memory mechanism based on a high-level task design. We implemented task scoped global shared data based on the one-sided communication feature of MPI-3 and enable users to implement and create multi-threaded tasks that can execute either on a single node or on multiple nodes. Task threads of distributed nodes can share data sets through global shared data objects using one-sided remote memory access. We ported and developed a set of benchmark applications and tested on a cluster platform. The high-level task design and hybrid shared memory help users develop and maintain parallel programs easily, and the results show that the global shared data can deliver good RMA performance; the multi-threaded task implementations perform up to 20% faster than ordinary OpenMP programs and have better scaling performance than MPI programs on multiple nodes.
{"title":"Local and Global Shared Memory for Task Based HPC Applications on Heterogeneous Platforms","authors":"Chao Liu, M. Leeser","doi":"10.1109/PDP2018.2018.00055","DOIUrl":"https://doi.org/10.1109/PDP2018.2018.00055","url":null,"abstract":"With the prevalence of multicore and manycore processors, developing parallel applications to bene?t from massively parallel resources is important. In this work, we introduce a hybrid shared memory mechanism based on a high-level task design. We implemented task scoped global shared data based on the one-sided communication feature of MPI-3 and enable users to implement and create multi-threaded tasks that can execute either on a single node or on multiple nodes. Task threads of distributed nodes can share data sets through global shared data objects using one-sided remote memory access. We ported and developed a set of benchmark applications and tested on a cluster platform. The high-level task design and hybrid shared memory help users develop and maintain parallel programs easily, and the results show that the global shared data can deliver good RMA performance; the multi-threaded task implementations perform up to 20% faster than ordinary OpenMP programs and have better scaling performance than MPI programs on multiple nodes.","PeriodicalId":333367,"journal":{"name":"2018 26th Euromicro International Conference on Parallel, Distributed and Network-based Processing (PDP)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124097984","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-21DOI: 10.1109/PDP2018.2018.00029
Moussa Beji, Sami Achour
With the birth of multi-cluster platforms, scheduling and finding the optimal number of resources (clusters, processors) to execute an application constitute very critical problems. In this paper, we address the need for scheduling techniques for parallel task applications on this kind of platforms and we propose a new strategy for scheduling sequential task graphs based on existing heuristics that have proved to be efficient on homogeneous environments. The contribution of this paper lies in determining the appropriate clusters which participate to compute a given application. Our solution is composed of three steps: Firstly, determining of the computing clusters, secondly, determining the optimal number of processors in each cluster, finally place the tasks on the appropriate processors. Simulation results, based on both randomly generated graphs and real configuration platforms, show that the proposed approach provides interesting trade-off between makespan and resource consumption.
{"title":"Resizing of Heterogeneous Platforms and the Optimization of Parallel Applications","authors":"Moussa Beji, Sami Achour","doi":"10.1109/PDP2018.2018.00029","DOIUrl":"https://doi.org/10.1109/PDP2018.2018.00029","url":null,"abstract":"With the birth of multi-cluster platforms, scheduling and finding the optimal number of resources (clusters, processors) to execute an application constitute very critical problems. In this paper, we address the need for scheduling techniques for parallel task applications on this kind of platforms and we propose a new strategy for scheduling sequential task graphs based on existing heuristics that have proved to be efficient on homogeneous environments. The contribution of this paper lies in determining the appropriate clusters which participate to compute a given application. Our solution is composed of three steps: Firstly, determining of the computing clusters, secondly, determining the optimal number of processors in each cluster, finally place the tasks on the appropriate processors. Simulation results, based on both randomly generated graphs and real configuration platforms, show that the proposed approach provides interesting trade-off between makespan and resource consumption.","PeriodicalId":333367,"journal":{"name":"2018 26th Euromicro International Conference on Parallel, Distributed and Network-based Processing (PDP)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124182842","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-21DOI: 10.1109/PDP2018.2018.00044
I. Zoppis, R. Dondi, Davide Coppetti, Alessandro Beltramo, G. Mauri
Social interaction allows to support the disease management by creating online spaces where patients can interact with clinicians, and share experiences with other patients. Therefore, promoting targeted communication in online social spaces is a means to group patients around shared goals, offer emotional support, and finally engage patients in their healthcare decision making process. In this paper, we approach the argument from a theoretical perspective: we design an optimization problem aimed to encourage the creation of (induced) sub-networks of patients which, being recently diagnosed, wish to deepen the knowledge about their medical treatment with some other similar profiled patients, which have already been followed up by specific (even alternative) care centers. In particular, due to the computational hardness of the proposed problem, we provide approximated solutions based on distributed heuristics (i.e., Genetic Algorithms). Results are given for simulated data using Erdos-Renyi random graphs.
{"title":"Distributed Heuristics for Optimizing Cohesive Groups: A Support for Clinical Patient Engagement in Social Network Analysis","authors":"I. Zoppis, R. Dondi, Davide Coppetti, Alessandro Beltramo, G. Mauri","doi":"10.1109/PDP2018.2018.00044","DOIUrl":"https://doi.org/10.1109/PDP2018.2018.00044","url":null,"abstract":"Social interaction allows to support the disease management by creating online spaces where patients can interact with clinicians, and share experiences with other patients. Therefore, promoting targeted communication in online social spaces is a means to group patients around shared goals, offer emotional support, and finally engage patients in their healthcare decision making process. In this paper, we approach the argument from a theoretical perspective: we design an optimization problem aimed to encourage the creation of (induced) sub-networks of patients which, being recently diagnosed, wish to deepen the knowledge about their medical treatment with some other similar profiled patients, which have already been followed up by specific (even alternative) care centers. In particular, due to the computational hardness of the proposed problem, we provide approximated solutions based on distributed heuristics (i.e., Genetic Algorithms). Results are given for simulated data using Erdos-Renyi random graphs.","PeriodicalId":333367,"journal":{"name":"2018 26th Euromicro International Conference on Parallel, Distributed and Network-based Processing (PDP)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121138116","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-21DOI: 10.1109/PDP2018.2018.00085
T. Rauber, G. Rünger
Runge-Kutta methods are widely used and popular solutions method for scientific simulations based on differential equations and, thus, their efficient execution is crucial for many applications. Today, also the energy consumption is getting more and more important for high performance computing. In this article, we investigate the performance and the energy consumption of Runge-Kutta methods solving systems of ordinary differential equations on recent Intel processors. Our specific interest is the study of different program versions of multithreaded Runge-Kutta methods which result from loop transformations within the nested loops over stage vectors and systems sizes. Four program versions of the Runge-Kutta method DOPRI5 are chosen and are applied to systems of ordinary differential equations with different workload. Experiments have been performed for different numbers of threads and the performance, power and energy consumption is reported and analyzed.
{"title":"How do Loop Transformations Affect the Energy Consumption of Multi-Threaded Runge-Kutta Methods?","authors":"T. Rauber, G. Rünger","doi":"10.1109/PDP2018.2018.00085","DOIUrl":"https://doi.org/10.1109/PDP2018.2018.00085","url":null,"abstract":"Runge-Kutta methods are widely used and popular solutions method for scientific simulations based on differential equations and, thus, their efficient execution is crucial for many applications. Today, also the energy consumption is getting more and more important for high performance computing. In this article, we investigate the performance and the energy consumption of Runge-Kutta methods solving systems of ordinary differential equations on recent Intel processors. Our specific interest is the study of different program versions of multithreaded Runge-Kutta methods which result from loop transformations within the nested loops over stage vectors and systems sizes. Four program versions of the Runge-Kutta method DOPRI5 are chosen and are applied to systems of ordinary differential equations with different workload. Experiments have been performed for different numbers of threads and the performance, power and energy consumption is reported and analyzed.","PeriodicalId":333367,"journal":{"name":"2018 26th Euromicro International Conference on Parallel, Distributed and Network-based Processing (PDP)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128569129","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-21DOI: 10.1109/PDP2018.2018.00071
Valentina Giansanti, D. D'Agostino, C. Maj, S. Beretta, I. Merelli
In complex phenotypes (e.g., psychiatric diseases) single locus tests, commonly performed with genome-wide association studies, have proven to be limited in discovering strong gene associations. A growing body of evidence suggests that epistatic non-linear effects may be responsible for complex phenotypes arising from the interaction of different biological factors. A major issue in epistasis analysis is the computational burden due to the huge number of statistical tests to be performed when considering all the potential genotype combinations. In this work, we developed a computational efficient approach to compute empirical p-values concerning the presence of epistasis at a genome-wide scale in bipolar disorder, which is a typical example of complex phenotype with a relevant but unexplained genetic background. By running our approach we were able to identify 13 epistasis interactions between variants located in genes potentially involved in biological processes associated with the analyzed phenotype.
{"title":"Computing Empirical P-Values for Estimating Gene-Gene Interactions in Genome-Wide Association Studies: A Parallel Computing Approach","authors":"Valentina Giansanti, D. D'Agostino, C. Maj, S. Beretta, I. Merelli","doi":"10.1109/PDP2018.2018.00071","DOIUrl":"https://doi.org/10.1109/PDP2018.2018.00071","url":null,"abstract":"In complex phenotypes (e.g., psychiatric diseases) single locus tests, commonly performed with genome-wide association studies, have proven to be limited in discovering strong gene associations. A growing body of evidence suggests that epistatic non-linear effects may be responsible for complex phenotypes arising from the interaction of different biological factors. A major issue in epistasis analysis is the computational burden due to the huge number of statistical tests to be performed when considering all the potential genotype combinations. In this work, we developed a computational efficient approach to compute empirical p-values concerning the presence of epistasis at a genome-wide scale in bipolar disorder, which is a typical example of complex phenotype with a relevant but unexplained genetic background. By running our approach we were able to identify 13 epistasis interactions between variants located in genes potentially involved in biological processes associated with the analyzed phenotype.","PeriodicalId":333367,"journal":{"name":"2018 26th Euromicro International Conference on Parallel, Distributed and Network-based Processing (PDP)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128966327","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-21DOI: 10.1109/PDP2018.2018.00017
Yuanfang Chen, Qingchuan Shi, Xiaoming Li
Simultaneous multithreading (SMT) is a unique computer architecture feature to increase the pipeline utilization and therefore, increase the instruction throughput. It improves instruction level throughput by simultaneously filling both vertical and horizontal super-scalar pipeline slots that are left unfilled by native threads. So far SMT has been implemented in hardware. However, hardware SMT implementations have its limitations. First, it is complex and expensive to implement—only higher-end processors are equipped with it even though lower-end processors have same pipeline design as the higher-end variants and might also benefit from it. SMT also introduces great power/energy and area overheads. Moreover, being a hardware feature, SMT is limited by the range and depth of instruction analysis that it can afford at execution time, therefore it is unlikely to benefit from high-level software knowledge about instruction mix and might lose many improvement opportunities. In this paper, we address the limitation of the hardware-based SMT and introduce CSSMT: Compiler based Software Simultaneous Multithreading (SMT). The main contribution of CSSMT is that it exploits high- level program profiles to purposefully "re-mix" instructions from multiple programs to better fill vertical and horizontal super- scalar pipeline slots so that the overall throughput is improved. Furthermore, CSSMT is a software-transformation technique that enables SMT at software level during compilation time. Therefore, it can help overcome the limitation of the hardware-based SMT implementation and is more portable. We test CSSMT with programs from SPEC2006 and NAS benchmarks and achieve up to 12% speedup of execution time (30.7% improvement in terms of multi-program throughput).
{"title":"CSSMT: Compiler Based Software Simultaneous Multithreading (SMT)","authors":"Yuanfang Chen, Qingchuan Shi, Xiaoming Li","doi":"10.1109/PDP2018.2018.00017","DOIUrl":"https://doi.org/10.1109/PDP2018.2018.00017","url":null,"abstract":"Simultaneous multithreading (SMT) is a unique computer architecture feature to increase the pipeline utilization and therefore, increase the instruction throughput. It improves instruction level throughput by simultaneously filling both vertical and horizontal super-scalar pipeline slots that are left unfilled by native threads. So far SMT has been implemented in hardware. However, hardware SMT implementations have its limitations. First, it is complex and expensive to implement—only higher-end processors are equipped with it even though lower-end processors have same pipeline design as the higher-end variants and might also benefit from it. SMT also introduces great power/energy and area overheads. Moreover, being a hardware feature, SMT is limited by the range and depth of instruction analysis that it can afford at execution time, therefore it is unlikely to benefit from high-level software knowledge about instruction mix and might lose many improvement opportunities. In this paper, we address the limitation of the hardware-based SMT and introduce CSSMT: Compiler based Software Simultaneous Multithreading (SMT). The main contribution of CSSMT is that it exploits high- level program profiles to purposefully \"re-mix\" instructions from multiple programs to better fill vertical and horizontal super- scalar pipeline slots so that the overall throughput is improved. Furthermore, CSSMT is a software-transformation technique that enables SMT at software level during compilation time. Therefore, it can help overcome the limitation of the hardware-based SMT implementation and is more portable. We test CSSMT with programs from SPEC2006 and NAS benchmarks and achieve up to 12% speedup of execution time (30.7% improvement in terms of multi-program throughput).","PeriodicalId":333367,"journal":{"name":"2018 26th Euromicro International Conference on Parallel, Distributed and Network-based Processing (PDP)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132347048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-21DOI: 10.1109/PDP2018.2018.00078
Gianpiero Costantino, F. Martinelli, I. Matteucci, A. Bertolino, Antonello Calabrò, E. Marchetti
The introduction of new generation ICT systems into vehicles makes them highly connected with the external World. As drawback, vehicle becomes potentially vulnerable to security attacks. Here, we consider a scenario in which Vehicular Networks and a Urban Network work together to realize a defence mechanism based on Reputation Systems. In this way, we are able to identify and isolate possible malicious vehicles acting that could send messages with the aim of reducing the availability of the network. We propose Context Aware Reputation Systems, CARS, able to identify insider attackers and isolate them taking into account contextual conditions derived from sensors spread along the entire urban network. Then, we experimentally evaluate CARS on a real data-set of mobility traces of taxis in Rome to compare the proposed systems with existing ones that do not consider contextual conditions. The preliminary results obtained are promising and show the feasibility and potentiality of CARS.
{"title":"CARS: Context Aware Reputation Systems to Evaluate Vehicles' Behaviour","authors":"Gianpiero Costantino, F. Martinelli, I. Matteucci, A. Bertolino, Antonello Calabrò, E. Marchetti","doi":"10.1109/PDP2018.2018.00078","DOIUrl":"https://doi.org/10.1109/PDP2018.2018.00078","url":null,"abstract":"The introduction of new generation ICT systems into vehicles makes them highly connected with the external World. As drawback, vehicle becomes potentially vulnerable to security attacks. Here, we consider a scenario in which Vehicular Networks and a Urban Network work together to realize a defence mechanism based on Reputation Systems. In this way, we are able to identify and isolate possible malicious vehicles acting that could send messages with the aim of reducing the availability of the network. We propose Context Aware Reputation Systems, CARS, able to identify insider attackers and isolate them taking into account contextual conditions derived from sensors spread along the entire urban network. Then, we experimentally evaluate CARS on a real data-set of mobility traces of taxis in Rome to compare the proposed systems with existing ones that do not consider contextual conditions. The preliminary results obtained are promising and show the feasibility and potentiality of CARS.","PeriodicalId":333367,"journal":{"name":"2018 26th Euromicro International Conference on Parallel, Distributed and Network-based Processing (PDP)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129980091","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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