Pub Date : 2003-05-13DOI: 10.1109/RELPHY.2003.1197780
W. Chien, Shunwang Chiang, S. Tseng, C.H.J. Huang, K. Yang, W. Wang, J. Zhou
As the product life cycle shrinks, qualification needs to be completed in a much shorter time. This makes wafer level reliability (WLR) an important tool, enabling results to be obtained in a much shorter time. The two key issues for WLR are to guarantee the same failure mechanisms as conventional package-level reliability (PLR) and to maintain a statistically acceptable correlation (in terms of parameter estimation, lifetime projections and trend). We report the correlation of WLR and PLR tests and present WLR control (WLRC) methodology to ensure in-line reliability/process stability and to assist new technology development. We also present WLRC cases/plots/models, which show the benefits of a special control chart and principal component analysis (PCA). Apart from its use for in-line monitoring, by suitably designing the test structures and choosing the fail criteria, we also apply WLRC as a quick assessment of process/tool change qualification. WLRC can be embedded in the wafer acceptance test (WAT). We show how to use WLRC data to formulate reliability-WAT-yield models to facilitate yield improvement and reliability optimization.
{"title":"Practical WLRC methodology & applications in a wafer foundry","authors":"W. Chien, Shunwang Chiang, S. Tseng, C.H.J. Huang, K. Yang, W. Wang, J. Zhou","doi":"10.1109/RELPHY.2003.1197780","DOIUrl":"https://doi.org/10.1109/RELPHY.2003.1197780","url":null,"abstract":"As the product life cycle shrinks, qualification needs to be completed in a much shorter time. This makes wafer level reliability (WLR) an important tool, enabling results to be obtained in a much shorter time. The two key issues for WLR are to guarantee the same failure mechanisms as conventional package-level reliability (PLR) and to maintain a statistically acceptable correlation (in terms of parameter estimation, lifetime projections and trend). We report the correlation of WLR and PLR tests and present WLR control (WLRC) methodology to ensure in-line reliability/process stability and to assist new technology development. We also present WLRC cases/plots/models, which show the benefits of a special control chart and principal component analysis (PCA). Apart from its use for in-line monitoring, by suitably designing the test structures and choosing the fail criteria, we also apply WLRC as a quick assessment of process/tool change qualification. WLRC can be embedded in the wafer acceptance test (WAT). We show how to use WLRC data to formulate reliability-WAT-yield models to facilitate yield improvement and reliability optimization.","PeriodicalId":344023,"journal":{"name":"2003 IEEE International Reliability Physics Symposium Proceedings, 2003. 41st Annual.","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115404407","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-05-13DOI: 10.1109/RELPHY.2003.1197828
M. Ershov, R. Lindley, S. Saxena, A. Shibkov, S. Minehane, J. Babcock, S. Winters, H. Karbasi, T. Yamashita, P. Clifton, M. Redford
We report a new effect - relaxation of pMOSFET degradation due to negative bias temperature instability (NBTI). "Apparent" NBTI degradation is reduced ("recovered") by as much as 30-50% after stress interruption, which can increase device lifetime by a factor of 10-30. Some problems associated with extrapolation of degradation with respect to time and stress voltage are also discussed.
{"title":"Transient effects and characterization methodology of negative bias temperature instability in pMOS transistors","authors":"M. Ershov, R. Lindley, S. Saxena, A. Shibkov, S. Minehane, J. Babcock, S. Winters, H. Karbasi, T. Yamashita, P. Clifton, M. Redford","doi":"10.1109/RELPHY.2003.1197828","DOIUrl":"https://doi.org/10.1109/RELPHY.2003.1197828","url":null,"abstract":"We report a new effect - relaxation of pMOSFET degradation due to negative bias temperature instability (NBTI). \"Apparent\" NBTI degradation is reduced (\"recovered\") by as much as 30-50% after stress interruption, which can increase device lifetime by a factor of 10-30. Some problems associated with extrapolation of degradation with respect to time and stress voltage are also discussed.","PeriodicalId":344023,"journal":{"name":"2003 IEEE International Reliability Physics Symposium Proceedings, 2003. 41st Annual.","volume":"96 2-4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120932219","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-05-13DOI: 10.1109/RELPHY.2003.1197798
Jaeduk Lee, Jeong-Hyuk Choi, Donggun Park, Kinam Kim
We have verified that as the cell transistor width decreases below 100 nm for the NAND flash memory interface trap generation increases rapidly by FN current stress on the tunnel oxide. Accordingly, in contrast to the SILC (Stress-Induced Leakage Current) mechanism for the large dimensional cell transistors, it is revealed that the major failure mechanism of the data retention of 90 nm cell transistors is the relaxation of interface traps, which consist of the fast and slow traps. For the interface trap analysis, a new analysis method using I/sub d/-V/sub g/ hysteresis curve is proposed.
{"title":"Degradation of tunnel oxide by FN current stress and its effects on data retention characteristics of 90 nm NAND flash memory cells","authors":"Jaeduk Lee, Jeong-Hyuk Choi, Donggun Park, Kinam Kim","doi":"10.1109/RELPHY.2003.1197798","DOIUrl":"https://doi.org/10.1109/RELPHY.2003.1197798","url":null,"abstract":"We have verified that as the cell transistor width decreases below 100 nm for the NAND flash memory interface trap generation increases rapidly by FN current stress on the tunnel oxide. Accordingly, in contrast to the SILC (Stress-Induced Leakage Current) mechanism for the large dimensional cell transistors, it is revealed that the major failure mechanism of the data retention of 90 nm cell transistors is the relaxation of interface traps, which consist of the fast and slow traps. For the interface trap analysis, a new analysis method using I/sub d/-V/sub g/ hysteresis curve is proposed.","PeriodicalId":344023,"journal":{"name":"2003 IEEE International Reliability Physics Symposium Proceedings, 2003. 41st Annual.","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121206827","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-05-13DOI: 10.1109/RELPHY.2003.1197829
D. Brisbin, A. Strachan, P. Chaparala
Today's power management devices often require operation in the 20-30 V range. These applications combine a high performance BiCMOS process with a power lateral n-channel DMOS (N-LDMOS) driver. To obtain high drive currents and low on-resistance, LDMOS devices are often implemented in transistor arrays. Because of the high voltages and currents applied to these arrays, hot carrier (HC) degradation is a real reliability concern. This paper differs from previous work in that it discusses for the first time one- and two-dimensional aspects of LDMOS transistor array layout on HC performance and introduces a novel LDMOS transistor layout featuring a drain ring that substantially improves the array's HC performance.
{"title":"Design optimization of N-LDMOS transistor arrays for hot carrier lifetime enhancement","authors":"D. Brisbin, A. Strachan, P. Chaparala","doi":"10.1109/RELPHY.2003.1197829","DOIUrl":"https://doi.org/10.1109/RELPHY.2003.1197829","url":null,"abstract":"Today's power management devices often require operation in the 20-30 V range. These applications combine a high performance BiCMOS process with a power lateral n-channel DMOS (N-LDMOS) driver. To obtain high drive currents and low on-resistance, LDMOS devices are often implemented in transistor arrays. Because of the high voltages and currents applied to these arrays, hot carrier (HC) degradation is a real reliability concern. This paper differs from previous work in that it discusses for the first time one- and two-dimensional aspects of LDMOS transistor array layout on HC performance and introduces a novel LDMOS transistor layout featuring a drain ring that substantially improves the array's HC performance.","PeriodicalId":344023,"journal":{"name":"2003 IEEE International Reliability Physics Symposium Proceedings, 2003. 41st Annual.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121239317","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-05-13DOI: 10.1109/RELPHY.2003.1197775
M. Stout, K. Tumin, C. Vargas, B. Gotchall
This paper compares the development and effectiveness of scan-based testing and functional testing using two microcontroller studies. This design-for-test methodology has been shown to reliably produce high quality products. This approach also provides a diagnostic failure analysis methodology that can greatly improve detection of quality and reliability failures.
{"title":"Challenges of testing high-volume, low-cost 8-bit microcontrollers","authors":"M. Stout, K. Tumin, C. Vargas, B. Gotchall","doi":"10.1109/RELPHY.2003.1197775","DOIUrl":"https://doi.org/10.1109/RELPHY.2003.1197775","url":null,"abstract":"This paper compares the development and effectiveness of scan-based testing and functional testing using two microcontroller studies. This design-for-test methodology has been shown to reliably produce high quality products. This approach also provides a diagnostic failure analysis methodology that can greatly improve detection of quality and reliability failures.","PeriodicalId":344023,"journal":{"name":"2003 IEEE International Reliability Physics Symposium Proceedings, 2003. 41st Annual.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130412215","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-05-13DOI: 10.1109/RELPHY.2003.1197788
Min Ding, H. Matsuhashi, P. Ho, A. Marathe, R. Master, V. Pham
In this paper, we describe a new approach and a new system developed for EM tests of solder balls in a packaging assembly. The approach was based on the Wheatstone bridge method, which provided significant improvement in the sensitivity for detecting EM damage in solder balls. In the bridge circuit, each of the arms can contain an ensemble of solder balls connected in series and/or in parallel to increase the number of solder balls being tested. Thus the method can be used for EM tests of a large ensemble of solder balls, extending the range of statistical detection of early failures and reducing EM test time. Using this method, EM tests were performed at 165/spl deg/ and 235/spl deg/C on 97Pb-3Sn solder balls in ceramic flip-chip packages. The results yielded an activation energy of 0.85 eV. By extending the test time to 2000 hrs at 165/spl deg/C, all of the test circuits except one showed resistance saturation, suggesting the existence of a threshold jL/sub c/ product. Subjected to a maximum resistance change of about 15 m/spl Omega/, the jL/sub c/ product was estimated to be 110 A-cm for 97Pb-3Sn solders at 165/spl deg/C.
本文介绍了一种用于封装组件中焊料球电磁测试的新方法和新系统。该方法基于惠斯通电桥法，显著提高了检测焊锡球电磁损伤的灵敏度。在桥接电路中，每个臂可以包含一系列串联和/或并联的焊球，以增加被测试的焊球数量。因此，该方法可用于大量焊锡球的电磁测试，扩大了早期故障的统计检测范围，缩短了电磁测试时间。利用该方法，对陶瓷倒装芯片封装中的97Pb-3Sn焊料球在165和235℃的环境下进行了电磁测试。结果得到活化能为0.85 eV。在165/spl度/C下延长测试时间至2000小时，除1个测试电路外，其余测试电路均出现电阻饱和，表明存在阈值jL/sub C / product。在165/spl℃下，97Pb-3Sn焊料的最大电阻变化约为15 m/spl ω /，其jL/sub c/产物估计为110 a -cm。
{"title":"Wheatstone bridge method for electromigration study of solder balls in flip-chip packages","authors":"Min Ding, H. Matsuhashi, P. Ho, A. Marathe, R. Master, V. Pham","doi":"10.1109/RELPHY.2003.1197788","DOIUrl":"https://doi.org/10.1109/RELPHY.2003.1197788","url":null,"abstract":"In this paper, we describe a new approach and a new system developed for EM tests of solder balls in a packaging assembly. The approach was based on the Wheatstone bridge method, which provided significant improvement in the sensitivity for detecting EM damage in solder balls. In the bridge circuit, each of the arms can contain an ensemble of solder balls connected in series and/or in parallel to increase the number of solder balls being tested. Thus the method can be used for EM tests of a large ensemble of solder balls, extending the range of statistical detection of early failures and reducing EM test time. Using this method, EM tests were performed at 165/spl deg/ and 235/spl deg/C on 97Pb-3Sn solder balls in ceramic flip-chip packages. The results yielded an activation energy of 0.85 eV. By extending the test time to 2000 hrs at 165/spl deg/C, all of the test circuits except one showed resistance saturation, suggesting the existence of a threshold jL/sub c/ product. Subjected to a maximum resistance change of about 15 m/spl Omega/, the jL/sub c/ product was estimated to be 110 A-cm for 97Pb-3Sn solders at 165/spl deg/C.","PeriodicalId":344023,"journal":{"name":"2003 IEEE International Reliability Physics Symposium Proceedings, 2003. 41st Annual.","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126699288","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-05-13DOI: 10.1109/RELPHY.2003.1197808
K. Nakashima, T. Yoshida, Y. Watanabe, Y. Mitsushima
A new technique to detect oxygen precipitates in Si wafers using highly selective reactive ion etching is presented. In this technique, oxygen precipitates in Si wafers are detected as Si cones which have an oxygen precipitate at the tip of each cone. It was demonstrated that this technique was capable of detecting nanometer-sized oxygen precipitates and estimating their size and morphology. In addition, the technique was found to evaluate the depth distribution of the precipitates with an accuracy of 0.3 /spl mu/m. The detectable size limit and depth resolution was found to be about ten times higher than those of LST. Moreover, relationships of the size or density of oxygen precipitates to OSF formation and GOI characteristics were demonstrated using this technique.
{"title":"A new approach to detect small-sized oxygen precipitates in Si wafers using reactive ion etching","authors":"K. Nakashima, T. Yoshida, Y. Watanabe, Y. Mitsushima","doi":"10.1109/RELPHY.2003.1197808","DOIUrl":"https://doi.org/10.1109/RELPHY.2003.1197808","url":null,"abstract":"A new technique to detect oxygen precipitates in Si wafers using highly selective reactive ion etching is presented. In this technique, oxygen precipitates in Si wafers are detected as Si cones which have an oxygen precipitate at the tip of each cone. It was demonstrated that this technique was capable of detecting nanometer-sized oxygen precipitates and estimating their size and morphology. In addition, the technique was found to evaluate the depth distribution of the precipitates with an accuracy of 0.3 /spl mu/m. The detectable size limit and depth resolution was found to be about ten times higher than those of LST. Moreover, relationships of the size or density of oxygen precipitates to OSF formation and GOI characteristics were demonstrated using this technique.","PeriodicalId":344023,"journal":{"name":"2003 IEEE International Reliability Physics Symposium Proceedings, 2003. 41st Annual.","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129204259","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-05-13DOI: 10.1109/RELPHY.2003.1197819
M. Rubin
This paper proposes a complete methodology of localizing functional scan failures on complex custom ASIC designs without the need for special test development or use of specialized design debug equipment. The effectiveness of the methodology was proven in the foundry on several ASIC products from two different companies. The results of this work provided necessary information for the FAB manufacturing teams to understand the nature of the problem and resulted in process enhancements, which enabled the FAB to achieve significant yield improvement in record time.
{"title":"Localization and analysis of functional failures in deep submicron advanced ASIC products","authors":"M. Rubin","doi":"10.1109/RELPHY.2003.1197819","DOIUrl":"https://doi.org/10.1109/RELPHY.2003.1197819","url":null,"abstract":"This paper proposes a complete methodology of localizing functional scan failures on complex custom ASIC designs without the need for special test development or use of specialized design debug equipment. The effectiveness of the methodology was proven in the foundry on several ASIC products from two different companies. The results of this work provided necessary information for the FAB manufacturing teams to understand the nature of the problem and resulted in process enhancements, which enabled the FAB to achieve significant yield improvement in record time.","PeriodicalId":344023,"journal":{"name":"2003 IEEE International Reliability Physics Symposium Proceedings, 2003. 41st Annual.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123442712","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-05-13DOI: 10.1109/RELPHY.2003.1197729
M. Mirabedini, V. Gopinath, A. Kamath, M.Y. Lee, W. Hsia, V. Hornback, Y. Le, A. Badowski, B. Baylis, E. Li, S. Prasad, O. Kobozeva, J. Haywood, W. Catabay, W. C. Yeh
This paper describes a 90 nm System-on-a-chip (SoC) technology with modular quadruple gate oxides (16, 28, 50, 64 /spl Aring/) on the same chip allowing integration of optimized transistors operating at supply voltages of 1, 1.2, 1.8, 2.5 and 3.3 Volts for different circuit applications. The proposed modular gate oxide process with pre-gate nitrogen implant was shown to be superior to conventional grow-etch-grow approach in terms of gate leakage current, integrity and interface quality of the multiple gate oxides. A high current drive of 1020/390 /spl mu/A//spl mu/m was demonstrated for N/P channel core transistors.
{"title":"A 90 nm CMOS technology with modular quadruple gate oxides for advanced SoC applications","authors":"M. Mirabedini, V. Gopinath, A. Kamath, M.Y. Lee, W. Hsia, V. Hornback, Y. Le, A. Badowski, B. Baylis, E. Li, S. Prasad, O. Kobozeva, J. Haywood, W. Catabay, W. C. Yeh","doi":"10.1109/RELPHY.2003.1197729","DOIUrl":"https://doi.org/10.1109/RELPHY.2003.1197729","url":null,"abstract":"This paper describes a 90 nm System-on-a-chip (SoC) technology with modular quadruple gate oxides (16, 28, 50, 64 /spl Aring/) on the same chip allowing integration of optimized transistors operating at supply voltages of 1, 1.2, 1.8, 2.5 and 3.3 Volts for different circuit applications. The proposed modular gate oxide process with pre-gate nitrogen implant was shown to be superior to conventional grow-etch-grow approach in terms of gate leakage current, integrity and interface quality of the multiple gate oxides. A high current drive of 1020/390 /spl mu/A//spl mu/m was demonstrated for N/P channel core transistors.","PeriodicalId":344023,"journal":{"name":"2003 IEEE International Reliability Physics Symposium Proceedings, 2003. 41st Annual.","volume":"294 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132530161","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-05-13DOI: 10.1109/RELPHY.2003.1197774
I. Kim, Se-Kyeong Choi, Jin-Hyeok Choi, Joosung Park
Circuits to apply dynamic operation stress (DOS) to DRAM cells in wafer burn-in (WBI) mode are successfully implemented and contribute to wafer level reliability characterization of DRAMs. We verify that DOS during the burn-in (BI) test deteriorates data retention time microscopically, which is mainly attributed to DOS-induced hot carrier (HC) degradation of DRAM cells. In addition, the DRAM reliability characterization results in the WBI mode are in good agreement with those by dynamic operation in the package burn-in (PBI) mode.
{"title":"DRAM reliability characterization by using dynamic operation stress in wafer burn-in mode","authors":"I. Kim, Se-Kyeong Choi, Jin-Hyeok Choi, Joosung Park","doi":"10.1109/RELPHY.2003.1197774","DOIUrl":"https://doi.org/10.1109/RELPHY.2003.1197774","url":null,"abstract":"Circuits to apply dynamic operation stress (DOS) to DRAM cells in wafer burn-in (WBI) mode are successfully implemented and contribute to wafer level reliability characterization of DRAMs. We verify that DOS during the burn-in (BI) test deteriorates data retention time microscopically, which is mainly attributed to DOS-induced hot carrier (HC) degradation of DRAM cells. In addition, the DRAM reliability characterization results in the WBI mode are in good agreement with those by dynamic operation in the package burn-in (PBI) mode.","PeriodicalId":344023,"journal":{"name":"2003 IEEE International Reliability Physics Symposium Proceedings, 2003. 41st Annual.","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130220724","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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