Timo Hönig, C. Eibel, Benedict Herzog, Heiko Janker, Peter Wägemann, Wolfgang Schröder-Preikschat
Energy has emerged to be the most important resource for computing systems. Despite the exceptional importance of energy, reducing its demand at application and system level remains a challenging task for programmers and engineers. This is aggravated by the fact that traditional energy-saving approaches are not only error-prone but even lead to adverse consequences (i.e. increased energy consumption). To address this concern, we present the FigarOS operating system for fine-grained system-level energy optimizations. The evaluation of our FigarOS implementation shows that the operating system lowers the energy consumption of processes by up to 2.9 x.
{"title":"Playing Hare and Tortoise: The FigarOS Kernel for Fine-Grained System-Level Energy Optimizations","authors":"Timo Hönig, C. Eibel, Benedict Herzog, Heiko Janker, Peter Wägemann, Wolfgang Schröder-Preikschat","doi":"10.1109/SBESC.2015.22","DOIUrl":"https://doi.org/10.1109/SBESC.2015.22","url":null,"abstract":"Energy has emerged to be the most important resource for computing systems. Despite the exceptional importance of energy, reducing its demand at application and system level remains a challenging task for programmers and engineers. This is aggravated by the fact that traditional energy-saving approaches are not only error-prone but even lead to adverse consequences (i.e. increased energy consumption). To address this concern, we present the FigarOS operating system for fine-grained system-level energy optimizations. The evaluation of our FigarOS implementation shows that the operating system lowers the energy consumption of processes by up to 2.9 x.","PeriodicalId":350033,"journal":{"name":"2015 Brazilian Symposium on Computing Systems Engineering (SBESC)","volume":"152 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131187610","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Thiago Zanivan Felisberto, Elder Dominghini Tramontin, Felipe Santos, A. S. Morales, Frank Siqueira, G. Araújo
The growing evolution in the development of embedded systems has raised a numerous amount of distributed applications. Such applications have a strong tendency to integrate various types of existing devices. This trend is aligned with the ideas of ubiquitous computing, which is expected to turn devices increasingly independent of people, making the relationship between technologies more natural and intuitive. The different communication rotocols used by these devices target a specific segment, such as multimedia sharing, electronic security, home automation and healthcare. However, this variety increases the complexity of device integration and represents an obstacle to their development. This paper presents an architecture capable of providing compatible services that can be requested using heterogeneous protocols and is based on the fundamentals of the service-oriented architecture. The central component of this architecture is a middleware capable of abstracting requests of different protocols, facilitating dynamic composition of services distributed in heterogeneous LAN. The proposed architecture is detailed in this article. In addition, several experiments were conducted to evaluate the performance of the proposed middleware, in pursuit of their boundaries and aiming to validate the adopted technologies. As far as we know, our work is the first one that provides interoperation between the DLNA and DPWS technologies.
{"title":"UDP4US: Universal Device Pipe for Ubiquitous Services","authors":"Thiago Zanivan Felisberto, Elder Dominghini Tramontin, Felipe Santos, A. S. Morales, Frank Siqueira, G. Araújo","doi":"10.1109/SBESC.2015.14","DOIUrl":"https://doi.org/10.1109/SBESC.2015.14","url":null,"abstract":"The growing evolution in the development of embedded systems has raised a numerous amount of distributed applications. Such applications have a strong tendency to integrate various types of existing devices. This trend is aligned with the ideas of ubiquitous computing, which is expected to turn devices increasingly independent of people, making the relationship between technologies more natural and intuitive. The different communication rotocols used by these devices target a specific segment, such as multimedia sharing, electronic security, home automation and healthcare. However, this variety increases the complexity of device integration and represents an obstacle to their development. This paper presents an architecture capable of providing compatible services that can be requested using heterogeneous protocols and is based on the fundamentals of the service-oriented architecture. The central component of this architecture is a middleware capable of abstracting requests of different protocols, facilitating dynamic composition of services distributed in heterogeneous LAN. The proposed architecture is detailed in this article. In addition, several experiments were conducted to evaluate the performance of the proposed middleware, in pursuit of their boundaries and aiming to validate the adopted technologies. As far as we know, our work is the first one that provides interoperation between the DLNA and DPWS technologies.","PeriodicalId":350033,"journal":{"name":"2015 Brazilian Symposium on Computing Systems Engineering (SBESC)","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128178563","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Cristiane Silva Garcia, D. Eckhard, J. Netto, C. Pereira, I. Müller
The wireless sensor networks (WSN) are gradually gaining attention because it is a key technology for the Internet of Things. For most of these networks, the data is usually collected in a manual way, by removing a memory unit or connecting the collector node to a personal computer. This is a constraint, because it demands the manipulation of the collector radio by the operator, which consists in a problem in practical applications. The main goal of this work is to present a non-invasive alternative way to collect the data by means of Bluetooth technology. The approach allows the development of hermetic devices, which is a desirable feature for practical deployment of the sensor nodes.
{"title":"Bluetooth Enabled Data Collector for Wireless Sensor Networks","authors":"Cristiane Silva Garcia, D. Eckhard, J. Netto, C. Pereira, I. Müller","doi":"10.1109/SBESC.2015.17","DOIUrl":"https://doi.org/10.1109/SBESC.2015.17","url":null,"abstract":"The wireless sensor networks (WSN) are gradually gaining attention because it is a key technology for the Internet of Things. For most of these networks, the data is usually collected in a manual way, by removing a memory unit or connecting the collector node to a personal computer. This is a constraint, because it demands the manipulation of the collector radio by the operator, which consists in a problem in practical applications. The main goal of this work is to present a non-invasive alternative way to collect the data by means of Bluetooth technology. The approach allows the development of hermetic devices, which is a desirable feature for practical deployment of the sensor nodes.","PeriodicalId":350033,"journal":{"name":"2015 Brazilian Symposium on Computing Systems Engineering (SBESC)","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129639883","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
E. Gurjão, Paulo Barbosa, Y. Medeiros, L. Albornoz
Due to complex safety requirements, medical devices must obey rigorous standards. In the development of these devices, modeling techniques must be used to analyze the design decisions in agreement with such standards. In this paper, we present a Matlab/Simulink specification as an analytical model for Automated External Defibrillators (AEDs) and its integration with a Model Based Systems Engineering (MBSE) approach through descriptive models. The proposed model allows us to analyze algorithms for decision of shock application, performance of circuits when obtaining the required voltage, safety of the produced energy for shock delivery and characteristics of signals produced at the output of the AED. The model is composed of modules with interfaces specification, allowing safe module replacement and the assessment of the module influence over the system at a technical level.
{"title":"A Model for Architecture Centric Development of Automated External Defibrillators","authors":"E. Gurjão, Paulo Barbosa, Y. Medeiros, L. Albornoz","doi":"10.1109/SBESC.2015.11","DOIUrl":"https://doi.org/10.1109/SBESC.2015.11","url":null,"abstract":"Due to complex safety requirements, medical devices must obey rigorous standards. In the development of these devices, modeling techniques must be used to analyze the design decisions in agreement with such standards. In this paper, we present a Matlab/Simulink specification as an analytical model for Automated External Defibrillators (AEDs) and its integration with a Model Based Systems Engineering (MBSE) approach through descriptive models. The proposed model allows us to analyze algorithms for decision of shock application, performance of circuits when obtaining the required voltage, safety of the produced energy for shock delivery and characteristics of signals produced at the output of the AED. The model is composed of modules with interfaces specification, allowing safe module replacement and the assessment of the module influence over the system at a technical level.","PeriodicalId":350033,"journal":{"name":"2015 Brazilian Symposium on Computing Systems Engineering (SBESC)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125000616","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Edmar Bellorini, M. Oyamada, R. Hexsel, A. Giron, I. Gimenes
The development of embedded systems requires methodologies to enable the integration of different levels of abstraction and able to deal with functional and non-functional requirements. Many methodologies are proposed like Software Product Line (SPL) and Model-driven Engineering (MDE), in order to reduce the complexity of the development process. This paper presents the use of a software product line approach for a digital magnifier development. The design flow starts from the specification using a SPL approach and follows a systematic set of steps to allow the application synthesis of desktop and embedded versions.
{"title":"Case Study of Product Line Approach to Provide Embedded and Desktop-Based Applications","authors":"Edmar Bellorini, M. Oyamada, R. Hexsel, A. Giron, I. Gimenes","doi":"10.1109/SBESC.2015.27","DOIUrl":"https://doi.org/10.1109/SBESC.2015.27","url":null,"abstract":"The development of embedded systems requires methodologies to enable the integration of different levels of abstraction and able to deal with functional and non-functional requirements. Many methodologies are proposed like Software Product Line (SPL) and Model-driven Engineering (MDE), in order to reduce the complexity of the development process. This paper presents the use of a software product line approach for a digital magnifier development. The design flow starts from the specification using a SPL approach and follows a systematic set of steps to allow the application synthesis of desktop and embedded versions.","PeriodicalId":350033,"journal":{"name":"2015 Brazilian Symposium on Computing Systems Engineering (SBESC)","volume":"38 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132624803","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents an approach for event-triggered wireless sensor networks (WSN) application modeling, aiming to evaluate the performance of WSN configurations with regards to metrics that are meaningful to specific application domains and respective end-users. It combines application, environment-generated workload and computing/communication infrastructure within a high-level modeling simulation framework, and includes modeling primitives to represent different kind of events based on different probabilities distributions. Such primitives help end-users to characterize their application workload and check the performance of specific WSN configurations when running realistic scenarios. Extensive experimental work shows that the proposed approach is effective in verifying whether a given WSN configuration can fulfill application non-functional requirements, as well as identifying the application behaviors that can lead a WSN to a break point after which it cannot further maintain application constraints.
{"title":"Impact of Temporal and Spatial Application Modeling on Event-Triggered Wireless Sensor Network Evaluation","authors":"L. Brisolara, P. Ferreira, L. Indrusiak","doi":"10.1109/SBESC.2015.13","DOIUrl":"https://doi.org/10.1109/SBESC.2015.13","url":null,"abstract":"This paper presents an approach for event-triggered wireless sensor networks (WSN) application modeling, aiming to evaluate the performance of WSN configurations with regards to metrics that are meaningful to specific application domains and respective end-users. It combines application, environment-generated workload and computing/communication infrastructure within a high-level modeling simulation framework, and includes modeling primitives to represent different kind of events based on different probabilities distributions. Such primitives help end-users to characterize their application workload and check the performance of specific WSN configurations when running realistic scenarios. Extensive experimental work shows that the proposed approach is effective in verifying whether a given WSN configuration can fulfill application non-functional requirements, as well as identifying the application behaviors that can lead a WSN to a break point after which it cannot further maintain application constraints.","PeriodicalId":350033,"journal":{"name":"2015 Brazilian Symposium on Computing Systems Engineering (SBESC)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129256759","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Ramon Nepomuceno, Jonatas C. Santos, L. O. Luz, Ivan Saraiva Silva
Nowadays, multi-core architectures have become mainstream in the microprocessor industry. However, while the number of cores integrated in a single chip growth, more important becomes the need for an adequate programming model. In recent years, the OpenCL programming model has attracted the attention of multi-core designers' community. This paper presents an OpenCL-compliant architecture and demonstrates that such programming model can be successfully used as programming model for general-purpose multi-core architectures.
{"title":"An OpenCL-Compliant Multi-core Platform and Its Companion Compiler","authors":"Ramon Nepomuceno, Jonatas C. Santos, L. O. Luz, Ivan Saraiva Silva","doi":"10.1109/SBESC.2015.29","DOIUrl":"https://doi.org/10.1109/SBESC.2015.29","url":null,"abstract":"Nowadays, multi-core architectures have become mainstream in the microprocessor industry. However, while the number of cores integrated in a single chip growth, more important becomes the need for an adequate programming model. In recent years, the OpenCL programming model has attracted the attention of multi-core designers' community. This paper presents an OpenCL-compliant architecture and demonstrates that such programming model can be successfully used as programming model for general-purpose multi-core architectures.","PeriodicalId":350033,"journal":{"name":"2015 Brazilian Symposium on Computing Systems Engineering (SBESC)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128807175","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Real-time mixed-criticality systems (MCS) are designed so that tasks with different criticality levels share the same computing platform. Scheduling mechanisms must ensure that high criticality tasks are safe independently of lower criticality tasks' behaviour. In this paper we provide theoretical schedulability properties for MCS by showing that: (a) the least upper bound on processor utilisation of MCS is in general null for both uniprocessor and multiprocessor platforms, (b) this bound lies in interval [ln 2, 2 (v2-1)] if higher criticality tasks do not have periods larger than lower criticality ones, and (c) if the task of these uniprocessor systems have harmonic periods, the least upper bound reaches 1.
{"title":"Considerations on the Least Upper Bound for Mixed-Criticality Real-Time Systems","authors":"J. Santos, George Lima, K. Bletsas","doi":"10.1109/SBESC.2015.18","DOIUrl":"https://doi.org/10.1109/SBESC.2015.18","url":null,"abstract":"Real-time mixed-criticality systems (MCS) are designed so that tasks with different criticality levels share the same computing platform. Scheduling mechanisms must ensure that high criticality tasks are safe independently of lower criticality tasks' behaviour. In this paper we provide theoretical schedulability properties for MCS by showing that: (a) the least upper bound on processor utilisation of MCS is in general null for both uniprocessor and multiprocessor platforms, (b) this bound lies in interval [ln 2, 2 (v2-1)] if higher criticality tasks do not have periods larger than lower criticality ones, and (c) if the task of these uniprocessor systems have harmonic periods, the least upper bound reaches 1.","PeriodicalId":350033,"journal":{"name":"2015 Brazilian Symposium on Computing Systems Engineering (SBESC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116251691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Ford-Fulkerson algorithm is widely used to solve maximum Graph-Flow problems and it can be applied to a range of different areas, including networking. This paper proposes an approach based on Ford-Fulkerson algorithm to maximize the flow (bandwidth usage) of computer network. Such method mitigates congestion problems and increases network utilization. In order to show the applicability of the proposed approach, this paper presents the analysis of different network scenarios.
{"title":"An Approach Based on Ford-Fulkerson Algorithm to Optimize Network Bandwidth Usage","authors":"E. P. Neto, G. Callou","doi":"10.1109/SBESC.2015.21","DOIUrl":"https://doi.org/10.1109/SBESC.2015.21","url":null,"abstract":"Ford-Fulkerson algorithm is widely used to solve maximum Graph-Flow problems and it can be applied to a range of different areas, including networking. This paper proposes an approach based on Ford-Fulkerson algorithm to maximize the flow (bandwidth usage) of computer network. Such method mitigates congestion problems and increases network utilization. In order to show the applicability of the proposed approach, this paper presents the analysis of different network scenarios.","PeriodicalId":350033,"journal":{"name":"2015 Brazilian Symposium on Computing Systems Engineering (SBESC)","volume":"469 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132986231","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Due to the power constraints of the current semiconductor technology, energy consumption has become an important factor for computer systems. Reducing energy consumption can mean more battery life for mobile devices or reduction of financial costs for data centers. One of the energy bottlenecks of computer systems is the information traffic between the processor and memory hierarchy. In this paper we evaluate the energy reduction of our new spill code minimization technique called color flipping in comparison with classical approaches. We implemented the Briggs' register allocator in the LLVM compiler framework with and without color flipping strategy and we ran some SPEC CPU 2006 benchmarks in a modified gem5 simulator for Cortex-A9. Then the energy consumption was estimated using the McPAT framework. Experimental results showed that our technique can reduce about 1% of the energy consumption of integer programs.
由于目前半导体技术的功率限制，能耗已成为计算机系统的一个重要因素。减少能源消耗可以延长移动设备的电池寿命，或者降低数据中心的财务成本。计算机系统的能量瓶颈之一是处理器和存储器之间的信息传输。在本文中，我们评估了我们的新的泄漏码最小化技术称为颜色翻转与传统方法的能源减少。我们在LLVM编译器框架中使用和不使用颜色翻转策略实现了Briggs的寄存器分配器，并在针对Cortex-A9的修改后的gem5模拟器中运行了一些SPEC CPU 2006基准测试。然后利用McPAT框架对能耗进行估算。实验结果表明，该方法可使整数程序的能耗降低1%左右。
{"title":"Decreasing Spill Code to Decrease Energy Consumption","authors":"Marcelo F. Luna, Felipe L. Silva, Wesley Attrot","doi":"10.1109/SBESC.2015.31","DOIUrl":"https://doi.org/10.1109/SBESC.2015.31","url":null,"abstract":"Due to the power constraints of the current semiconductor technology, energy consumption has become an important factor for computer systems. Reducing energy consumption can mean more battery life for mobile devices or reduction of financial costs for data centers. One of the energy bottlenecks of computer systems is the information traffic between the processor and memory hierarchy. In this paper we evaluate the energy reduction of our new spill code minimization technique called color flipping in comparison with classical approaches. We implemented the Briggs' register allocator in the LLVM compiler framework with and without color flipping strategy and we ran some SPEC CPU 2006 benchmarks in a modified gem5 simulator for Cortex-A9. Then the energy consumption was estimated using the McPAT framework. Experimental results showed that our technique can reduce about 1% of the energy consumption of integer programs.","PeriodicalId":350033,"journal":{"name":"2015 Brazilian Symposium on Computing Systems Engineering (SBESC)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125023687","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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