Keni Qiu, Zhiyao Gong, Dongqin Zhou, Weiwen Chen, Yongpan Liu
Harvested energy is intrinsically unstable and program execution will be interrupted frequently. To solve this problem, nonvolatile processor (NVP) is proposed because it can back up volatile state before the system energy is depleted. However, the backup and the recovery processes also consume non-negligible energy and delay program progress. To improve the performance of NVP, retention state has been proposed recently which can enable a system to retain the volatile data to wait for power resumption instead of saving data immediately. The objective of this paper is to forward program execution progress as much as possible by exploiting the retention state. Compared to the instant backup scheme, preliminary evaluation results report that power failures can be reduced by 81.6% and computation efficiency can be increased by 105%.
{"title":"Retention state-aware energy management for efficient nonvolatile processors: work-in-progress","authors":"Keni Qiu, Zhiyao Gong, Dongqin Zhou, Weiwen Chen, Yongpan Liu","doi":"10.1145/3125502.3129535","DOIUrl":"https://doi.org/10.1145/3125502.3129535","url":null,"abstract":"Harvested energy is intrinsically unstable and program execution will be interrupted frequently. To solve this problem, nonvolatile processor (NVP) is proposed because it can back up volatile state before the system energy is depleted. However, the backup and the recovery processes also consume non-negligible energy and delay program progress. To improve the performance of NVP, retention state has been proposed recently which can enable a system to retain the volatile data to wait for power resumption instead of saving data immediately. The objective of this paper is to forward program execution progress as much as possible by exploiting the retention state. Compared to the instant backup scheme, preliminary evaluation results report that power failures can be reduced by 81.6% and computation efficiency can be increased by 105%.","PeriodicalId":350509,"journal":{"name":"Proceedings of the Twelfth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Companion","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122745760","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Moreau, Felipe Augusto, Patrick Howe, Armin Alaghi, L. Ceze
Approximate computing aims to expose and exploit quality vs. efficiency tradeoffs to enable ever-more demanding applications on energy-constrained devices such as smartphones, or IoT devices. This paper makes the case for arbitrary quantization as a compelling approximation technique that exposes quality vs. energy tradeoffs and provides practical error guarantees. We present QAPPA (Quality Autotuner for Precision Programmable Accelerators), an autotuning framework for C/C++ programs that automatically minimizes the precision of each arithmetic and memory operation to meet user defined application level quality guarantees. QAPPA integrates energy models of precision scaling mechanisms to produce bandwidth and energy savings estimates for precision scalable accelerator designs. We show that QAPPA can exploit precision scaling mechanisms to meet arbitrary user-provided quality targets on the PERFECT benchmark suite to achieve significant energy savings and memory bandwidth reduction.
近似计算旨在暴露和利用质量与效率之间的权衡，以在智能手机或物联网设备等能源受限设备上实现要求越来越高的应用。本文将任意量化作为一种引人注目的近似技术，它暴露了质量与能量的权衡，并提供了实际的误差保证。我们提出了QAPPA (Quality Autotuner for Precision Programmable Accelerators)，这是一个C/ c++程序的自动调谐框架，可以自动最小化每个算术和内存操作的精度，以满足用户定义的应用程序级质量保证。QAPPA集成了精确缩放机制的能量模型，为精确缩放加速器设计提供带宽和节能估算。我们证明QAPPA可以利用精确缩放机制来满足PERFECT基准套件上任意用户提供的质量目标，从而实现显著的节能和内存带宽减少。
{"title":"Exploiting quality-energy tradeoffs with arbitrary quantization: special session paper","authors":"T. Moreau, Felipe Augusto, Patrick Howe, Armin Alaghi, L. Ceze","doi":"10.1145/3125502.3125544","DOIUrl":"https://doi.org/10.1145/3125502.3125544","url":null,"abstract":"Approximate computing aims to expose and exploit quality vs. efficiency tradeoffs to enable ever-more demanding applications on energy-constrained devices such as smartphones, or IoT devices. This paper makes the case for arbitrary quantization as a compelling approximation technique that exposes quality vs. energy tradeoffs and provides practical error guarantees. We present QAPPA (Quality Autotuner for Precision Programmable Accelerators), an autotuning framework for C/C++ programs that automatically minimizes the precision of each arithmetic and memory operation to meet user defined application level quality guarantees. QAPPA integrates energy models of precision scaling mechanisms to produce bandwidth and energy savings estimates for precision scalable accelerator designs. We show that QAPPA can exploit precision scaling mechanisms to meet arbitrary user-provided quality targets on the PERFECT benchmark suite to achieve significant energy savings and memory bandwidth reduction.","PeriodicalId":350509,"journal":{"name":"Proceedings of the Twelfth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Companion","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122255095","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Streaming applications are often modeled with Synchronous data flow graphs (SDFGs). A proper analysis of the models is helpful to predict the performance of a system. In this paper, we focus on the throughput analysis of memory-constrained SDFGs (MC SDFGs), which needs to choose a memory abstraction that decides when the space of consumed data is released and when the required space is claimed. Different memory abstractions may lead to different achievable throughputs. The existing techniques, however, consider only a certain abstraction. If a model is implemented according to other abstractions, the analysis result may not truly evaluate the performance of the system. In this paper, we present a unified framework for throughput analysis of MC SDFGs for difference abstractions, aiming to provide evaluations matching up to the corresponding implementations.
{"title":"A unified framework for throughput analysis of synchronous data flow graphs under memory constraints: work-in-progress","authors":"Xue-Yang Zhu","doi":"10.1145/3125502.3125535","DOIUrl":"https://doi.org/10.1145/3125502.3125535","url":null,"abstract":"Streaming applications are often modeled with Synchronous data flow graphs (SDFGs). A proper analysis of the models is helpful to predict the performance of a system. In this paper, we focus on the throughput analysis of memory-constrained SDFGs (MC SDFGs), which needs to choose a memory abstraction that decides when the space of consumed data is released and when the required space is claimed. Different memory abstractions may lead to different achievable throughputs. The existing techniques, however, consider only a certain abstraction. If a model is implemented according to other abstractions, the analysis result may not truly evaluate the performance of the system. In this paper, we present a unified framework for throughput analysis of MC SDFGs for difference abstractions, aiming to provide evaluations matching up to the corresponding implementations.","PeriodicalId":350509,"journal":{"name":"Proceedings of the Twelfth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Companion","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125226834","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Dave Burke, Dainius Jenkus, Issa Qiqieh, R. Shafik, Shidhartha Das, Alexandre Yakovlev
With increasing resolutions the volume of data generated by image processing applications is escalating dramatically. When coupled with real-time performance requirements, reducing energy consumption for such a large volume of data is proving challenging.
{"title":"Significance-driven adaptive approximate computing for energy-efficient image processing applications: special session paper","authors":"Dave Burke, Dainius Jenkus, Issa Qiqieh, R. Shafik, Shidhartha Das, Alexandre Yakovlev","doi":"10.1145/3125502.3125554","DOIUrl":"https://doi.org/10.1145/3125502.3125554","url":null,"abstract":"With increasing resolutions the volume of data generated by image processing applications is escalating dramatically. When coupled with real-time performance requirements, reducing energy consumption for such a large volume of data is proving challenging.","PeriodicalId":350509,"journal":{"name":"Proceedings of the Twelfth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Companion","volume":"887 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127078455","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Lattice-based cryptography is a promising family of post quantum algorithms. Contrary to other approaches, lattice-based primitives are extremely versatile and allow the realisation of several essential cryptographic primitives, such as encryption and digital signatures. In addition, they enable more sophisicated schemes to be constructed, such as Identity-based and Attribute-based Encryption, and even Fully Homomorphic Encryption. However, lattice-based cryptography requires novel implementations of several computationally intensive building blocks, for example discrete sampling (often from a Gaussian distribution) and Number Theoretic Transforms. This paper reviews the state-of-the-art in efficient designs for these core components in hardware and software.
{"title":"Efficient arithmetic for lattice-based cryptography: special session paper","authors":"E. O'Sullivan, F. Regazzoni","doi":"10.1145/3125502.3125543","DOIUrl":"https://doi.org/10.1145/3125502.3125543","url":null,"abstract":"Lattice-based cryptography is a promising family of post quantum algorithms. Contrary to other approaches, lattice-based primitives are extremely versatile and allow the realisation of several essential cryptographic primitives, such as encryption and digital signatures. In addition, they enable more sophisicated schemes to be constructed, such as Identity-based and Attribute-based Encryption, and even Fully Homomorphic Encryption. However, lattice-based cryptography requires novel implementations of several computationally intensive building blocks, for example discrete sampling (often from a Gaussian distribution) and Number Theoretic Transforms. This paper reviews the state-of-the-art in efficient designs for these core components in hardware and software.","PeriodicalId":350509,"journal":{"name":"Proceedings of the Twelfth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Companion","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123219272","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
System-level thermal management techniques normally map applications on non-adjacent cores to guarantee the safe temperature in many-core systems, while the communication efficiency will be oppositely affected by long-distance data transmission over conventional Network-on-Chips (NoC). SMART NoC has enabled single-cycle multi-hop bypass channels between distant cores, which can significantly reduce inter-processor communication latency. However, communication efficiency of SMART will be significantly diminished by express bypass break due to communication conflict. In order to achieve communication optimization with guaranteed system thermal reliability, we propose a dynamic reconfiguration method for logical interconnection topology through task mapping on top of SMART NoC. Active cores are physically decentralized on chip for better heat dissipation, while communication overhead can be reduced by minimized communication conflict and maximized bypass routing. Applicability and effectiveness of the proposed technique can be improved with significant achievements in reducing communication overhead and improving application performance, compared with state-of-the-art techniques.
{"title":"Communication optimization for thermal reliable many-core systems: work-in-progress","authors":"Weichen Liu, Lei Yang, Weiwen Jiang, Nan Guan","doi":"10.1145/3125502.3125539","DOIUrl":"https://doi.org/10.1145/3125502.3125539","url":null,"abstract":"System-level thermal management techniques normally map applications on non-adjacent cores to guarantee the safe temperature in many-core systems, while the communication efficiency will be oppositely affected by long-distance data transmission over conventional Network-on-Chips (NoC). SMART NoC has enabled single-cycle multi-hop bypass channels between distant cores, which can significantly reduce inter-processor communication latency. However, communication efficiency of SMART will be significantly diminished by express bypass break due to communication conflict. In order to achieve communication optimization with guaranteed system thermal reliability, we propose a dynamic reconfiguration method for logical interconnection topology through task mapping on top of SMART NoC. Active cores are physically decentralized on chip for better heat dissipation, while communication overhead can be reduced by minimized communication conflict and maximized bypass routing. Applicability and effectiveness of the proposed technique can be improved with significant achievements in reducing communication overhead and improving application performance, compared with state-of-the-art techniques.","PeriodicalId":350509,"journal":{"name":"Proceedings of the Twelfth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Companion","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126454914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Vatanparvar, Sina Faezi, Igor Burago, M. Levorato, M. A. Faruque
Battery and energy management methodologies such as automotive climate controls have been proposed to address the design challenges of driving range and battery lifetime in Electric Vehicles (EV). However, driving behavior estimation is a major factor neglected in these methodologies. In this paper, we propose a novel context-aware methodology for estimating the driving behavior in terms of future vehicle speeds that will be integrated into the EV battery optimization. We implement a driving behavior model using a variation of Artificial Neural Networks (ANN) called Nonlinear AutoRegressive model with eXogenous inputs (NARX). We train our novel context-aware NARX model based on historical behavior of real drivers, their recent driving reactions, and the route average speed retrieved from Google Maps in order to enable driver-specific and self-adaptive driving behavior modeling and long-term estimation. Our methodology shows only 12% error for up to 30-second speed prediction which is improved by 27% compared to the state-of-the-art. Hence, it can achieve up to 82% of the maximum energy saving and battery lifetime improvement possible by the ideal methodology where the future vehicle speed is known.
{"title":"Driving behavior modeling and estimation for battery optimization in electric vehicles: work-in-progress","authors":"K. Vatanparvar, Sina Faezi, Igor Burago, M. Levorato, M. A. Faruque","doi":"10.1145/3125502.3125542","DOIUrl":"https://doi.org/10.1145/3125502.3125542","url":null,"abstract":"Battery and energy management methodologies such as automotive climate controls have been proposed to address the design challenges of driving range and battery lifetime in Electric Vehicles (EV). However, driving behavior estimation is a major factor neglected in these methodologies. In this paper, we propose a novel context-aware methodology for estimating the driving behavior in terms of future vehicle speeds that will be integrated into the EV battery optimization. We implement a driving behavior model using a variation of Artificial Neural Networks (ANN) called Nonlinear AutoRegressive model with eXogenous inputs (NARX). We train our novel context-aware NARX model based on historical behavior of real drivers, their recent driving reactions, and the route average speed retrieved from Google Maps in order to enable driver-specific and self-adaptive driving behavior modeling and long-term estimation. Our methodology shows only 12% error for up to 30-second speed prediction which is improved by 27% compared to the state-of-the-art. Hence, it can achieve up to 82% of the maximum energy saving and battery lifetime improvement possible by the ideal methodology where the future vehicle speed is known.","PeriodicalId":350509,"journal":{"name":"Proceedings of the Twelfth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Companion","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127314126","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this work, we explore a security reference monitor (RM) design which borrows from the Flask security architecture. Our RM design goal is to achieve complete mediation by checking and verifying the authority and the authenticity of every access to every system object in systems-on-chip (SoCs). Access decisions are administered by a security logic "server" implemented as an extension of the peripheral bus. Initial results show a minimal increase in resource overhead and no significant impact on the performance.
{"title":"Towards the application of flask security architecture to SoC design: work-in-progress","authors":"Festus Hategekimana, C. Bobda","doi":"10.1145/3125502.3125558","DOIUrl":"https://doi.org/10.1145/3125502.3125558","url":null,"abstract":"In this work, we explore a security reference monitor (RM) design which borrows from the Flask security architecture. Our RM design goal is to achieve complete mediation by checking and verifying the authority and the authenticity of every access to every system object in systems-on-chip (SoCs). Access decisions are administered by a security logic \"server\" implemented as an extension of the peripheral bus. Initial results show a minimal increase in resource overhead and no significant impact on the performance.","PeriodicalId":350509,"journal":{"name":"Proceedings of the Twelfth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Companion","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129312620","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Unauthorized hardware or firmware modifications, known as trojans, can steal information, drain the battery, or damage IoT devices. This paper presents a stand-off self-referencing technique for detecting unauthorized activity. The proposed technique processes involuntary electromagnetic emissions on a separate hardware, which is physically decoupled from the device under test. When the device enter the test mode, it runs a predefined application repetitively with a fixed period. The periodicity ensures that the spectral electromagnetic power of the test application concentrates at known frequencies, leaving the remaining frequencies within the operation bandwidth at the noise level. Any deviations from the noise level for these unoccupied frequency locations indicates the presence of unknown (unauthorized) activity. Experiments based on hardware measurements show that the proposed technique achieves close to 100% detection accuracy at up to 120 cm distance.
{"title":"Remote detection of unauthorized activity via spectral analysis: work-in-progress","authors":"F. Karabacak, Ümit Y. Ogras, S. Ozev","doi":"10.1145/3125502.3125552","DOIUrl":"https://doi.org/10.1145/3125502.3125552","url":null,"abstract":"Unauthorized hardware or firmware modifications, known as trojans, can steal information, drain the battery, or damage IoT devices. This paper presents a stand-off self-referencing technique for detecting unauthorized activity. The proposed technique processes involuntary electromagnetic emissions on a separate hardware, which is physically decoupled from the device under test. When the device enter the test mode, it runs a predefined application repetitively with a fixed period. The periodicity ensures that the spectral electromagnetic power of the test application concentrates at known frequencies, leaving the remaining frequencies within the operation bandwidth at the noise level. Any deviations from the noise level for these unoccupied frequency locations indicates the presence of unknown (unauthorized) activity. Experiments based on hardware measurements show that the proposed technique achieves close to 100% detection accuracy at up to 120 cm distance.","PeriodicalId":350509,"journal":{"name":"Proceedings of the Twelfth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Companion","volume":"371 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115198232","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
William Hwang, M. Aly, Yash H. Malviya, Mingyu Gao, Tony F. Wu, C. Kozyrakis, H. Wong, S. Mitra
The world's appetite for abundant-data computing, where a massive amount of structured and unstructured data is analyzed, has increased dramatically. The computational demands of these applications, such as deep learning, far exceed the capabilities of today's systems, especially for energy-constrained embedded systems (e.g., mobile systems with limited battery capacity). These demands are unlikely to be met by isolated improvements in transistor or memory technologies, or integrated circuit (IC) architectures alone. Transformative nanosystems, which leverage the unique properties of emerging nanotechnologies to create new IC architectures, are required to deliver unprecedented functionality, performance, and energy efficiency. We show that the projected energy efficiency benefits of domain-specific 3D nanosystems is in the range of 1,000x (quantified using the product of system-level energy consumption and execution time) over today's domain-specific 2D systems with off-chip DRAM. Such a drastic improvement is key to enabling new capabilities such as deep learning in embedded systems.
{"title":"3D nanosystems enable embedded abundant-data computing: special session paper","authors":"William Hwang, M. Aly, Yash H. Malviya, Mingyu Gao, Tony F. Wu, C. Kozyrakis, H. Wong, S. Mitra","doi":"10.1145/3125502.3125531","DOIUrl":"https://doi.org/10.1145/3125502.3125531","url":null,"abstract":"The world's appetite for abundant-data computing, where a massive amount of structured and unstructured data is analyzed, has increased dramatically. The computational demands of these applications, such as deep learning, far exceed the capabilities of today's systems, especially for energy-constrained embedded systems (e.g., mobile systems with limited battery capacity). These demands are unlikely to be met by isolated improvements in transistor or memory technologies, or integrated circuit (IC) architectures alone. Transformative nanosystems, which leverage the unique properties of emerging nanotechnologies to create new IC architectures, are required to deliver unprecedented functionality, performance, and energy efficiency. We show that the projected energy efficiency benefits of domain-specific 3D nanosystems is in the range of 1,000x (quantified using the product of system-level energy consumption and execution time) over today's domain-specific 2D systems with off-chip DRAM. Such a drastic improvement is key to enabling new capabilities such as deep learning in embedded systems.","PeriodicalId":350509,"journal":{"name":"Proceedings of the Twelfth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Companion","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114149775","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：