The current SystemC modelling language lacks a standard framework that supports the modelling of wireless communication systems. This research investigates how wireless features can be incorporated into existing SystemC design methodology. The components to be investigated in order to achieve this target are divided into three parts: developing a system-level model of a digital wireless communication channel, creating a small library of dedicated elements at system level, and concluding with a case study on flocking behaviour system to validate the wireless extension methodology. In previous works, all these parts were successfully modelled and implemented. In this paper, the integration of communication modelling is introduced into design modelling during the early stages of system development. We use a flocking behaviour system to show how the stability of the system and converging point are measured and optimised in terms of system construction, using some important concepts of graph theory.
{"title":"Measuring and Optimising Convergence and Stability in Terms of System Construction in SystemC","authors":"I. Aref, N. Ahmed, F. Salazar, K. Elgaid","doi":"10.1109/ECBS.2010.36","DOIUrl":"https://doi.org/10.1109/ECBS.2010.36","url":null,"abstract":"The current SystemC modelling language lacks a standard framework that supports the modelling of wireless communication systems. This research investigates how wireless features can be incorporated into existing SystemC design methodology. The components to be investigated in order to achieve this target are divided into three parts: developing a system-level model of a digital wireless communication channel, creating a small library of dedicated elements at system level, and concluding with a case study on flocking behaviour system to validate the wireless extension methodology. In previous works, all these parts were successfully modelled and implemented. In this paper, the integration of communication modelling is introduced into design modelling during the early stages of system development. We use a flocking behaviour system to show how the stability of the system and converging point are measured and optimised in terms of system construction, using some important concepts of graph theory.","PeriodicalId":356361,"journal":{"name":"2010 17th IEEE International Conference and Workshops on Engineering of Computer Based Systems","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134175829","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Network-on-Chip (NoC) is the interconnection platform that answers the requirements of the modern on-Chip design. Small optimizations in NoC router architecture can show a significant improvement in the overall performance of NoC based systems. Power consumption, area overhead and the entire NoC performance is influenced by the router buffers. Resource sharing for on-chip network is critical to reduce the chip area and power consumption. Virtual channel buffer sharing by other router ports has been proposed to enhance the performance of on-chip communication. We approach the router architecture optimization by utilizing the idle buffers instead of increasing the number and size of buffers for desired throughput.
{"title":"Power and Area Efficient Design of Network-on-Chip Router through Utilization of Idle Buffers","authors":"Khalid Latif, T. Seceleanu, H. Tenhunen","doi":"10.1109/ECBS.2010.21","DOIUrl":"https://doi.org/10.1109/ECBS.2010.21","url":null,"abstract":"Network-on-Chip (NoC) is the interconnection platform that answers the requirements of the modern on-Chip design. Small optimizations in NoC router architecture can show a significant improvement in the overall performance of NoC based systems. Power consumption, area overhead and the entire NoC performance is influenced by the router buffers. Resource sharing for on-chip network is critical to reduce the chip area and power consumption. Virtual channel buffer sharing by other router ports has been proposed to enhance the performance of on-chip communication. We approach the router architecture optimization by utilizing the idle buffers instead of increasing the number and size of buffers for desired throughput.","PeriodicalId":356361,"journal":{"name":"2010 17th IEEE International Conference and Workshops on Engineering of Computer Based Systems","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134532595","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Software performance assessment is a very important task especially in the architectural design stage of software development. Software engineers must be supplied with techniques and tools that will allow them to complete this task without the extra cost of hiring quality assurance experts. This paper proposes the UML-JMT tool which provides functionalities for studying the expected performance characterisations of an architectural design. The UML-JMT tool uses the architectural design models as building blocks for an equivalent performance extended queuing network model (ENQ). This ENQ will be solved and analysed using the tools available in the JMT suite. In this paper we will explain the theoretical and technical aspects of the UML-JMT tool and we will use an example to explain the performance study steps and validate the results of this tool.
{"title":"UML-JMT: A Tool for Evaluating Performance Requirements","authors":"A. A. Abdullatif, R. Pooley","doi":"10.1109/ECBS.2010.30","DOIUrl":"https://doi.org/10.1109/ECBS.2010.30","url":null,"abstract":"Software performance assessment is a very important task especially in the architectural design stage of software development. Software engineers must be supplied with techniques and tools that will allow them to complete this task without the extra cost of hiring quality assurance experts. This paper proposes the UML-JMT tool which provides functionalities for studying the expected performance characterisations of an architectural design. The UML-JMT tool uses the architectural design models as building blocks for an equivalent performance extended queuing network model (ENQ). This ENQ will be solved and analysed using the tools available in the JMT suite. In this paper we will explain the theoretical and technical aspects of the UML-JMT tool and we will use an example to explain the performance study steps and validate the results of this tool.","PeriodicalId":356361,"journal":{"name":"2010 17th IEEE International Conference and Workshops on Engineering of Computer Based Systems","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133191788","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Multi-Level Testing is an emerging approach for test level integration through reuse. Its principal instrument, multi-level test cases, has only been considered in the context of bottom-up reuse to date. This test level integration strategy leads to excellent test effort reductions for embedded systems. However, bottom-up reuse is incapable of dealing with components featuring complex dynamic behavior. Top-down reuse is a novel test level integration approach that enables the reuse of test cases from higher test levels at lower test levels even in presence of complex dynamic behavior. With this practice, multi-level testing becomes applicable for a large set of new systems that can now benefit from great test effort reductions. In addition, test level design at the top test levels leads to system- and hence customer-oriented testing.
{"title":"Top-Down Reuse for Multi-level Testing","authors":"Abel Marrero Pérez, Stefan Kaiser","doi":"10.1109/ECBS.2010.23","DOIUrl":"https://doi.org/10.1109/ECBS.2010.23","url":null,"abstract":"Multi-Level Testing is an emerging approach for test level integration through reuse. Its principal instrument, multi-level test cases, has only been considered in the context of bottom-up reuse to date. This test level integration strategy leads to excellent test effort reductions for embedded systems. However, bottom-up reuse is incapable of dealing with components featuring complex dynamic behavior. Top-down reuse is a novel test level integration approach that enables the reuse of test cases from higher test levels at lower test levels even in presence of complex dynamic behavior. With this practice, multi-level testing becomes applicable for a large set of new systems that can now benefit from great test effort reductions. In addition, test level design at the top test levels leads to system- and hence customer-oriented testing.","PeriodicalId":356361,"journal":{"name":"2010 17th IEEE International Conference and Workshops on Engineering of Computer Based Systems","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121411065","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Camilo Carromeu, D. M. B. Paiva, Maria Istela Cagnin, Hana K. Rubinsztejn, M. Turine, K. Breitman
In spite of the wide coverage of Internet and the need for Web systems to support various governmental tasks, the Brazilian state of Mato Grosso do Sul (Central West region) did not have a technological infrastructure which was sufficient to meet these needs in 2001. This led to setting up the Laboratory of Software Engineering (LEDES) at the Department of Computing and Statistics (DCT), the current Computing Faculty (FACOM), at the Federal University of Mato Grosso do Sul (UFMS), which is now collaborating effectively with the state government providing technological solutions, especially in Web sites and Web applications (WebApps). Developing these solutions has made it possible to capture patterns, define flexible architecture and subsequently set up a process of a Software Product Line (SPL) to develop WebApps in e-gov domain, as well as create computational support tools which automatize this process. This paper presents such computational support tools, lessons learnt during the most relevant projects which have been developed since the creation of LEDES, and the architecture for e-gov web systems development, resultant from early experience.
{"title":"Component-Based Architecture for e-Gov Web Systems Development","authors":"Camilo Carromeu, D. M. B. Paiva, Maria Istela Cagnin, Hana K. Rubinsztejn, M. Turine, K. Breitman","doi":"10.1109/ECBS.2010.60","DOIUrl":"https://doi.org/10.1109/ECBS.2010.60","url":null,"abstract":"In spite of the wide coverage of Internet and the need for Web systems to support various governmental tasks, the Brazilian state of Mato Grosso do Sul (Central West region) did not have a technological infrastructure which was sufficient to meet these needs in 2001. This led to setting up the Laboratory of Software Engineering (LEDES) at the Department of Computing and Statistics (DCT), the current Computing Faculty (FACOM), at the Federal University of Mato Grosso do Sul (UFMS), which is now collaborating effectively with the state government providing technological solutions, especially in Web sites and Web applications (WebApps). Developing these solutions has made it possible to capture patterns, define flexible architecture and subsequently set up a process of a Software Product Line (SPL) to develop WebApps in e-gov domain, as well as create computational support tools which automatize this process. This paper presents such computational support tools, lessons learnt during the most relevant projects which have been developed since the creation of LEDES, and the architecture for e-gov web systems development, resultant from early experience.","PeriodicalId":356361,"journal":{"name":"2010 17th IEEE International Conference and Workshops on Engineering of Computer Based Systems","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114621735","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The demand for highly lightweight decentralised self-management of Wireless Sensor Networks (WSNs) has lead to the pursuit of emergent and bio-inspired solutions. I will introduce the WSN field briefly and highlight the aspects that differentiate it from 'normal' computing. I then present some of the research we have been doing in this field for decentralised network control and emergent systems management. Many of the algorithms produced to manage a WSN focus on one managerial aspect or parameter, limiting their usefulness and consuming already scarce resources. We have identified sets of common structures and elements of many well-known emergent algorithms. I present examples that exploit this to efficiently manage more than one managerial parameter or aspect. However, I also show how established evaluation methodologies are extremely misleading as when implementing the systems on actual devices we soon find some very unexpected results. I discuss this phenomenon, suggest causes and make some suggestions regarding the engineering of WSNs.
{"title":"Wireless Sensor Networking: The Pleasure and the Pain","authors":"J. Mccann","doi":"10.1109/ECBS.2010.61","DOIUrl":"https://doi.org/10.1109/ECBS.2010.61","url":null,"abstract":"The demand for highly lightweight decentralised self-management of Wireless Sensor Networks (WSNs) has lead to the pursuit of emergent and bio-inspired solutions. I will introduce the WSN field briefly and highlight the aspects that differentiate it from 'normal' computing. I then present some of the research we have been doing in this field for decentralised network control and emergent systems management. Many of the algorithms produced to manage a WSN focus on one managerial aspect or parameter, limiting their usefulness and consuming already scarce resources. We have identified sets of common structures and elements of many well-known emergent algorithms. I present examples that exploit this to efficiently manage more than one managerial parameter or aspect. However, I also show how established evaluation methodologies are extremely misleading as when implementing the systems on actual devices we soon find some very unexpected results. I discuss this phenomenon, suggest causes and make some suggestions regarding the engineering of WSNs.","PeriodicalId":356361,"journal":{"name":"2010 17th IEEE International Conference and Workshops on Engineering of Computer Based Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125791011","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents MATERA, a framework that integrates modeling in the Unified Modeling Language (UML), with requirement traceability across a model-based testing (MBT) process. The Graphical User Interface (GUI) of MATERA is implemented as a plug-in in the NoMagic's MagicDraw modeling tool, combining existing capabilities of MagicDraw with custom ones. MATERA supports graphical specification of the requirements using SysML and tracing of them to the UML models specifying the SUT. Model validation is performed in MagicDraw using both predefined and custom validation rules. The resulting models are automatically transformed into input for the Conformiq Qtronic tool, used for automated test generation. Upon executing the test scripts generated by Qtronic in the NetHawk's East execution environment, the results of statistic analysis of the test run are presented in the GUI. The back-traceability of the covered requirements from test to models is also provided in the GUI to facilitate the identification of the source of possible errors in the models. The approach we present shows that existing model-based languages and tools are an enabler for model-based testing and for providing integrated tool support across the MBT process.
{"title":"MATERA - An Integrated Framework for Model-Based Testing","authors":"Fredrik Abbors, A. Backlund, D. Truscan","doi":"10.1109/ECBS.2010.46","DOIUrl":"https://doi.org/10.1109/ECBS.2010.46","url":null,"abstract":"This paper presents MATERA, a framework that integrates modeling in the Unified Modeling Language (UML), with requirement traceability across a model-based testing (MBT) process. The Graphical User Interface (GUI) of MATERA is implemented as a plug-in in the NoMagic's MagicDraw modeling tool, combining existing capabilities of MagicDraw with custom ones. MATERA supports graphical specification of the requirements using SysML and tracing of them to the UML models specifying the SUT. Model validation is performed in MagicDraw using both predefined and custom validation rules. The resulting models are automatically transformed into input for the Conformiq Qtronic tool, used for automated test generation. Upon executing the test scripts generated by Qtronic in the NetHawk's East execution environment, the results of statistic analysis of the test run are presented in the GUI. The back-traceability of the covered requirements from test to models is also provided in the GUI to facilitate the identification of the source of possible errors in the models. The approach we present shows that existing model-based languages and tools are an enabler for model-based testing and for providing integrated tool support across the MBT process.","PeriodicalId":356361,"journal":{"name":"2010 17th IEEE International Conference and Workshops on Engineering of Computer Based Systems","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126663570","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In the case of a fault fail-safe systems achieve and maintain a safe state for people, environment and property. These systems are usually realized using microcontroller-based architectures. With respect to cost per unit and development effort for fail-safe systems, industry has to consider new approaches. An option is to realize simple safety functions using architectures that include CPLDs. A novel hardware architecture for embedded fail-safe systems is the outcome of recent research efforts at SIEMENS. This architecture is homogeneously redundant and contains, in contrast to similar systems, exclusively two CPLDs instead of microcontrollers. This paper is presenting design and implementation of the very first fail-safe system based on this architecture. This system targets the market of industrial automation. The fail-safe system enhances a power converter with safety functions. To achieve the required safety integrity, adequate measures able to detect random and permanent faults, are implemented. The novel fail-safe system adheres to the draft of the second edition of the IEC 61508, which includes requirements for the realization of safety functions using CPLDs, the IEC 61800-5-2 and the EN ISO 13849.
在发生故障的情况下，故障安全系统实现并维持人员、环境和财产的安全状态。这些系统通常使用基于微控制器的架构来实现。考虑到故障安全系统的单位成本和开发工作，工业界必须考虑新的方法。一种选择是使用包含cpld的架构来实现简单的安全功能。一种用于嵌入式故障安全系统的新型硬件架构是西门子公司最近的研究成果。与类似的系统相比，这种架构是均匀冗余的，并且只包含两个cpld而不是微控制器。本文介绍了基于该体系结构的第一个故障安全系统的设计和实现。本系统针对工业自动化市场。故障安全系统增强了具有安全功能的电源转换器。为了达到所需的安全完整性，需要采取足够的措施来检测随机和永久故障。新型故障安全系统符合IEC 61508第二版草案，其中包括使用cpld实现安全功能的要求，IEC 61800-5-2和EN ISO 13849。
{"title":"Design and Implementation of Safety Functions on a Novel CPLD-Based Fail-Safe System Architecture","authors":"G. Grießnig, R. Mader, C. Steger, R. Weiss","doi":"10.1109/ECBS.2010.29","DOIUrl":"https://doi.org/10.1109/ECBS.2010.29","url":null,"abstract":"In the case of a fault fail-safe systems achieve and maintain a safe state for people, environment and property. These systems are usually realized using microcontroller-based architectures. With respect to cost per unit and development effort for fail-safe systems, industry has to consider new approaches. An option is to realize simple safety functions using architectures that include CPLDs. A novel hardware architecture for embedded fail-safe systems is the outcome of recent research efforts at SIEMENS. This architecture is homogeneously redundant and contains, in contrast to similar systems, exclusively two CPLDs instead of microcontrollers. This paper is presenting design and implementation of the very first fail-safe system based on this architecture. This system targets the market of industrial automation. The fail-safe system enhances a power converter with safety functions. To achieve the required safety integrity, adequate measures able to detect random and permanent faults, are implemented. The novel fail-safe system adheres to the draft of the second edition of the IEC 61508, which includes requirements for the realization of safety functions using CPLDs, the IEC 61800-5-2 and the EN ISO 13849.","PeriodicalId":356361,"journal":{"name":"2010 17th IEEE International Conference and Workshops on Engineering of Computer Based Systems","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125275974","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
As a programming model, MapReduce is popularly and widely used in processing and generating large cluster of data sets distributed on large amount of machines. With its widespread use, its validity and other major properties need to be analyzed in a formal framework. In this paper, a formal model is presented using CSP method. We focus on the dominant parts of MapReduce and formalize them in detail. Through this formal model, the processing and function of each component can be clearly reflected. Moreover, we illustrate this formal model by an example computation. The result reflects the validity of MapReduce in some appropriate applications.
{"title":"Formalizing MapReduce with CSP","authors":"F. Yang, Wen Su, Huibiao Zhu, Qin Li","doi":"10.1109/ECBS.2010.50","DOIUrl":"https://doi.org/10.1109/ECBS.2010.50","url":null,"abstract":"As a programming model, MapReduce is popularly and widely used in processing and generating large cluster of data sets distributed on large amount of machines. With its widespread use, its validity and other major properties need to be analyzed in a formal framework. In this paper, a formal model is presented using CSP method. We focus on the dominant parts of MapReduce and formalize them in detail. Through this formal model, the processing and function of each component can be clearly reflected. Moreover, we illustrate this formal model by an example computation. The result reflects the validity of MapReduce in some appropriate applications.","PeriodicalId":356361,"journal":{"name":"2010 17th IEEE International Conference and Workshops on Engineering of Computer Based Systems","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132575094","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Software architectures constitute one of the main artefacts of software-intensive system development. They outline the essential components and interconnections of a software system at a high level of abstraction, ignoring unnecessary details. How to address the evolution of software architectures, however, is still an important topic of current research. In this article, we use UML 2 as architectural description language notation and formalise it with graph transformation, with a proof-of-concept implemented in the AGG tool. We use this formalisation to express and reason about architectural evolution patterns that introduce architectural styles.
{"title":"Guiding Architectural Restructuring through Architectural Styles","authors":"D. Tamzalit, T. Mens","doi":"10.1109/ECBS.2010.15","DOIUrl":"https://doi.org/10.1109/ECBS.2010.15","url":null,"abstract":"Software architectures constitute one of the main artefacts of software-intensive system development. They outline the essential components and interconnections of a software system at a high level of abstraction, ignoring unnecessary details. How to address the evolution of software architectures, however, is still an important topic of current research. In this article, we use UML 2 as architectural description language notation and formalise it with graph transformation, with a proof-of-concept implemented in the AGG tool. We use this formalisation to express and reason about architectural evolution patterns that introduce architectural styles.","PeriodicalId":356361,"journal":{"name":"2010 17th IEEE International Conference and Workshops on Engineering of Computer Based Systems","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130046170","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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