{"title":"DLL loop dynamics and jitter","authors":"","doi":"10.1049/pbcs059e_ch7","DOIUrl":"https://doi.org/10.1049/pbcs059e_ch7","url":null,"abstract":"","PeriodicalId":357134,"journal":{"name":"Analysis and Design of CMOS Clocking Circuits for Low Phase Noise","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117258081","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this chapter, the phase domain transfer function of each building block of the PLL is described. Because the intent of the PLL is "phase lock," the analysis should be done in the phase domain, so it is assumed that a phase error (O m ) is applied to the input of the PLL. For the derivation of the loop dynamics, Oerr is assumed to be small enough and to be introduced after the PLL achieves the phase lock.
{"title":"PLL loop dynamics and jitter","authors":"W. Bae, D. Jeong","doi":"10.1049/pbcs059e_ch6","DOIUrl":"https://doi.org/10.1049/pbcs059e_ch6","url":null,"abstract":"In this chapter, the phase domain transfer function of each building block of the PLL is described. Because the intent of the PLL is \"phase lock,\" the analysis should be done in the phase domain, so it is assumed that a phase error (O m ) is applied to the input of the PLL. For the derivation of the loop dynamics, Oerr is assumed to be small enough and to be introduced after the PLL achieves the phase lock.","PeriodicalId":357134,"journal":{"name":"Analysis and Design of CMOS Clocking Circuits for Low Phase Noise","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132706253","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
INTRODUCTION This note describes several square wave oscillators that can be built using CMOS logic elements. These circuits offer the following advantages: • Guaranteed startability • Relatively good stability with respect to power supply variations • Operation over a wide supply voltage range (3V to 15V) • Operation over a wide frequency range from less than 1 Hz to about 15 MHz • Low power consumption (see AN-90) • Easy interface to other logic families and elements including TTL Several RC oscillators and two crystal controlled oscillators are described. The stability of the RC oscillator will be sufficient for the bulk of applications; however, some applications will probably require the stability of a crystal. Some applications that require a lot of stability are: 1. Timekeeping over a long interval. A good deal of stability is required to duplicate the performance of an ordinary wrist watch (about 12 ppm). This is, of course, obtainable with a crystal. However, if the time interval is short and/or the resolution of the timekeeping device is relatively large, an RC oscillator may be adequate. For example: if a stopwatch is built with a resolution of tenths of seconds and the longest interval of interest is two minutes, then an accuracy of 1 part in 1200 (2 minutes x 60 seconds/minute x 10 tenth/second) may be acceptable since any error is less than the resolution of the device. 2. When logic elements are operated near their specified limits. It may be necessary to maintain clock frequency accuracy within very tight limits in order to avoid exceeding the limits of the logic family being used, or in which the timing relationships of clock signals in dynamic MOS memory or shift register systems must be preserved. 3. Baud rate generators for communications equipment. 4. Any system that must interface with other tightly specified systems. Particularly those that use a “handshake” technique in which Request or Acknowledge pulses must be of specific widths.
{"title":"CMOS oscillators","authors":"","doi":"10.1049/pbcs059e_ch3","DOIUrl":"https://doi.org/10.1049/pbcs059e_ch3","url":null,"abstract":"INTRODUCTION This note describes several square wave oscillators that can be built using CMOS logic elements. These circuits offer the following advantages: • Guaranteed startability • Relatively good stability with respect to power supply variations • Operation over a wide supply voltage range (3V to 15V) • Operation over a wide frequency range from less than 1 Hz to about 15 MHz • Low power consumption (see AN-90) • Easy interface to other logic families and elements including TTL Several RC oscillators and two crystal controlled oscillators are described. The stability of the RC oscillator will be sufficient for the bulk of applications; however, some applications will probably require the stability of a crystal. Some applications that require a lot of stability are: 1. Timekeeping over a long interval. A good deal of stability is required to duplicate the performance of an ordinary wrist watch (about 12 ppm). This is, of course, obtainable with a crystal. However, if the time interval is short and/or the resolution of the timekeeping device is relatively large, an RC oscillator may be adequate. For example: if a stopwatch is built with a resolution of tenths of seconds and the longest interval of interest is two minutes, then an accuracy of 1 part in 1200 (2 minutes x 60 seconds/minute x 10 tenth/second) may be acceptable since any error is less than the resolution of the device. 2. When logic elements are operated near their specified limits. It may be necessary to maintain clock frequency accuracy within very tight limits in order to avoid exceeding the limits of the logic family being used, or in which the timing relationships of clock signals in dynamic MOS memory or shift register systems must be preserved. 3. Baud rate generators for communications equipment. 4. Any system that must interface with other tightly specified systems. Particularly those that use a “handshake” technique in which Request or Acknowledge pulses must be of specific widths.","PeriodicalId":357134,"journal":{"name":"Analysis and Design of CMOS Clocking Circuits for Low Phase Noise","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124076487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-07-01DOI: 10.1049/pbcs059e_appendixb
{"title":"Survey on state-of-the-art clock generators","authors":"","doi":"10.1049/pbcs059e_appendixb","DOIUrl":"https://doi.org/10.1049/pbcs059e_appendixb","url":null,"abstract":"","PeriodicalId":357134,"journal":{"name":"Analysis and Design of CMOS Clocking Circuits for Low Phase Noise","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115828421","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this chapter, we start by defming time interval error (TIE), period jitter, and cycle -to -cycle jitter. Figure 2.1 shows the definitions of TIE, period jitter, and cycle -to -cycle jitter of a clock signal. TIE also has many different titles such as edge-to-edge jitter, time interval jitter, absolute jitter, phase jitter, or just jitter. TIE is defined as the absolute difference in the position of a clock's edge from the ideally exact position. Therefore, the ideal positions must be known or estimated to calculate TIE. On the other hand, the period jitter and cycle-to-cycle jitter do not need the ideal positions to be calculated. The period jitter, which is also called as cycle jitter, means the difference between any one measured clock period and the ideal clock period [3]. Although the period jitter definition refers to the ideal clock, its root of mean square (RMS) and peak -to -peak values are calculated statistically regardless of the ideal clock period.
{"title":"Introduction to phase noise and jitter","authors":"W. Bae, D. Jeong","doi":"10.1049/pbcs059e_ch2","DOIUrl":"https://doi.org/10.1049/pbcs059e_ch2","url":null,"abstract":"In this chapter, we start by defming time interval error (TIE), period jitter, and cycle -to -cycle jitter. Figure 2.1 shows the definitions of TIE, period jitter, and cycle -to -cycle jitter of a clock signal. TIE also has many different titles such as edge-to-edge jitter, time interval jitter, absolute jitter, phase jitter, or just jitter. TIE is defined as the absolute difference in the position of a clock's edge from the ideally exact position. Therefore, the ideal positions must be known or estimated to calculate TIE. On the other hand, the period jitter and cycle-to-cycle jitter do not need the ideal positions to be calculated. The period jitter, which is also called as cycle jitter, means the difference between any one measured clock period and the ideal clock period [3]. Although the period jitter definition refers to the ideal clock, its root of mean square (RMS) and peak -to -peak values are calculated statistically regardless of the ideal clock period.","PeriodicalId":357134,"journal":{"name":"Analysis and Design of CMOS Clocking Circuits for Low Phase Noise","volume":"122 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131386391","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Back Matter","authors":"","doi":"10.1049/pbcs059e_bm","DOIUrl":"https://doi.org/10.1049/pbcs059e_bm","url":null,"abstract":"","PeriodicalId":357134,"journal":{"name":"Analysis and Design of CMOS Clocking Circuits for Low Phase Noise","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120897750","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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