Pub Date : 2015-04-13DOI: 10.1109/CoolChips.2015.7158658
T. Sakamoto, Y. Tsuji, M. Tada, H. Makiyama, T. Hasegawa, Yoshiki Yamamoto, S. Okanishi, K. Maekawa, N. Banno, M. Miyamura, K. Okamoto, N. Iguchi, Y. Ogasahara, H. Oda, S. Kamohara, Y. Yamagata, N. Sugii, H. Hada
We present an ultra-low-power Microcontroller Unit (MCU) with an embedded atom switch ROM, which performs a 0.33-1.2 V operation voltage and 46.8-μA/MHz active current (or 18.26-μW/MHz active power). The MCU is fabricated by the hybrid of Silicon-On-Thin-Buried-oxide (SOTB) CMOS and bulk CMOS [1]. The SOTB CMOS with a body-bias voltage control realizes a high drivability up to 40-MHz operation at 0.54 V and small sleep power (0.628 μW), simultaneously.
设计了一种嵌入原子开关ROM的超低功耗微控制器(MCU)，工作电压为0.33 ~ 1.2 V，工作电流为46.8 μ a /MHz，工作功率为18.26 μ w /MHz。该MCU是由薄埋氧化硅(SOTB) CMOS和体CMOS混合制成的[1]。采用体偏置电压控制的SOTB CMOS可在0.54 V下实现高达40 mhz的高驱动性，同时具有较小的睡眠功率(0.628 μW)。
{"title":"0.39-V, 18.26-µW/MHz SOTB CMOS Microcontroller with embedded atom switch ROM","authors":"T. Sakamoto, Y. Tsuji, M. Tada, H. Makiyama, T. Hasegawa, Yoshiki Yamamoto, S. Okanishi, K. Maekawa, N. Banno, M. Miyamura, K. Okamoto, N. Iguchi, Y. Ogasahara, H. Oda, S. Kamohara, Y. Yamagata, N. Sugii, H. Hada","doi":"10.1109/CoolChips.2015.7158658","DOIUrl":"https://doi.org/10.1109/CoolChips.2015.7158658","url":null,"abstract":"We present an ultra-low-power Microcontroller Unit (MCU) with an embedded atom switch ROM, which performs a 0.33-1.2 V operation voltage and 46.8-μA/MHz active current (or 18.26-μW/MHz active power). The MCU is fabricated by the hybrid of Silicon-On-Thin-Buried-oxide (SOTB) CMOS and bulk CMOS [1]. The SOTB CMOS with a body-bias voltage control realizes a high drivability up to 40-MHz operation at 0.54 V and small sleep power (0.628 μW), simultaneously.","PeriodicalId":358999,"journal":{"name":"2015 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS XVIII)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124025074","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-13DOI: 10.1109/CoolChips.2015.7158660
Masayuki Sato, Chengguang Han, K. Komatsu, Ryusuke Egawa, H. Takizawa, Hiroaki Kobayashi
DRAM-based main memories are energy-hungry components of modern computer systems. Since accesses to DRAM need a complex protocol, the performance of an address-mapping scheme that decides physical locations of data based on physical addresses has a big impact on energy consumption. To improve the energy efficiency, this paper proposes a mechanism that dynamically selects an appropriate address-mapping scheme under the consideration of a trade-off between performance and power consumption. The mechanism works so as to reduce the energy consumption of the main memory. The evaluation results show that the proposed mechanism can reduce the energy consumption in comparison with conventional address-mapping schemes, which do not change their address mappings.
{"title":"An energy-efficient dynamic memory address mapping mechanism","authors":"Masayuki Sato, Chengguang Han, K. Komatsu, Ryusuke Egawa, H. Takizawa, Hiroaki Kobayashi","doi":"10.1109/CoolChips.2015.7158660","DOIUrl":"https://doi.org/10.1109/CoolChips.2015.7158660","url":null,"abstract":"DRAM-based main memories are energy-hungry components of modern computer systems. Since accesses to DRAM need a complex protocol, the performance of an address-mapping scheme that decides physical locations of data based on physical addresses has a big impact on energy consumption. To improve the energy efficiency, this paper proposes a mechanism that dynamically selects an appropriate address-mapping scheme under the consideration of a trade-off between performance and power consumption. The mechanism works so as to reduce the energy consumption of the main memory. The evaluation results show that the proposed mechanism can reduce the energy consumption in comparison with conventional address-mapping schemes, which do not change their address mappings.","PeriodicalId":358999,"journal":{"name":"2015 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS XVIII)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125587995","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-13DOI: 10.1109/CoolChips.2015.7158663
Raghuraman Balasubramanian, Vinay Gangadhar, Ziliang Guo, C. Ho, Cherin Joseph, J. Menon, M. Drumond, Robin Paul, Sharath Prasad, Pradip Valathol, K. Sankaralingam
Graphic Processing Unit (GPU) based general purpose computing is developing as a viable alternative to CPU based computing in many domains. In this paper, we introduce MIAOW (Many-core Integrated Accelerator Of Wisconsin), an open source RTL implementation of the AMD Southern Islands GPGPU ISA, capable of running unmodified OpenCL-based applications. We present our design motivated by our goals to create a realistic, flexible, OpenCL compatible GPGPU, capable of emulating a full system. We demonstrate that MIAOW enables disruptive and transformative research and has the potential to bring all of the benefits of open source development to GPUs in real products in the long term.
{"title":"MIAOW - An open source RTL implementation of a GPGPU","authors":"Raghuraman Balasubramanian, Vinay Gangadhar, Ziliang Guo, C. Ho, Cherin Joseph, J. Menon, M. Drumond, Robin Paul, Sharath Prasad, Pradip Valathol, K. Sankaralingam","doi":"10.1109/CoolChips.2015.7158663","DOIUrl":"https://doi.org/10.1109/CoolChips.2015.7158663","url":null,"abstract":"Graphic Processing Unit (GPU) based general purpose computing is developing as a viable alternative to CPU based computing in many domains. In this paper, we introduce MIAOW (Many-core Integrated Accelerator Of Wisconsin), an open source RTL implementation of the AMD Southern Islands GPGPU ISA, capable of running unmodified OpenCL-based applications. We present our design motivated by our goals to create a realistic, flexible, OpenCL compatible GPGPU, capable of emulating a full system. We demonstrate that MIAOW enables disruptive and transformative research and has the potential to bring all of the benefits of open source development to GPUs in real products in the long term.","PeriodicalId":358999,"journal":{"name":"2015 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS XVIII)","volume":"206 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132539734","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-13DOI: 10.1109/CoolChips.2015.7158659
JinSeok Oh, Sungyu Kim, Eunji Jeong, Soo-Mook Moon
Program analysis to check performance bottleneck or execution coverage is often implemented by instrumentation. Static binary instrumentation (SBI) adds the probing code before runtime, and dynamic binary instrumentation (DBI) changes the code at runtime with an OS support. Unfortunately, both are not appropriate for instrumenting embedded firmware such as the program on the flash memory controller, since it should be analyzed “as-is” on the real target for more realistic testing with target-specific conditions; additional code added by SBI might not fit in the limited memory of the target, while the OS support required by DBI is often not available on the target platform. This paper proposes a novel OS-less DBI framework using a hardware debugger for analyzing this embedded firmware. Our DBI does not increase the code size nor relies on any OS support. We experimented with our DBI tool for performance profiling and code coverage to check its usefulness. We also experimented on the real flash memory controller.
{"title":"OS-less dynamic binary instrumentation for embedded firmware","authors":"JinSeok Oh, Sungyu Kim, Eunji Jeong, Soo-Mook Moon","doi":"10.1109/CoolChips.2015.7158659","DOIUrl":"https://doi.org/10.1109/CoolChips.2015.7158659","url":null,"abstract":"Program analysis to check performance bottleneck or execution coverage is often implemented by instrumentation. Static binary instrumentation (SBI) adds the probing code before runtime, and dynamic binary instrumentation (DBI) changes the code at runtime with an OS support. Unfortunately, both are not appropriate for instrumenting embedded firmware such as the program on the flash memory controller, since it should be analyzed “as-is” on the real target for more realistic testing with target-specific conditions; additional code added by SBI might not fit in the limited memory of the target, while the OS support required by DBI is often not available on the target platform. This paper proposes a novel OS-less DBI framework using a hardware debugger for analyzing this embedded firmware. Our DBI does not increase the code size nor relies on any OS support. We experimented with our DBI tool for performance profiling and code coverage to check its usefulness. We also experimented on the real flash memory controller.","PeriodicalId":358999,"journal":{"name":"2015 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS XVIII)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125176244","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-13DOI: 10.1109/CoolChips.2015.7158662
Akira Takeda, Akira Yokosawa, Shintarou Sano, Shunsuke Sasaki, T. Kodaka, T. Tokuyoshi, T. Kizu
On wearable devices where an MCU primarily remains in an idle state, keeping the MCU in a deep sleep mode during idle periods can lead to significant power reduction. Since the deep sleep mode has a relatively high wake-up overhead, one of the effective techniques for power reduction is to decrease the wake-up frequency of the MCU. Meanwhile, due to the recent trend of increasing the number of sensors embedded in wearable devices, the MCU must wake up more frequently for data acquisitions from the sensors. This indicates an increase in power consumption caused by frequent wakeups. In this paper, we propose a new method to achieve power reduction of the MCU for wearable applications. The applications acquire data periodically from multiple sensors. Our proposed method achieves low power consumption by gathering the scattered data acquisitions of the sensors and decreasing the wake-up frequency. The experimental result shows that the proposed method achieved an 8.5-31% power reduction in the MCU.
{"title":"A novel energy-efficient data acquisition method for wearable devices","authors":"Akira Takeda, Akira Yokosawa, Shintarou Sano, Shunsuke Sasaki, T. Kodaka, T. Tokuyoshi, T. Kizu","doi":"10.1109/CoolChips.2015.7158662","DOIUrl":"https://doi.org/10.1109/CoolChips.2015.7158662","url":null,"abstract":"On wearable devices where an MCU primarily remains in an idle state, keeping the MCU in a deep sleep mode during idle periods can lead to significant power reduction. Since the deep sleep mode has a relatively high wake-up overhead, one of the effective techniques for power reduction is to decrease the wake-up frequency of the MCU. Meanwhile, due to the recent trend of increasing the number of sensors embedded in wearable devices, the MCU must wake up more frequently for data acquisitions from the sensors. This indicates an increase in power consumption caused by frequent wakeups. In this paper, we propose a new method to achieve power reduction of the MCU for wearable applications. The applications acquire data periodically from multiple sensors. Our proposed method achieves low power consumption by gathering the scattered data acquisitions of the sensors and decreasing the wake-up frequency. The experimental result shows that the proposed method achieved an 8.5-31% power reduction in the MCU.","PeriodicalId":358999,"journal":{"name":"2015 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS XVIII)","volume":"88 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125364091","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/coolchips.2015.7158524
Hiroaki Kobayashi
It is my pleasure to welcome you to the COOL Chips XVIII, the 18th IEEE Symposium on Low-Power and High-Speed Chips. COOL Chips Conference Series started in 1998, which was held in Tokyo as a one-day event of invited talks only. Now COOL Chips is a three-day event fully sponsored by IEEE Computer Society, which covers not only the chip architecture design, but also software technologies at system software and application levels.
{"title":"Message from the organizing committee chair","authors":"Hiroaki Kobayashi","doi":"10.1109/coolchips.2015.7158524","DOIUrl":"https://doi.org/10.1109/coolchips.2015.7158524","url":null,"abstract":"It is my pleasure to welcome you to the COOL Chips XVIII, the 18th IEEE Symposium on Low-Power and High-Speed Chips. COOL Chips Conference Series started in 1998, which was held in Tokyo as a one-day event of invited talks only. Now COOL Chips is a three-day event fully sponsored by IEEE Computer Society, which covers not only the chip architecture design, but also software technologies at system software and application levels.","PeriodicalId":358999,"journal":{"name":"2015 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS XVIII)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125330261","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/bigdatacongress.2015.6
M. Ikeda, F. Arakawa
Welcome to COOL Chips XVIII, an international symposium that provides you with the latest developments on low-power and high-speed chips. This year we are bringing you an exciting program that includes six keynote speeches, three invited speeches, three instructive special invited lectures, two special invited presentations and one panel discussion in this noble harbor city of Yokohama. We have two keynote speeches and two invited speeches on 14th April. The first keynote speech will be given by Dr. Tsuyoshi Abe of Intel. He will give us perspective and intention for advancing Moore's Low. The second will be from Dr. Michael Rosenfield of IBM. He will talk about data centric systems from both architecture and solution points of view. Two invited talks are both related to advanced driving assistance systems. The first invited talk will be given by Dr. Motoki Kimura of Renesas Electronics, on image recognition hardware. The second will be given by Mr. Takashi Miyamori of Toshiba, on a heterogeneous multi-core SoC.
{"title":"Message from the program committee chairs","authors":"M. Ikeda, F. Arakawa","doi":"10.1109/bigdatacongress.2015.6","DOIUrl":"https://doi.org/10.1109/bigdatacongress.2015.6","url":null,"abstract":"Welcome to COOL Chips XVIII, an international symposium that provides you with the latest developments on low-power and high-speed chips. This year we are bringing you an exciting program that includes six keynote speeches, three invited speeches, three instructive special invited lectures, two special invited presentations and one panel discussion in this noble harbor city of Yokohama. We have two keynote speeches and two invited speeches on 14th April. The first keynote speech will be given by Dr. Tsuyoshi Abe of Intel. He will give us perspective and intention for advancing Moore's Low. The second will be from Dr. Michael Rosenfield of IBM. He will talk about data centric systems from both architecture and solution points of view. Two invited talks are both related to advanced driving assistance systems. The first invited talk will be given by Dr. Motoki Kimura of Renesas Electronics, on image recognition hardware. The second will be given by Mr. Takashi Miyamori of Toshiba, on a heterogeneous multi-core SoC.","PeriodicalId":358999,"journal":{"name":"2015 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS XVIII)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116907932","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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