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2014 Formal Methods in Computer-Aided Design (FMCAD)最新文献

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Interpolation with Guided Refinement: Revisiting incrementality in SAT-based unbounded model checking 带导向精化的插值:重新审视基于sat的无界模型检验中的递增性
Pub Date : 2014-10-21 DOI: 10.1007/s10703-022-00406-7
G. Cabodi, M. Palena, P. Pasini
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引用次数: 16
Synthesis of synchronization using uninterpreted functions 使用未解释函数的同步合成
Pub Date : 2014-10-21 DOI: 10.1109/FMCAD.2014.6987593
R. Bloem, Georg Hofferek, Bettina Könighofer, Robert Könighofer, Simon Außerlechner, Raphael Spork
Correctness of a program with respect to concurrency is often hard to achieve, but easy to specify: the concurrent program should produce the same results as a sequential reference version. We show how to automatically insert small atomic sections into a program to ensure correctness with respect to this implicit specification. Using techniques from bounded software model checking, we transform the program into an SMT formula that becomes unsatisfiable when we add correct atomic sections. By using uninterpreted functions to abstract data-related computational details, we make our approach applicable to programs with very complex computations, e.g., cryptographic algorithms. Our method starts with an empty set of atomic sections, and, based on counterexamples obtained from the SMT solver, refines the program by adding new atomic sections until correctness is achieved. We compare two different such refinement methods and provide experimental results, including Linux kernel modules where we successfully fix race conditions.
程序在并发性方面的正确性通常很难实现,但很容易指定:并发程序应该产生与顺序引用版本相同的结果。我们将展示如何自动地将小的原子节插入到程序中,以确保该隐式规范的正确性。使用来自有界软件模型检查的技术,我们将程序转换为SMT公式,当我们添加正确的原子部分时,该公式将变得不令人满意。通过使用未解释的函数来抽象与数据相关的计算细节,我们使我们的方法适用于具有非常复杂计算的程序,例如加密算法。我们的方法从一组空的原子节开始,并基于从SMT求解器获得的反例,通过添加新的原子节来改进程序,直到实现正确性。我们比较了两种不同的细化方法,并提供了实验结果,其中包括我们成功修复竞争条件的Linux内核模块。
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引用次数: 17
Finding conflicting instances of quantified formulas in SMT 发现SMT中量化公式的冲突实例
Pub Date : 2014-10-21 DOI: 10.1109/FMCAD.2014.6987613
Andrew Reynolds, C. Tinelli, L. D. Moura
In the past decade, Satisfiability Modulo Theories (SMT) solvers have been used successfully in a variety of applications including verification, automated theorem proving, and synthesis. While such solvers are highly adept at handling ground constraints in several decidable background theories, they primarily rely on heuristic quantifier instantiation methods such as E-matching to process quantified formulas. The success of these methods is often hindered by an overproduction of instantiations which makes ground level reasoning difficult. We introduce a new technique that alleviates this shortcoming by first discovering instantiations that are in conflict with the current state of the solver. The solver only resorts to traditional heuristic methods when such instantiations cannot be found, thus decreasing its dependence upon E-matching. Our experimental results show that our technique significantly reduces the number of instantiations required by an SMT solver to answer "unsatisfiable" for several benchmark libraries, and consequently leads to improvements over state-of-the-art implementations.
在过去的十年中,可满足模理论(SMT)解算器已经成功地应用于各种应用,包括验证、自动定理证明和综合。虽然这样的求解器在处理几个可确定背景理论中的地面约束方面非常熟练,但它们主要依赖于启发式量词实例化方法,如e匹配来处理量化公式。这些方法的成功常常被实例化的过度产生所阻碍,这使得底层的推理变得困难。我们引入了一种新技术,通过首先发现与求解器当前状态冲突的实例来缓解这一缺点。求解器只有在找不到实例时才采用传统的启发式方法,从而减少了对e匹配的依赖。我们的实验结果表明,我们的技术显著减少了SMT求解器回答几个基准库的“不满意”问题所需的实例化数量,从而导致了对最先进实现的改进。
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引用次数: 70
A program transformation for faster goal-directed search 一个程序转换为更快的目标导向搜索
Pub Date : 2014-10-21 DOI: 10.1109/FMCAD.2014.6987607
A. Lal, S. Qadeer
A goal-directed search attempts to reveal only relevant information needed to establish reachability (or unreachability) of the goal from the initial state of the program. The further apart the goal is from the initial state, the harder it can get to establish what is relevant. This paper addresses this concern in the context of programs with assertions that may be nested deeply inside its call graph - thus, far away interprocedurally from main. We present a source-to-source transformation on programs that lifts all assertions in the input program to the entry procedure of the output program, thus, revealing more information about the assertions close to the entry of the program. The transformation is easy to implement and applies to sequential as well as concurrent programs. We empirically validate using multiple goal-directed verifiers that applying this transformation before invoking the verifier results in significant speedups, sometimes up to an order of magnitude.
目标导向搜索试图从程序的初始状态只显示建立目标可达性(或不可达性)所需的相关信息。目标离初始状态越远,就越难确定什么是相关的。本文在程序的上下文中解决了这个问题,这些程序的断言可能嵌套在其调用图中——因此,在程序间远离main。我们提供了一个程序的源到源转换,该转换将输入程序中的所有断言提升到输出程序的入口过程,从而揭示了关于接近程序入口的断言的更多信息。这种转换很容易实现,既适用于顺序程序,也适用于并发程序。我们使用多个目标导向的验证器进行经验验证,在调用验证器之前应用此转换会导致显著的加速,有时达到数量级。
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引用次数: 13
Efficient verification of periodic programs using sequential consistency and snapshots 使用顺序一致性和快照对周期性程序进行有效验证
Pub Date : 2014-10-21 DOI: 10.1109/FMCAD.2014.6987595
S. Chaki, A. Gurfinkel, Nishant Sinha
We verify safety properties of periodic programs, consisting of periodically activated threads scheduled preemptively based on their priorities. We develop an approach based on generating, and solving, a provably correct verification condition (VC). The VC is generated by adapting Lamport's sequential consistency to the semantics of periodic programs. Our approach is able to handle periodic programs that synchronize via two commonly used types of locks - priority ceiling protocol (PCP) locks, and CPU locks. To improve the scalability of our approach, we develop a strategy called snapshotting, which leads to VCs containing fewer redundant sub-formulas, and are therefore more easily solved by current SMT engines. We develop two types of snapshotting - SS-ALL snapshots all shared variables aggressively, while SS-MOD snapshots only modified variables. We have implemented our approach in a tool. Experiments on a benchmark of robot controllers indicate that SS-MOD is the best overall strategy, and even outperforms significantly the state-of-the art periodic program verifier prior to this work.
我们验证了周期性程序的安全特性,周期性程序由基于优先级调度的周期性激活线程组成。我们开发了一种基于生成和求解可证明正确的验证条件(VC)的方法。VC是通过将Lamport的顺序一致性应用于周期规划的语义而生成的。我们的方法能够处理通过两种常用的锁类型进行同步的周期性程序——优先级上限协议(PCP)锁和CPU锁。为了提高我们方法的可扩展性,我们开发了一种称为快照的策略,它导致vc包含更少的冗余子公式,因此更容易被当前的SMT引擎解决。我们开发了两种类型的快照- SS-ALL快照所有共享变量积极,而SS-MOD快照只修改变量。我们已经在一个工具中实现了我们的方法。在机器人控制器基准上的实验表明,SS-MOD是最佳的整体策略,甚至在此工作之前显著优于最先进的定期程序验证器。
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引用次数: 4
A tour of CVC4: How it works, and how to use it CVC4之旅:它是如何工作的,以及如何使用它
Pub Date : 2014-10-21 DOI: 10.1109/FMCAD.2014.6987586
Morgan Deters, Andrew Reynolds, Tim King, Clark W. Barrett, C. Tinelli
CVC4 is a solver for Satisfiability Modulo Theories (SMT). This tutorial aims to give participants an overview of SMT, describe the main features of CVC4, and walk through in-depth examples using CVC4 to demonstrate how to solve real problems with an SMT solver. We will provide a detailed description of various aspects of CVC4's internals, including its architecture, its capacity for dealing with quantifiers, its finite model finder, and the linear arithmetic solver. We will show examples of software and hardware verification problems, and how they are encoded and handled by these features in CVC4. Participants are expected to have only a basic knowledge of what SMT is. This tutorial will give casual users a taste of encoding complex, real-world problems in SMT and effectively using CVC4 to solve them. Participants will be left with some knowledge of what goes on inside a modern SMT solver and some of the practical issues that arise in using them. CVC4, jointly developed at New York University and the University of Iowa, is freely available for both research and commercial use under an open-source license. The organizers of this tutorial are all architects and implementors of CVC4 and have extensive expertise in the area of SMT.
CVC4是可满足模理论(SMT)的求解器。本教程旨在为参与者提供SMT的概述,描述CVC4的主要功能,并通过使用CVC4的深入示例来演示如何使用SMT求解器解决实际问题。我们将详细描述CVC4内部的各个方面,包括它的体系结构、处理量词的能力、有限模型查找器和线性算法求解器。我们将展示软件和硬件验证问题的示例,以及如何在CVC4中对这些特性进行编码和处理。参与者只需要对SMT有一个基本的了解。本教程将让普通用户体验在SMT中编码复杂的现实问题,并有效地使用CVC4来解决这些问题。参与者将了解现代SMT求解器内部发生的事情以及在使用它们时出现的一些实际问题。CVC4由纽约大学和爱荷华大学联合开发,在开源许可下可免费用于研究和商业用途。本教程的组织者都是CVC4的架构师和实现者,并且在SMT领域拥有丰富的专业知识。
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引用次数: 41
Efficient extraction of Skolem functions from QRAT proofs 从QRAT证明中高效提取Skolem函数
Pub Date : 2014-10-21 DOI: 10.1109/FMCAD.2014.6987602
Marijn J. H. Heule, M. Seidl, Armin Biere
Many synthesis problems can be solved by formulating them as a quantified Boolean formula (QBF). For such problems, a mere true/false answer is often not enough. Instead, expressing the answer in terms of Skolem functions reflecting the quantifier dependencies of the variables is required. Several approaches have been presented to extract such functions from term-resolution proofs. However, not all solvers and preprocessors are able to produce term-resolution proofs, especially when universal expansion is involved. In previous work, we developed the QRAT proof system consisting of three simple rules which allowed us to overcome this issue and to equip modern expansion-based tools like the preprocessor bloqqer with proof tracing. In this paper, we show how to extract Skolem functions from QRAT proofs. We present a general extraction tool and compare its performance to similar resolution-based tools. We show that the Skolem functions extracted from QRAT proofs are smaller than those produced by alternative approaches making our method in particular useful for synthesis applications.
许多综合问题可以用量化布尔公式(QBF)来解决。对于这样的问题,仅仅给出对/错的答案往往是不够的。相反,需要用反映变量的量词依赖关系的Skolem函数来表示答案。已经提出了几种从项分辨证明中提取此类函数的方法。然而,并不是所有的解算器和预处理器都能够产生term-resolution证明,特别是当涉及到通用展开时。在之前的工作中,我们开发了由三个简单规则组成的QRAT证明系统,这使我们能够克服这个问题,并为基于扩展的现代工具(如预处理器bloqqer)配备证明跟踪。在本文中,我们展示了如何从QRAT证明中提取Skolem函数。我们提出了一种通用的提取工具,并将其性能与类似的基于分辨率的工具进行了比较。我们表明,从QRAT证明中提取的Skolem函数比其他方法产生的函数要小,这使得我们的方法对合成应用特别有用。
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引用次数: 42
Template-based circuit understanding 基于模板的电路理解
Pub Date : 2014-10-21 DOI: 10.1109/FMCAD.2014.6987599
Adrià Gascón, Pramod Subramanyan, B. Dutertre, A. Tiwari, Dejan Jovanovic, S. Malik
When verifying or reverse-engineering digital circuits, one often wants to identify and understand small components in a larger system. A possible approach is to show that the sub-circuit under investigation is functionally equivalent to a reference implementation. In many cases, this task is difficult as one may not have full information about the mapping between input and output of the two circuits, or because the equivalence depends on settings of control inputs. We propose a template-based approach that automates this process. It extracts a functional description for a low-level combinational circuit by showing it to be equivalent to a reference implementation, while synthesizing an appropriate mapping of input and output signals and setting of control signals. The method relies on solving an exists/forall problem using an SMT solver, and on a pruning technique based on signature computation.
当验证或逆向工程数字电路时,人们通常希望识别和理解较大系统中的小组件。一种可能的方法是表明所研究的子电路在功能上等同于参考实现。在许多情况下,这项任务很困难,因为人们可能没有关于两个电路的输入和输出之间映射的完整信息,或者因为等效性取决于控制输入的设置。我们提出一种基于模板的方法来自动化这个过程。它通过表示低级组合电路相当于参考实现来提取其功能描述,同时合成适当的输入输出信号映射和控制信号设置。该方法依赖于使用SMT求解器解决存在/所有问题,以及基于签名计算的修剪技术。
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引用次数: 46
Kuai: A model checker for software-defined networks 快:软件定义网络的模型检查器
Pub Date : 2014-10-21 DOI: 10.1109/FMCAD.2014.6987609
R. Majumdar, S. Tetali, Zilong Wang
In software-defined networking (SDN), a software controller manages a distributed collection of switches by installing and uninstalling packet-forwarding rules in the switches. SDNs allow flexible implementations for expressive and sophisticated network management policies. We consider the problem of verifying that an SDN satisfies a given safety property. We describe Kuai, a distributed enumerative model checker for SDNs. Kuai takes as input a controller implementation written in Murphi, a description of the network topology (switches and connections), and a safety property, and performs a distributed enumerative reachability analysis on a cluster of machines. Kuai uses a set of partial order reduction techniques specific to the SDN domain that help reduce the state space dramatically. In addition, Kuai performs an automatic abstraction to handle unboundedly many packets traversing the network at a given time and unboundedly many control messages between the controller and the switches. We demonstrate the scalability and coverage of Kuai on standard SDN benchmarks. We show that our set of partial order reduction techniques significantly reduces the state spaces of these benchmarks by many orders of magnitude. In addition, Kuai exploits large-scale distribution to quickly search the reduced state space.
在SDN (software-defined networking)中,软件控制器通过在交换机中安装和卸载包转发规则来管理分布式交换机集合。sdn允许灵活地实现表达性和复杂的网络管理策略。我们考虑验证SDN是否满足给定的安全属性的问题。我们描述了Kuai,一个用于sdn的分布式枚举模型检查器。Kuai将用Murphi编写的控制器实现、网络拓扑(交换机和连接)描述和安全属性作为输入,并在机器集群上执行分布式枚举可达性分析。Kuai使用了一组特定于SDN域的偏序约简技术,可以帮助显著减少状态空间。此外,Kuai执行自动抽象来处理在给定时间内穿越网络的无限多的数据包,以及控制器和交换机之间的无限多的控制消息。我们在标准SDN基准上演示了Kuai的可扩展性和覆盖范围。我们表明,我们的偏序约简技术集显著地将这些基准的状态空间降低了许多数量级。此外,Kuai利用大规模分布来快速搜索约简状态空间。
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引用次数: 54
Reducing CTL-live model checking to first-order logic validity checking 将CTL-live模型检查简化为一阶逻辑有效性检查
Pub Date : 2014-10-21 DOI: 10.1109/FMCAD.2014.6987616
Amirhossein Vakili, N. Day
Temporal logic model checking of infinite state systems without the use of iteration or abstraction is usually considered beyond the realm of first-order logic (FOL) reasoners because of the need for a fixpoint computation. In this paper, we show that it is possible to reduce model checking of a finite or infinite Kripke structure that is expressed in FOL to a validity problem in FOL for a fragment of computational tree logic (CTL), which we call CTL-live. CTL-live includes the CTL connectives that are traditionally used to express liveness properties. Our reduction can form the basis for methods that use FOL reasoning techniques directly to accomplish model checking of CTL-live properties without the need for fixpoint operators, transitive closure, abstraction, or induction.
无限状态系统的时间逻辑模型检查不使用迭代或抽象,通常被认为超出了一阶逻辑推理的范畴,因为需要不动点计算。在本文中,我们证明有可能将有限或无限Kripke结构的模型检验简化为计算树逻辑片段(CTL)的有效性问题,我们称之为CTL-live。CTL-live包括传统上用于表达活性属性的CTL连接词。我们的简化可以构成直接使用FOL推理技术来完成ctl活动属性的模型检查的方法的基础,而不需要固定点操作符、传递闭包、抽象或归纳。
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引用次数: 9
期刊
2014 Formal Methods in Computer-Aided Design (FMCAD)
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