Pub Date : 2011-06-05DOI: 10.1109/SASP.2011.5941072
Liang Chen, Nicolas Boichat, T. Mitra
Multiprocessor System-on-Chip (MPSoC) platforms have become increasingly popular for high-performance embedded applications. Each processing element (PE) on such platforms can be tuned to match the computational demands of the tasks executing on it, creating a heterogeneous multiprocessor system. Extensible processor cores, where the base instruction-set architecture can be augmented with application-specific custom instructions, have recently emerged as flexible building blocks for heterogeneous MPSoC platforms. However, the customization of the different PEs has to be carried out in a synergistic manner so as to create an optimal system. In this work, we propose a pseudo-polynomial time algorithm to design the most resource-efficient customized MPSoC platform for mapping linear task graphs representing streaming applications, under deadline constraints. Experimental validation with MP3 encoder and MPEG-2 encoder applications confirms the efficiency of our approach.
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Pub Date : 2011-06-01DOI: 10.1109/SASP.2011.5941087
T. Aa, M. Palkovic, Matthias Hartmann, P. Raghavan, A. Dejonghe, L. Perre
Throughput of wireless communication standards ever increases. Computation requirements for systems implementing those standards increase even more. On battery operated devices, next to high performance a low power implementation is also crucial. Reaching this is only possible by utilizing parallelizations at all levels. The ADRES processor is an embedded coarse-grained reconfigurable baseband processor that already could exploit Data Level Parallelism (DLP), Instruction Level Parallelism (ILP) efficiently. In this paper we present extensions to ADRES to also exploit Task Level Parallelism (TLP) efficiently. We show how we reduce the overhead in communication and synchronization between tasks and demonstrate this on a mapping of an 802.11n 300Mbps standard.
{"title":"A multi-threaded coarse-grained array processor for wireless baseband","authors":"T. Aa, M. Palkovic, Matthias Hartmann, P. Raghavan, A. Dejonghe, L. Perre","doi":"10.1109/SASP.2011.5941087","DOIUrl":"https://doi.org/10.1109/SASP.2011.5941087","url":null,"abstract":"Throughput of wireless communication standards ever increases. Computation requirements for systems implementing those standards increase even more. On battery operated devices, next to high performance a low power implementation is also crucial. Reaching this is only possible by utilizing parallelizations at all levels. The ADRES processor is an embedded coarse-grained reconfigurable baseband processor that already could exploit Data Level Parallelism (DLP), Instruction Level Parallelism (ILP) efficiently. In this paper we present extensions to ADRES to also exploit Task Level Parallelism (TLP) efficiently. We show how we reduce the overhead in communication and synchronization between tasks and demonstrate this on a mapping of an 802.11n 300Mbps standard.","PeriodicalId":375788,"journal":{"name":"2011 IEEE 9th Symposium on Application Specific Processors (SASP)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131379809","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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