Pub Date : 2015-07-16DOI: 10.1109/ECTC.2015.7159703
V. Sukumaran, T. Tran-Quinn, J. Lubguban, David Webster, Brittany Hedrick, H. Cox, J. Wood, H. Miyazoe, Hongwen Yan, E. Joseph, Hongqing Zhang, B. Backes, M. Chace, E. Perfecto, I. Melville, M. Angyal
Glass is widely used as a carrier substrate for processing thin silicon wafers for 3D applications. Moreover, the use of glass as an interposer material has recently attracted significant attention in both research and development. For silicon interposer applications, the silicon wafer with through silicon vias (TSVs) is first bonded to a temporary glass handler and subsequently subjected to wafer thinning to reveal the TSVs. After TSV reveal, wiring layers are patterned on the `grind-side' using photoresist, with sputtered TiW/Cu as the metal seed-layer and SiNx as the dielectric separating the metal layers. This paper reports a new `resistdependent' delamination phenomenon that occurs at the interface between TiW/Cu and SiNx surfaces, which is triggered during the plasma process. The delamination manifests as small blisters of raised TiW/Cu over the SiNx surface, and was observed while using glass wafers, either as a handler or as the actual electronic substrate. In this study, the root cause of delamination is identified as the Ar plasma used for clamping the wafers. The defect intensity is minimized by lowering the power of Ar plasma. Finally, defects are completely mitigated by substituting O2 gas in place of Ar during plasma processing.
{"title":"Defect mitigation of plasma-induced delamination of TiW/Cu from SiNx layer in thin si interposer processing with glass carriers","authors":"V. Sukumaran, T. Tran-Quinn, J. Lubguban, David Webster, Brittany Hedrick, H. Cox, J. Wood, H. Miyazoe, Hongwen Yan, E. Joseph, Hongqing Zhang, B. Backes, M. Chace, E. Perfecto, I. Melville, M. Angyal","doi":"10.1109/ECTC.2015.7159703","DOIUrl":"https://doi.org/10.1109/ECTC.2015.7159703","url":null,"abstract":"Glass is widely used as a carrier substrate for processing thin silicon wafers for 3D applications. Moreover, the use of glass as an interposer material has recently attracted significant attention in both research and development. For silicon interposer applications, the silicon wafer with through silicon vias (TSVs) is first bonded to a temporary glass handler and subsequently subjected to wafer thinning to reveal the TSVs. After TSV reveal, wiring layers are patterned on the `grind-side' using photoresist, with sputtered TiW/Cu as the metal seed-layer and SiNx as the dielectric separating the metal layers. This paper reports a new `resistdependent' delamination phenomenon that occurs at the interface between TiW/Cu and SiNx surfaces, which is triggered during the plasma process. The delamination manifests as small blisters of raised TiW/Cu over the SiNx surface, and was observed while using glass wafers, either as a handler or as the actual electronic substrate. In this study, the root cause of delamination is identified as the Ar plasma used for clamping the wafers. The defect intensity is minimized by lowering the power of Ar plasma. Finally, defects are completely mitigated by substituting O2 gas in place of Ar during plasma processing.","PeriodicalId":381358,"journal":{"name":"2015 IEEE 65th Electronic Components and Technology Conference (ECTC)","volume":"204 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123050268","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-07-16DOI: 10.1109/ECTC.2015.7159893
J. Meng, A. Dasgupta, M. Sillanpaa, E. Hussa, Timo Turkkila, Hong-xian Zhang, T. Salminen, V. Halkola
In this study, a novel side-impact test method is developed for shearing-off miniature electromechanical devices from the printed wiring boards (PWBs) of portable products. The test method is implemented by modifying a commercial IZOD pendulum impact test setup. The key modification is the replacement of the instrumented pendulum impactor with an instrumented “striker-bar” design. The pendulum instrumented with the “striker-bar” allows high impact velocity up to 3.54E+3 mm/s, and is specially designed for testing components with very low profile. In this study, this setup is used to test a miniaturized electromechanical devices, such as a micro-switch, whose low profile presents a significant challenge to repeatable side-impact testing. Both overstress impact tests and repetitive impact fatigue tests are conducted, to evaluate the interaction of the different parts of the entire electromechanical assembly, including the solder joints, pins, through-holes and housing of the package. Failure modes are documented and failure envelopes are developed by relating the measured durability to the impact parameters like impact velocity, fracture energy and force impulse.
{"title":"Side impact reliability of micro-switches","authors":"J. Meng, A. Dasgupta, M. Sillanpaa, E. Hussa, Timo Turkkila, Hong-xian Zhang, T. Salminen, V. Halkola","doi":"10.1109/ECTC.2015.7159893","DOIUrl":"https://doi.org/10.1109/ECTC.2015.7159893","url":null,"abstract":"In this study, a novel side-impact test method is developed for shearing-off miniature electromechanical devices from the printed wiring boards (PWBs) of portable products. The test method is implemented by modifying a commercial IZOD pendulum impact test setup. The key modification is the replacement of the instrumented pendulum impactor with an instrumented “striker-bar” design. The pendulum instrumented with the “striker-bar” allows high impact velocity up to 3.54E+3 mm/s, and is specially designed for testing components with very low profile. In this study, this setup is used to test a miniaturized electromechanical devices, such as a micro-switch, whose low profile presents a significant challenge to repeatable side-impact testing. Both overstress impact tests and repetitive impact fatigue tests are conducted, to evaluate the interaction of the different parts of the entire electromechanical assembly, including the solder joints, pins, through-holes and housing of the package. Failure modes are documented and failure envelopes are developed by relating the measured durability to the impact parameters like impact velocity, fracture energy and force impulse.","PeriodicalId":381358,"journal":{"name":"2015 IEEE 65th Electronic Components and Technology Conference (ECTC)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128542105","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-07-16DOI: 10.1109/ECTC.2015.7159718
X. Gu, Duixian Liu, C. Baks, B. Sadhu, A. Valdes-Garcia
This paper describes the demonstration of a millimeter-wave package for a fully-integrated switched-beam 60-GHz CMOS transceiver IC. The package supports differential transmit and single-ended receive paths in both broadside and end-fire directions with four integrated antennas. The multi-antenna configuration provides flexible link coverage with a small form factor suitable for portable communication devices. The 11mm × 11mm × 0.5mm package has 38 BGA pins and is built with low-cost printed circuit board technology using 4 metal layers and organic dielectric materials. Full-wave electromagnetic simulations were performed to verify antenna performance in the context of a full-package environment, including power/ground planes and signal wiring of the package and of the second-level PCB. System-level characterization results with a fully assembled transceiver module are presented, including measured antenna radiation patterns.
{"title":"A multilayer organic package with four integrated 60GHz antennas enabling broadside and end-fire radiation for portable communication devices","authors":"X. Gu, Duixian Liu, C. Baks, B. Sadhu, A. Valdes-Garcia","doi":"10.1109/ECTC.2015.7159718","DOIUrl":"https://doi.org/10.1109/ECTC.2015.7159718","url":null,"abstract":"This paper describes the demonstration of a millimeter-wave package for a fully-integrated switched-beam 60-GHz CMOS transceiver IC. The package supports differential transmit and single-ended receive paths in both broadside and end-fire directions with four integrated antennas. The multi-antenna configuration provides flexible link coverage with a small form factor suitable for portable communication devices. The 11mm × 11mm × 0.5mm package has 38 BGA pins and is built with low-cost printed circuit board technology using 4 metal layers and organic dielectric materials. Full-wave electromagnetic simulations were performed to verify antenna performance in the context of a full-package environment, including power/ground planes and signal wiring of the package and of the second-level PCB. System-level characterization results with a fully assembled transceiver module are presented, including measured antenna radiation patterns.","PeriodicalId":381358,"journal":{"name":"2015 IEEE 65th Electronic Components and Technology Conference (ECTC)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131677899","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-07-16DOI: 10.1109/ECTC.2015.7159901
Zhong Guan, M. Marek-Sadowska
In this paper, we develop an AC electromigration (EM) model for signal lines manufactured with copper dual damascene process. For the first time, the healing factor of AC EM is quantitatively modeled. To measure EM reliability of interconnects considering timing margins we introduce AC EM functional lifetime. We also develop an atomic flux divergence (AFD)-based void growth model to explain the resistance curves of measured results and calculate the functional EM lifetime of AC signal lines without extracting parameters from experiments. We demonstrate fidelity of the proposed model with measured results for both the healing factor and the rate of resistance change.
{"title":"Atomic flux divergence-based AC electromigration model for signal line reliability assessment","authors":"Zhong Guan, M. Marek-Sadowska","doi":"10.1109/ECTC.2015.7159901","DOIUrl":"https://doi.org/10.1109/ECTC.2015.7159901","url":null,"abstract":"In this paper, we develop an AC electromigration (EM) model for signal lines manufactured with copper dual damascene process. For the first time, the healing factor of AC EM is quantitatively modeled. To measure EM reliability of interconnects considering timing margins we introduce AC EM functional lifetime. We also develop an atomic flux divergence (AFD)-based void growth model to explain the resistance curves of measured results and calculate the functional EM lifetime of AC signal lines without extracting parameters from experiments. We demonstrate fidelity of the proposed model with measured results for both the healing factor and the rate of resistance change.","PeriodicalId":381358,"journal":{"name":"2015 IEEE 65th Electronic Components and Technology Conference (ECTC)","volume":"25 11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125767209","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-26DOI: 10.1109/ECTC.2015.7159759
Guangsen Chen, Fengshun Wu, Changqing Liu, Y. Chan
In this study, fullerene nanoparticles (FNSs, a mixture of approximately 80%C60, 20%C70), by varying their weight fractions (0.05, 0.1 and 0.2wt. %) were successfully added into the SAC305 lead free solder to fabricate composite solders through the powder metallurgy processing route. As well as the retained ratios of fullerene reinforcements in the solder joints were firstly tested, the composite solders were also characterized in terms of their microstructure, melting points, electrical conductivity, wettability and mechanical properties. The retained ratio of FNSs reinforcements in the solder joints shows a considerable decrease with the increase of reflow cycles. After FNSs addition to the solder alloy, the Sn rich phase and IMC phases (Cu6Sn5 and Ag3Sn) with a finer microstructure were observed in the solder matrix. With the increasing addition of fullerene, the composite solders showed an improvement in their wetting property but an insignificant change in their melting points and conductivity. The mechanical results indicated that the addition of 0.2wt. % fullerene can lead to 12.1% and 28.2% improvement in micro-hardness and shear strength respectively, when compared with that of the unreinforced solders. Furthermore, the FNSs doped composites exhibited better mechanical performance throughout the 360h aging period. These results obtained from this study proved that the addition of fullerene can improve not only the mechanical properties of the solder alloy, but also the wettability without any notable effect on the melting point and conductivity. Thus, these fullerene doped composite solders can be further developed as a potential material for microelectronics assembly and packaging industry.
{"title":"Effect of fullerene-C60&C70 on the microstructure and properties of 96.5Sn-3Ag-0.5Cu solder","authors":"Guangsen Chen, Fengshun Wu, Changqing Liu, Y. Chan","doi":"10.1109/ECTC.2015.7159759","DOIUrl":"https://doi.org/10.1109/ECTC.2015.7159759","url":null,"abstract":"In this study, fullerene nanoparticles (FNSs, a mixture of approximately 80%C60, 20%C70), by varying their weight fractions (0.05, 0.1 and 0.2wt. %) were successfully added into the SAC305 lead free solder to fabricate composite solders through the powder metallurgy processing route. As well as the retained ratios of fullerene reinforcements in the solder joints were firstly tested, the composite solders were also characterized in terms of their microstructure, melting points, electrical conductivity, wettability and mechanical properties. The retained ratio of FNSs reinforcements in the solder joints shows a considerable decrease with the increase of reflow cycles. After FNSs addition to the solder alloy, the Sn rich phase and IMC phases (Cu6Sn5 and Ag3Sn) with a finer microstructure were observed in the solder matrix. With the increasing addition of fullerene, the composite solders showed an improvement in their wetting property but an insignificant change in their melting points and conductivity. The mechanical results indicated that the addition of 0.2wt. % fullerene can lead to 12.1% and 28.2% improvement in micro-hardness and shear strength respectively, when compared with that of the unreinforced solders. Furthermore, the FNSs doped composites exhibited better mechanical performance throughout the 360h aging period. These results obtained from this study proved that the addition of fullerene can improve not only the mechanical properties of the solder alloy, but also the wettability without any notable effect on the melting point and conductivity. Thus, these fullerene doped composite solders can be further developed as a potential material for microelectronics assembly and packaging industry.","PeriodicalId":381358,"journal":{"name":"2015 IEEE 65th Electronic Components and Technology Conference (ECTC)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124242560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-26DOI: 10.1109/ECTC.2015.7159915
J. Xian, S. Belyakov, T. B. Britton, C. Gourlay
Cu6Sn5 is a common intermetallic in Pb-free soldering, and the volume fraction, size and shape of Cu6Sn5 particles in the bulk solder plays an important role in the reliability of solder joints. We have previously shown that Al additions can significantly reduce the size of primary Cu6Sn5 crystals in Sn-Cu-Al alloys, due to epitaxial nucleation of Cu6Sn5 on either Cu33Al17 or Cu9Al4 particles [1]. In this paper, we explore the extent to which dilute aluminium additions can control the size of large Cu6Sn5 hexagonal rods that can form during soldering of Sn-0.7Cu and Sn-3.0Ag-0.5Cu (SAC305) BGAs on Cu substrates. We find that Al additions cause significant grain refinement of primary Cu6Sn5 in all test samples. For example, a 0.05wt% Al addition in Sn-0.7Cu/Cu joints increased the number of primary Cu6Sn5 per mm2 by a factor of ~7 and decreased the mean 3D length of primary Cu6Sn5 rods by a factor of ~4. The average size of Cu6Sn5 rods also decreased significantly after adding 0.05wt%Al to SAC305/Cu joints. A Cu9Al4 or Cu33Al17 particle was found near the centre of many primary Cu6Sn5 rods and reproducible crystallographic orientation relationships (ORs) were measured by electron backscatter diffraction (EBSD). The grain refinement effect after adding Al is due to the heterogeneous nucleation of Cu6Sn5 on γ1-Cu9Al4 or δ-Cu33Al17 particles. The size of active nuclei was 2-5μm in Sn-4Cu-0.2Al solders, and <;1μm in Sn-0.7Cu-0.05Al/Cu and SAC305+0.05Al/Cu joints.
{"title":"Heterogeneous nucleation of bulk Cu6Sn5 in Sn-Ag-Cu-Al and Sn-Cu-Al solders","authors":"J. Xian, S. Belyakov, T. B. Britton, C. Gourlay","doi":"10.1109/ECTC.2015.7159915","DOIUrl":"https://doi.org/10.1109/ECTC.2015.7159915","url":null,"abstract":"Cu<sub>6</sub>Sn<sub>5</sub> is a common intermetallic in Pb-free soldering, and the volume fraction, size and shape of Cu<sub>6</sub>Sn<sub>5</sub> particles in the bulk solder plays an important role in the reliability of solder joints. We have previously shown that Al additions can significantly reduce the size of primary Cu<sub>6</sub>Sn<sub>5</sub> crystals in Sn-Cu-Al alloys, due to epitaxial nucleation of Cu<sub>6</sub>Sn<sub>5</sub> on either Cu<sub>33</sub>Al<sub>17</sub> or Cu<sub>9</sub>Al<sub>4</sub> particles [1]. In this paper, we explore the extent to which dilute aluminium additions can control the size of large Cu<sub>6</sub>Sn<sub>5</sub> hexagonal rods that can form during soldering of Sn-0.7Cu and Sn-3.0Ag-0.5Cu (SAC305) BGAs on Cu substrates. We find that Al additions cause significant grain refinement of primary Cu<sub>6</sub>Sn<sub>5</sub> in all test samples. For example, a 0.05wt% Al addition in Sn-0.7Cu/Cu joints increased the number of primary Cu<sub>6</sub>Sn<sub>5</sub> per mm<sup>2</sup> by a factor of ~7 and decreased the mean 3D length of primary Cu<sub>6</sub>Sn<sub>5</sub> rods by a factor of ~4. The average size of Cu<sub>6</sub>Sn<sub>5</sub> rods also decreased significantly after adding 0.05wt%Al to SAC305/Cu joints. A Cu<sub>9</sub>Al<sub>4</sub> or Cu<sub>33</sub>Al<sub>17</sub> particle was found near the centre of many primary Cu<sub>6</sub>Sn<sub>5</sub> rods and reproducible crystallographic orientation relationships (ORs) were measured by electron backscatter diffraction (EBSD). The grain refinement effect after adding Al is due to the heterogeneous nucleation of Cu<sub>6</sub>Sn<sub>5</sub> on γ<sub>1</sub>-Cu<sub>9</sub>Al<sub>4</sub> or δ-Cu<sub>33</sub>Al<sub>17</sub> particles. The size of active nuclei was 2-5μm in Sn-4Cu-0.2Al solders, and <;1μm in Sn-0.7Cu-0.05Al/Cu and SAC305+0.05Al/Cu joints.","PeriodicalId":381358,"journal":{"name":"2015 IEEE 65th Electronic Components and Technology Conference (ECTC)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124281440","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-26DOI: 10.1109/ECTC.2015.7159599
M. Ghazali, Eleazar Gutierrez, J. Myers, A. Kaur, Brian Wright, P. Chahal
In this paper, a variety of 3D printed microwave antennas are presented including wide band, narrow band, multiband and reconfigurable designs. In particular, single layer patch, folded E-patch, a bilateral Vivaldi, Spartan logo and Lego-like assembled antennas are demonstrated. 3D printing provides significant flexibility in the design of antennas that combine the assembly of both dielectric and metal layers to achieve desired performance characteristics such as resonant frequency and radiation pattern. Also, small Lego-like blocks can be printed that allows in the design and assembly of novel antennas structures using a combination of dielectric and metal coated blocks.
{"title":"Affordable 3D printed microwave antennas","authors":"M. Ghazali, Eleazar Gutierrez, J. Myers, A. Kaur, Brian Wright, P. Chahal","doi":"10.1109/ECTC.2015.7159599","DOIUrl":"https://doi.org/10.1109/ECTC.2015.7159599","url":null,"abstract":"In this paper, a variety of 3D printed microwave antennas are presented including wide band, narrow band, multiband and reconfigurable designs. In particular, single layer patch, folded E-patch, a bilateral Vivaldi, Spartan logo and Lego-like assembled antennas are demonstrated. 3D printing provides significant flexibility in the design of antennas that combine the assembly of both dielectric and metal layers to achieve desired performance characteristics such as resonant frequency and radiation pattern. Also, small Lego-like blocks can be printed that allows in the design and assembly of novel antennas structures using a combination of dielectric and metal coated blocks.","PeriodicalId":381358,"journal":{"name":"2015 IEEE 65th Electronic Components and Technology Conference (ECTC)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121215628","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-26DOI: 10.1109/ECTC.2015.7159841
F. Su, Tianbao Lan, X. Pan, Zheng Zhang
The through-Silicon-Vias (TSV) is a key component of three dimensional electronic packaging, knowing its stresses is very important for its reliability evaluation. In this paper, we evaluated the stress of TSV during thermal cycling with a micro-infrared photoelasticity system in full field and real time measurement mode, three important findings are reported. First, it was found that electroplating was a source of residual stress of TSV, and although annealing was helpful to release the chemical stress, it may cause thermal stress as well; Second, TSV obtained and kept its stress-free state as temperature is above 180-200° C; Third, with the increase of thermal cycling, residual stress of TSV tended to increase as well but got stabled when the number of thermal cycling is high enough. Besides, this paper reports experimental evidence of interfacial sliding between Cu and Si in Cu-filled TSVs during thermal loading/cycling, which be used to illustrate the above findings.
{"title":"Development and application of a micro-infrared photoelasticity system for stress evaluation of through-silicon Vias (TSV)","authors":"F. Su, Tianbao Lan, X. Pan, Zheng Zhang","doi":"10.1109/ECTC.2015.7159841","DOIUrl":"https://doi.org/10.1109/ECTC.2015.7159841","url":null,"abstract":"The through-Silicon-Vias (TSV) is a key component of three dimensional electronic packaging, knowing its stresses is very important for its reliability evaluation. In this paper, we evaluated the stress of TSV during thermal cycling with a micro-infrared photoelasticity system in full field and real time measurement mode, three important findings are reported. First, it was found that electroplating was a source of residual stress of TSV, and although annealing was helpful to release the chemical stress, it may cause thermal stress as well; Second, TSV obtained and kept its stress-free state as temperature is above 180-200° C; Third, with the increase of thermal cycling, residual stress of TSV tended to increase as well but got stabled when the number of thermal cycling is high enough. Besides, this paper reports experimental evidence of interfacial sliding between Cu and Si in Cu-filled TSVs during thermal loading/cycling, which be used to illustrate the above findings.","PeriodicalId":381358,"journal":{"name":"2015 IEEE 65th Electronic Components and Technology Conference (ECTC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125853403","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-26DOI: 10.1109/ECTC.2015.7159909
A. Panigrahi, Satish Bonam, Tamal Ghosh, S. Vanjari, S. Singh
In this paper, we report the methodology of achieving low temperature, low pressure CMOS compatible Wafer-on-Wafer (WoW) Cu-Cu thermo-compression bonding using optimally chosen ultra-thin layer of Titanium (Ti) as a passivation layer. We systematically studied the effects of Ti thickness on bonding quality via its effects on surface roughness, oxidation prevention and inter diffusion of Cu. Through this study, we have found that a Ti thickness of 3 nm not only results in excellent bonding but also leads to a reduction in operating pressure to 2.5 bar and temperature to 175° C. The reduction in pressure is more than an order of magnitude lower relative to the current state-of-the-art. The lower operating pressure and temperature manifest themselves in a very good homogenous bond further highlighting the efficacy of our approach. Finally, our results have been corroborated by evidence from AFM study of the Cu/Ti surface prior to bonding. The bond strength of Cu-Cu as measured by Instron Microtester measurement system is found to be 190 MPa which compares very well with the reported literatures.
{"title":"Low temperature, low pressure CMOS compatible Cu -Cu thermo-compression bonding with Ti passivation for 3D IC integration","authors":"A. Panigrahi, Satish Bonam, Tamal Ghosh, S. Vanjari, S. Singh","doi":"10.1109/ECTC.2015.7159909","DOIUrl":"https://doi.org/10.1109/ECTC.2015.7159909","url":null,"abstract":"In this paper, we report the methodology of achieving low temperature, low pressure CMOS compatible Wafer-on-Wafer (WoW) Cu-Cu thermo-compression bonding using optimally chosen ultra-thin layer of Titanium (Ti) as a passivation layer. We systematically studied the effects of Ti thickness on bonding quality via its effects on surface roughness, oxidation prevention and inter diffusion of Cu. Through this study, we have found that a Ti thickness of 3 nm not only results in excellent bonding but also leads to a reduction in operating pressure to 2.5 bar and temperature to 175° C. The reduction in pressure is more than an order of magnitude lower relative to the current state-of-the-art. The lower operating pressure and temperature manifest themselves in a very good homogenous bond further highlighting the efficacy of our approach. Finally, our results have been corroborated by evidence from AFM study of the Cu/Ti surface prior to bonding. The bond strength of Cu-Cu as measured by Instron Microtester measurement system is found to be 190 MPa which compares very well with the reported literatures.","PeriodicalId":381358,"journal":{"name":"2015 IEEE 65th Electronic Components and Technology Conference (ECTC)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125946466","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-26DOI: 10.1109/ECTC.2015.7159677
S. Moon, Jinho Kim, Jihyun Lee, Taeyong Kim, Kyongho Kim
Inside an electronic product with high-speed interfaces, a lot of technological effort is required for neutralizing mutual electromagnetic interference (EMI) between adjacent electronic components. Thus, it is necessary to adopt an EMI-aware design to maintain high-performance features by avoiding possible EMI causes in a large-scale integration (LSI) chip. In this work, we analyzed IC-level EMI causes for improving on-chip EMI perspectives by characterizing composing channel impedance with a view to the whole system. A test channel for characterizing system-level impedance properties consists of power/ground nets of on-chip metal layers, a chip-on film (CoF), and a printed circuit board (PCB). Specifically, we compared two test samples with different features. One (sample 1) has a 0.8nF on-chip decoupling capacitor, only horizontal Vdd-Vss pairing layout for power interconnects, and 0.2T clock shift scheme from data edge position. The other (sample 2) has a 1.5nF on-chip decoupling capacitor, both vertical and horizontal Vdd-Vss pairing layout for confining an EM field, and 0.5T clock shift scheme for frequency spreading effect. Using simulation results and frequency domain analysis, the impedance was found to be 1.3 Ohm to 0.9 Ohm at a specific noise frequency of interest (132MHz) as the decoupling capacitance increases from 0.8 nF to 1.5nF. In comparison, the performance of EMI properties in sample 2 was found to be improved by 6.0dB when compared to sample1. Specifically, this improvement turned out to be affected by 3.2dB due to increasing on-chip decoupling capacitance of 0.7dB due to a shielding effect on the power/ground interconnect layout of an added metal layer and 1.6dB due to changing the scheme of a clock timing transition. In the simulation-based estimation, this 5.5dB improvement was demonstrated to agree with the near-field measurement with a 6.0dB improvement. Consequently, our approach to analyze on-chip EMI effects is helpful to understand complex electromagnetic behaviors in an LSI chip and it is also expected to be applicable in suppressing complex EMI causes for leveraging on-chip EMI performance.
{"title":"An accurate on-chip design estimation for mitigating EMI effects in a large-scale integration chip","authors":"S. Moon, Jinho Kim, Jihyun Lee, Taeyong Kim, Kyongho Kim","doi":"10.1109/ECTC.2015.7159677","DOIUrl":"https://doi.org/10.1109/ECTC.2015.7159677","url":null,"abstract":"Inside an electronic product with high-speed interfaces, a lot of technological effort is required for neutralizing mutual electromagnetic interference (EMI) between adjacent electronic components. Thus, it is necessary to adopt an EMI-aware design to maintain high-performance features by avoiding possible EMI causes in a large-scale integration (LSI) chip. In this work, we analyzed IC-level EMI causes for improving on-chip EMI perspectives by characterizing composing channel impedance with a view to the whole system. A test channel for characterizing system-level impedance properties consists of power/ground nets of on-chip metal layers, a chip-on film (CoF), and a printed circuit board (PCB). Specifically, we compared two test samples with different features. One (sample 1) has a 0.8nF on-chip decoupling capacitor, only horizontal Vdd-Vss pairing layout for power interconnects, and 0.2T clock shift scheme from data edge position. The other (sample 2) has a 1.5nF on-chip decoupling capacitor, both vertical and horizontal Vdd-Vss pairing layout for confining an EM field, and 0.5T clock shift scheme for frequency spreading effect. Using simulation results and frequency domain analysis, the impedance was found to be 1.3 Ohm to 0.9 Ohm at a specific noise frequency of interest (132MHz) as the decoupling capacitance increases from 0.8 nF to 1.5nF. In comparison, the performance of EMI properties in sample 2 was found to be improved by 6.0dB when compared to sample1. Specifically, this improvement turned out to be affected by 3.2dB due to increasing on-chip decoupling capacitance of 0.7dB due to a shielding effect on the power/ground interconnect layout of an added metal layer and 1.6dB due to changing the scheme of a clock timing transition. In the simulation-based estimation, this 5.5dB improvement was demonstrated to agree with the near-field measurement with a 6.0dB improvement. Consequently, our approach to analyze on-chip EMI effects is helpful to understand complex electromagnetic behaviors in an LSI chip and it is also expected to be applicable in suppressing complex EMI causes for leveraging on-chip EMI performance.","PeriodicalId":381358,"journal":{"name":"2015 IEEE 65th Electronic Components and Technology Conference (ECTC)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126129952","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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