Pub Date : 2014-11-01DOI: 10.1109/ISOCC.2014.7087640
Huyen Pham Thi, S. Ajaz, Hanho Lee
This paper presents an novel modified Min-Max algorithm (MMMA) and an efficient implementation of an nonbinary LDPC (NB-LDPC) decoder on a graphics processing unit (GPU) to achieve both great flexibility and scalability. The MMMA for check node processing removes the multiplications over Galois-field in merger step and significantly reduces the decoding latency. The proposed MMMA provides a better BER performance than previous algorithm. The experimental results show that the GPU-based implementation of the proposed NB-LDPC decoder provides higher throughput and the coding gain under low 10-8 BER comparted to CPU-based implementation.
{"title":"Efficient Min-Max nonbinary LDPC decoding on GPU","authors":"Huyen Pham Thi, S. Ajaz, Hanho Lee","doi":"10.1109/ISOCC.2014.7087640","DOIUrl":"https://doi.org/10.1109/ISOCC.2014.7087640","url":null,"abstract":"This paper presents an novel modified Min-Max algorithm (MMMA) and an efficient implementation of an nonbinary LDPC (NB-LDPC) decoder on a graphics processing unit (GPU) to achieve both great flexibility and scalability. The MMMA for check node processing removes the multiplications over Galois-field in merger step and significantly reduces the decoding latency. The proposed MMMA provides a better BER performance than previous algorithm. The experimental results show that the GPU-based implementation of the proposed NB-LDPC decoder provides higher throughput and the coding gain under low 10-8 BER comparted to CPU-based implementation.","PeriodicalId":381891,"journal":{"name":"2014 International SoC Design Conference (ISOCC)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121236466","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-01DOI: 10.1109/ISOCC.2014.7087669
C. Gong, Chi-Tong Hung, Wei-Lin William Chu, Chang-Jie Lin, Yu-Fan Luo, C. Chien, Y. Kuo, Meng-Jung Chang, Chin-Chih Hsu
Among the reviews and discussions demonstrated in the literature, very little attention was paid to which logic style is the most for adiabatic and subthreshold techniques. This study tries to make up such a deficiency, with particular emphasis on two representative circuit structures. All the comparisons were based on 0.18-μm standard CMOS process.
{"title":"Comparison of subthreshold logic with adiabatic circuit techniques","authors":"C. Gong, Chi-Tong Hung, Wei-Lin William Chu, Chang-Jie Lin, Yu-Fan Luo, C. Chien, Y. Kuo, Meng-Jung Chang, Chin-Chih Hsu","doi":"10.1109/ISOCC.2014.7087669","DOIUrl":"https://doi.org/10.1109/ISOCC.2014.7087669","url":null,"abstract":"Among the reviews and discussions demonstrated in the literature, very little attention was paid to which logic style is the most for adiabatic and subthreshold techniques. This study tries to make up such a deficiency, with particular emphasis on two representative circuit structures. All the comparisons were based on 0.18-μm standard CMOS process.","PeriodicalId":381891,"journal":{"name":"2014 International SoC Design Conference (ISOCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128769840","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-01DOI: 10.1109/ISOCC.2014.7087562
Hyunmin Kim, Seokhie Hong
As the usage of PUFs such as in digital fingerprinting is growing dramatically, we've developed a new PUF based on an AES Sbox GF(24) inversion functions that uses differences in power consumption at output nodes due to process variation. It has several advantages such as being able to improve the properties of a PUF and it requires little additional resources.
{"title":"AES Sbox GF(24) inversion functions based PUFs","authors":"Hyunmin Kim, Seokhie Hong","doi":"10.1109/ISOCC.2014.7087562","DOIUrl":"https://doi.org/10.1109/ISOCC.2014.7087562","url":null,"abstract":"As the usage of PUFs such as in digital fingerprinting is growing dramatically, we've developed a new PUF based on an AES Sbox GF(24) inversion functions that uses differences in power consumption at output nodes due to process variation. It has several advantages such as being able to improve the properties of a PUF and it requires little additional resources.","PeriodicalId":381891,"journal":{"name":"2014 International SoC Design Conference (ISOCC)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129644819","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-01DOI: 10.1109/ISOCC.2014.7087546
H. Akita, T. Ito, K. Hayakawa, Nobuaki Matsudaira, Hirofumi Yamamoto, Chao Chen, S. Ohtsuka, S. Taguchi
This paper presents a fast lock data recovery, which can compensate pulse-width distortion of the data signal waveform caused by the optocoupler. The proposed technique exploits the nature that only the rising edges of the data have a fixed amount of time delay at the output of the optocoupler. This delay is cancelled out by a recursive digital calculation after the bit number estimation using the blind oversampling. An experimental prototype fabricated in an in-house 40-V 0.8-um SOI BCD automotive process compensates more than ±50% pulse-width distortion with only 10-bit training as a preamble pattern. It can be applied with an inaccurate CR oscillator with 0.17-UI (unit interval) peak-to-peak jitter and up to ±10% frequency offset between the transmitter and the receiver.
本文提出了一种快速锁定数据恢复方法，可以补偿光耦合器对数据信号波形造成的脉宽畸变。所提出的技术利用的性质，只有上升沿的数据有一个固定的时间延迟在光耦合器的输出。该延迟在盲过采样估计比特数后通过递归数字计算消除。在内部40 v 0.8 um SOI BCD汽车工艺中制作的实验原型仅用10位训练作为前置模式补偿了±50%以上的脉宽失真。它可以应用于一个不准确的CR振荡器，具有0.17-UI(单位间隔)峰对峰抖动和发射器和接收器之间高达±10%的频率偏移。
{"title":"A 10-bit fast lock data recovery compensating pulse-width distortion for isolated data communications","authors":"H. Akita, T. Ito, K. Hayakawa, Nobuaki Matsudaira, Hirofumi Yamamoto, Chao Chen, S. Ohtsuka, S. Taguchi","doi":"10.1109/ISOCC.2014.7087546","DOIUrl":"https://doi.org/10.1109/ISOCC.2014.7087546","url":null,"abstract":"This paper presents a fast lock data recovery, which can compensate pulse-width distortion of the data signal waveform caused by the optocoupler. The proposed technique exploits the nature that only the rising edges of the data have a fixed amount of time delay at the output of the optocoupler. This delay is cancelled out by a recursive digital calculation after the bit number estimation using the blind oversampling. An experimental prototype fabricated in an in-house 40-V 0.8-um SOI BCD automotive process compensates more than ±50% pulse-width distortion with only 10-bit training as a preamble pattern. It can be applied with an inaccurate CR oscillator with 0.17-UI (unit interval) peak-to-peak jitter and up to ±10% frequency offset between the transmitter and the receiver.","PeriodicalId":381891,"journal":{"name":"2014 International SoC Design Conference (ISOCC)","volume":"663 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123981222","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-01DOI: 10.1109/ISOCC.2014.7087634
Sukho Lee, Hyunmi Kim, Kyungjin Byun, N. Eum
H.265 (HEVC) is the latest joint video coding standard with ITU-T SG16 WP and ISO/IEC JTC1/SC29/WG11. Its coding efficiency is about two times compared to H.264. However the burden of coding unit (CU) mode decision with rate distortion optimization (RDO) is too costly to implement it with hardware. The key idea of this paper is a novel mode decision architecture to reduce the HW complexity of RDO that is the most effective on an encoder's performance without a noticeable PSNR loss. To shrink the size the Hypernova H.265 encoder uses simplified RDO blocks and shares the transform resources. Its operating clock frequency is 300MHz@60fps on FHD image and BD-BR increase is negligible at 6.02% on hardware aspect. The estimated gate count of its is around 1M.
{"title":"On FHD 300MHz@60fps, intra/inter CU mode decision hardware architecture for the Hypernova H.265 encoder","authors":"Sukho Lee, Hyunmi Kim, Kyungjin Byun, N. Eum","doi":"10.1109/ISOCC.2014.7087634","DOIUrl":"https://doi.org/10.1109/ISOCC.2014.7087634","url":null,"abstract":"H.265 (HEVC) is the latest joint video coding standard with ITU-T SG16 WP and ISO/IEC JTC1/SC29/WG11. Its coding efficiency is about two times compared to H.264. However the burden of coding unit (CU) mode decision with rate distortion optimization (RDO) is too costly to implement it with hardware. The key idea of this paper is a novel mode decision architecture to reduce the HW complexity of RDO that is the most effective on an encoder's performance without a noticeable PSNR loss. To shrink the size the Hypernova H.265 encoder uses simplified RDO blocks and shares the transform resources. Its operating clock frequency is 300MHz@60fps on FHD image and BD-BR increase is negligible at 6.02% on hardware aspect. The estimated gate count of its is around 1M.","PeriodicalId":381891,"journal":{"name":"2014 International SoC Design Conference (ISOCC)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121436908","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-01DOI: 10.1109/ISOCC.2014.7087604
Seungwon Kim, K. Han, Seokhyeong Kang, Youngmin Kim
Three dimensional (3D) integrated circuit (IC) technology has been proposed and used to reduce the delay among layers by shortening interconnection with TSVs. However, large power and ground TSV structures generate voltage noise and cause additional IR-drop in power delivery network (PDN). In this work, we investigate and analyze the voltage noise in multiple layers 3D IC stacking with PEEC-based on-chip PDN and frequency-dependent TSV models. Then we propose multi-paired on-chip PDN structure for reducing voltage noise in a 3D IC. Our proposed PDN architecture can achieve approximately maximum 19% IR-drop reduction. In addition, layer dependency of 3D IC between the conventional and the proposed PDN models is analyzed.
{"title":"Analysis and reduction of voltage noise of multi-layer 3D IC with PEEC-based PDN and frequency-dependent TSV models","authors":"Seungwon Kim, K. Han, Seokhyeong Kang, Youngmin Kim","doi":"10.1109/ISOCC.2014.7087604","DOIUrl":"https://doi.org/10.1109/ISOCC.2014.7087604","url":null,"abstract":"Three dimensional (3D) integrated circuit (IC) technology has been proposed and used to reduce the delay among layers by shortening interconnection with TSVs. However, large power and ground TSV structures generate voltage noise and cause additional IR-drop in power delivery network (PDN). In this work, we investigate and analyze the voltage noise in multiple layers 3D IC stacking with PEEC-based on-chip PDN and frequency-dependent TSV models. Then we propose multi-paired on-chip PDN structure for reducing voltage noise in a 3D IC. Our proposed PDN architecture can achieve approximately maximum 19% IR-drop reduction. In addition, layer dependency of 3D IC between the conventional and the proposed PDN models is analyzed.","PeriodicalId":381891,"journal":{"name":"2014 International SoC Design Conference (ISOCC)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126375443","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-01DOI: 10.1109/ISOCC.2014.7087646
Sanghyuk Kwon, Y. Son, Jung Ho Ahn
Continuous DRAM scaling exacerbates problems caused by faulty cells, which lead to lower yields and more frequent errors. In-DRAM ECC is regarded as one of the solutions to overcome these issues. The latest DDR4 SDRAM specification includes new features to further improve reliability, such as an ALERT_n pad, which can be used to report errors detected by a SECDED code in DRAM. This paper identifies the possibilities and challenges of implementing In-DRAM ECC on DDR4 SDRAM devices.
{"title":"Understanding DDR4 in pursuit of In-DRAM ECC","authors":"Sanghyuk Kwon, Y. Son, Jung Ho Ahn","doi":"10.1109/ISOCC.2014.7087646","DOIUrl":"https://doi.org/10.1109/ISOCC.2014.7087646","url":null,"abstract":"Continuous DRAM scaling exacerbates problems caused by faulty cells, which lead to lower yields and more frequent errors. In-DRAM ECC is regarded as one of the solutions to overcome these issues. The latest DDR4 SDRAM specification includes new features to further improve reliability, such as an ALERT_n pad, which can be used to report errors detected by a SECDED code in DRAM. This paper identifies the possibilities and challenges of implementing In-DRAM ECC on DDR4 SDRAM devices.","PeriodicalId":381891,"journal":{"name":"2014 International SoC Design Conference (ISOCC)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133206673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-01DOI: 10.1109/ISOCC.2014.7087672
M. Saberian, Zhaowei Cai, Jinhee Lee, N. Vasconcelos
The design of a fast and accurate pedestrian detector is considered. A system combining a fast cascaded pedestrian detector and a pedestrian validator is proposed. The detector first scans the image of interest and proposes a set of candidate bounding boxes. The pedestrian validator then decides if each proposed bounding box is consistent with a true pedestrian, based on scene context. Experiments show that the resulting system is faster and more accurate than current approaches to pedestrian detection.
{"title":"Using context to improve cascaded pedestrian detection","authors":"M. Saberian, Zhaowei Cai, Jinhee Lee, N. Vasconcelos","doi":"10.1109/ISOCC.2014.7087672","DOIUrl":"https://doi.org/10.1109/ISOCC.2014.7087672","url":null,"abstract":"The design of a fast and accurate pedestrian detector is considered. A system combining a fast cascaded pedestrian detector and a pedestrian validator is proposed. The detector first scans the image of interest and proposes a set of candidate bounding boxes. The pedestrian validator then decides if each proposed bounding box is consistent with a true pedestrian, based on scene context. Experiments show that the resulting system is faster and more accurate than current approaches to pedestrian detection.","PeriodicalId":381891,"journal":{"name":"2014 International SoC Design Conference (ISOCC)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123176971","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-01DOI: 10.1109/ISOCC.2014.7087585
Si Fu, Minjie Chen, Xutao Lee, T. Yoshihara
A novel high efficiency multi-channel LED using a soft self-commutating technique and load adaptive method is presented in this paper. Directly powered by a AC voltage, for a soft switching method, the proposed circuit can implement a higher efficiency as well as a lower total harmonic distortion (THD) and avoid some thorny problem such as EMI and EMC noise during hard commutations with self-commutating structure and adaptive load network. By utilizing the converter-free technique, this work can be fabricated into a BCDMOS process technology without using any inductors and capacitors. The proposed circuit is designed and simulated based on PSpice Model. The maximum output current and the efficiency for LED achieve 1.28A and 89.1% under 1KHz 220V/AC condition.
{"title":"A high efficiency multi-channel LED driver based on converter-free technique and load adaptive method","authors":"Si Fu, Minjie Chen, Xutao Lee, T. Yoshihara","doi":"10.1109/ISOCC.2014.7087585","DOIUrl":"https://doi.org/10.1109/ISOCC.2014.7087585","url":null,"abstract":"A novel high efficiency multi-channel LED using a soft self-commutating technique and load adaptive method is presented in this paper. Directly powered by a AC voltage, for a soft switching method, the proposed circuit can implement a higher efficiency as well as a lower total harmonic distortion (THD) and avoid some thorny problem such as EMI and EMC noise during hard commutations with self-commutating structure and adaptive load network. By utilizing the converter-free technique, this work can be fabricated into a BCDMOS process technology without using any inductors and capacitors. The proposed circuit is designed and simulated based on PSpice Model. The maximum output current and the efficiency for LED achieve 1.28A and 89.1% under 1KHz 220V/AC condition.","PeriodicalId":381891,"journal":{"name":"2014 International SoC Design Conference (ISOCC)","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115656838","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-01DOI: 10.1109/ISOCC.2014.7087635
Junwon Moon, Jaeseok Kim
In a high dynamic range (HDR) circumstance, it's hard to describe whole information of the scene as common sensor's dynamic range is not sufficient to cover whole range. In this paper, we describe hardware design which enables HDR multi exposure fusion technique pursuing to be processed on real-time, for high definition (HD) images at 60fps. The proposed design can operate with Virtex5 XC5VLX20T device.
{"title":"Real-time HDR multi exposure fusion hardware design","authors":"Junwon Moon, Jaeseok Kim","doi":"10.1109/ISOCC.2014.7087635","DOIUrl":"https://doi.org/10.1109/ISOCC.2014.7087635","url":null,"abstract":"In a high dynamic range (HDR) circumstance, it's hard to describe whole information of the scene as common sensor's dynamic range is not sufficient to cover whole range. In this paper, we describe hardware design which enables HDR multi exposure fusion technique pursuing to be processed on real-time, for high definition (HD) images at 60fps. The proposed design can operate with Virtex5 XC5VLX20T device.","PeriodicalId":381891,"journal":{"name":"2014 International SoC Design Conference (ISOCC)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115713633","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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