Pub Date : 2023-01-01DOI: 10.1504/ijhpsa.2023.10058380
Dheeraj Kumar Sharma N.A.
{"title":"Analysis of Area and Energy Efficiency in Fruit-v2, Fruit-80, Grain128AEAD for resource constrained devices","authors":"Dheeraj Kumar Sharma N.A.","doi":"10.1504/ijhpsa.2023.10058380","DOIUrl":"https://doi.org/10.1504/ijhpsa.2023.10058380","url":null,"abstract":"","PeriodicalId":39217,"journal":{"name":"International Journal of High Performance Systems Architecture","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"66896517","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-01-01DOI: 10.1504/ijhpsa.2023.130224
Shweta Kumari, Zeesha Mishra, Bibhudendra Acharya
The internet of things (IoT) has recently expanded, resulting in a new world of smart gadgets with substantial security consequences. For their vital security role, lightweight block ciphers have gained a significant amount of development in low resource devices (LRDs). SIMECK is a new lightweight block cipher family that incorporates the finest aspect of both SIMON and SPECK. SIMECK is a more efficient block cipher than SIMON and SPECK cipher. These lightweight ciphers are especially referred to as an alternative to the AES for RCD. In this study, area optimised architecture is implemented for SIMECK lightweight block cipher with sizes: 64/128. For implementation on different platforms such as Sparton-6, Sparton-3, Virtex-7, Virtex-6, Virtex-5 and Virtex-4 FPGA are used to examine several properties such as block size, key scheduling, and throughput, among others. The proposed area optimised architecture have attained a maximum operating frequency of 496.429 MHz with 61 slices and a high throughput of 706.032 Mbps on the Virtex-7 platform.
{"title":"Efficient hardware implementation of SIMECK lightweight block cipher","authors":"Shweta Kumari, Zeesha Mishra, Bibhudendra Acharya","doi":"10.1504/ijhpsa.2023.130224","DOIUrl":"https://doi.org/10.1504/ijhpsa.2023.130224","url":null,"abstract":"The internet of things (IoT) has recently expanded, resulting in a new world of smart gadgets with substantial security consequences. For their vital security role, lightweight block ciphers have gained a significant amount of development in low resource devices (LRDs). SIMECK is a new lightweight block cipher family that incorporates the finest aspect of both SIMON and SPECK. SIMECK is a more efficient block cipher than SIMON and SPECK cipher. These lightweight ciphers are especially referred to as an alternative to the AES for RCD. In this study, area optimised architecture is implemented for SIMECK lightweight block cipher with sizes: 64/128. For implementation on different platforms such as Sparton-6, Sparton-3, Virtex-7, Virtex-6, Virtex-5 and Virtex-4 FPGA are used to examine several properties such as block size, key scheduling, and throughput, among others. The proposed area optimised architecture have attained a maximum operating frequency of 496.429 MHz with 61 slices and a high throughput of 706.032 Mbps on the Virtex-7 platform.","PeriodicalId":39217,"journal":{"name":"International Journal of High Performance Systems Architecture","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135585159","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-01-01DOI: 10.1504/ijhpsa.2023.130225
S.K. Binu Siva Singh, K.V. Karthikeyan
{"title":"High resolution digital pulse width modulator architecture using reversible synchronous sequential counter and synchronous phase-shifted circuit","authors":"S.K. Binu Siva Singh, K.V. Karthikeyan","doi":"10.1504/ijhpsa.2023.130225","DOIUrl":"https://doi.org/10.1504/ijhpsa.2023.130225","url":null,"abstract":"","PeriodicalId":39217,"journal":{"name":"International Journal of High Performance Systems Architecture","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2023-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135585156","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-01-01DOI: 10.1504/ijhpsa.2022.10054069
R. S., Janani Kariyappa
{"title":"Countermeasure SDN-based IoT Threats Using Blockchain Multicontroller","authors":"R. S., Janani Kariyappa","doi":"10.1504/ijhpsa.2022.10054069","DOIUrl":"https://doi.org/10.1504/ijhpsa.2022.10054069","url":null,"abstract":"","PeriodicalId":39217,"journal":{"name":"International Journal of High Performance Systems Architecture","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"66896935","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-01-01DOI: 10.1504/ijhpsa.2021.10045128
Feilu Hang, Linjiang Xie, F. Shibly, Wei Ou, Yao Lv, W. Guo
{"title":"Network security defence system based on artificial intelligence and big data technology","authors":"Feilu Hang, Linjiang Xie, F. Shibly, Wei Ou, Yao Lv, W. Guo","doi":"10.1504/ijhpsa.2021.10045128","DOIUrl":"https://doi.org/10.1504/ijhpsa.2021.10045128","url":null,"abstract":"","PeriodicalId":39217,"journal":{"name":"International Journal of High Performance Systems Architecture","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"66896742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-01-01DOI: 10.1504/ijhpsa.2021.10042918
Abderrahmane Ez-Zahout
{"title":"A distributed big data analytics model for people re-identification based dimensionality reduction","authors":"Abderrahmane Ez-Zahout","doi":"10.1504/ijhpsa.2021.10042918","DOIUrl":"https://doi.org/10.1504/ijhpsa.2021.10042918","url":null,"abstract":"","PeriodicalId":39217,"journal":{"name":"International Journal of High Performance Systems Architecture","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"66896604","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-01-01DOI: 10.1504/IJHPSA.2017.10012615
Xinrong Lu, Xiaodong Gao, Dinghui Mao, Jiawei Wang, Yi-min Mao
{"title":"Research and application of an uncertain genetic neural network in landslide hazard prediction","authors":"Xinrong Lu, Xiaodong Gao, Dinghui Mao, Jiawei Wang, Yi-min Mao","doi":"10.1504/IJHPSA.2017.10012615","DOIUrl":"https://doi.org/10.1504/IJHPSA.2017.10012615","url":null,"abstract":"","PeriodicalId":39217,"journal":{"name":"International Journal of High Performance Systems Architecture","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"66896476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-01-01DOI: 10.1504/IJHPSA.2016.078802
J. Jianchun, Wang Kailong, Jing Yanmei
More and more multicore processors are applied to vehicle information terminal VIT. It has made a great challenge to vehicular network application VNA development that all VNA software must be adapted to the hardware features. We propose a parallel middleware framework for VNAs in this article. Our targets aim at resolving the requirements of VNAs for real-time performance, extensibility, reusable structure and parallelisation access, and the adaptability for heterogeneous network. We discuss and present a middleware framework with multi-layer architecture, which consist of static and active modules, to be responsible for data process and message transmission respectively. Finally, we develop the middleware prototypes to verify the feasibility of our middleware framework in Linux and Android systems, and the experimental results are presented to show the value and potential of the proposed method.
{"title":"A parallel middleware framework for vehicular network applications","authors":"J. Jianchun, Wang Kailong, Jing Yanmei","doi":"10.1504/IJHPSA.2016.078802","DOIUrl":"https://doi.org/10.1504/IJHPSA.2016.078802","url":null,"abstract":"More and more multicore processors are applied to vehicle information terminal VIT. It has made a great challenge to vehicular network application VNA development that all VNA software must be adapted to the hardware features. We propose a parallel middleware framework for VNAs in this article. Our targets aim at resolving the requirements of VNAs for real-time performance, extensibility, reusable structure and parallelisation access, and the adaptability for heterogeneous network. We discuss and present a middleware framework with multi-layer architecture, which consist of static and active modules, to be responsible for data process and message transmission respectively. Finally, we develop the middleware prototypes to verify the feasibility of our middleware framework in Linux and Android systems, and the experimental results are presented to show the value and potential of the proposed method.","PeriodicalId":39217,"journal":{"name":"International Journal of High Performance Systems Architecture","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1504/IJHPSA.2016.078802","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"66896779","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-03-01DOI: 10.1504/IJHPSA.2014.059873
Zhang Jian, Cheng Ren-hong, Wang Kai, Zhao Hong
With the number of digital videos and digital images increasing tremendously in e-mails and web pages, text extraction from images becomes important more than ever. Born-digital images are generated directly with the computer and the text in the images is important to help the semantic understanding of the images. Although there are many methods proposed over the past years for text extraction from natural scene images, the text detection and extraction from born-digital images remains a challenge. This paper proposes a novel method to segment the text connected components CCs from a born-digital image. Firstly, binarisation is conducted on the given image to get all candidate text CCs based on wavelet theory. Secondly, classification is conducted on the extracted CCs to label text CCs based on conditional random field CRF - a probabilistic graph model that has been widely used in natural language processing. Experimental results show that the proposed method can effectively extract text from the born-digital images.
{"title":"Research on born-digital image text extraction based on conditional random field","authors":"Zhang Jian, Cheng Ren-hong, Wang Kai, Zhao Hong","doi":"10.1504/IJHPSA.2014.059873","DOIUrl":"https://doi.org/10.1504/IJHPSA.2014.059873","url":null,"abstract":"With the number of digital videos and digital images increasing tremendously in e-mails and web pages, text extraction from images becomes important more than ever. Born-digital images are generated directly with the computer and the text in the images is important to help the semantic understanding of the images. Although there are many methods proposed over the past years for text extraction from natural scene images, the text detection and extraction from born-digital images remains a challenge. This paper proposes a novel method to segment the text connected components CCs from a born-digital image. Firstly, binarisation is conducted on the given image to get all candidate text CCs based on wavelet theory. Secondly, classification is conducted on the extracted CCs to label text CCs based on conditional random field CRF - a probabilistic graph model that has been widely used in natural language processing. Experimental results show that the proposed method can effectively extract text from the born-digital images.","PeriodicalId":39217,"journal":{"name":"International Journal of High Performance Systems Architecture","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1504/IJHPSA.2014.059873","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"66896705","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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