Pub Date : 2003-06-15DOI: 10.1109/ARITH.2003.1207658
Peter Kornerup
The quotient digit selection in the SRT division algorithm is based on a few most significant bits of the remainder and divisor, where the remainder is usually represented in a redundant representation. The number of leading bits needed depends on the quotient radix and digit set, and is usually found by an extensive search, to assure that the next quotient digit can be chosen as valid for all points (remainder, divisor) in a set defined by the truncated remainder and divisor, i.e., an "uncertainty rectangle". We present expressions for the number of bits needed for the truncated remainder and divisor, thus eliminating the need for a search through the truncation parameter space for validation. We also present simple algorithms to properly map truncated negative divisors and remainders into nonnegative values, allowing the quotient selection function only to be defined on the smaller domain of nonnegative values.
{"title":"Revisiting SRT quotient digit selection","authors":"Peter Kornerup","doi":"10.1109/ARITH.2003.1207658","DOIUrl":"https://doi.org/10.1109/ARITH.2003.1207658","url":null,"abstract":"The quotient digit selection in the SRT division algorithm is based on a few most significant bits of the remainder and divisor, where the remainder is usually represented in a redundant representation. The number of leading bits needed depends on the quotient radix and digit set, and is usually found by an extensive search, to assure that the next quotient digit can be chosen as valid for all points (remainder, divisor) in a set defined by the truncated remainder and divisor, i.e., an \"uncertainty rectangle\". We present expressions for the number of bits needed for the truncated remainder and divisor, thus eliminating the need for a search through the truncation parameter space for validation. We also present simple algorithms to properly map truncated negative divisors and remainders into nonnegative values, allowing the quotient selection function only to be defined on the smaller domain of nonnegative values.","PeriodicalId":399928,"journal":{"name":"Proceedings 2003 16th IEEE Symposium on Computer Arithmetic","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115343124","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-15DOI: 10.1109/ARITH.2003.1207668
J. Muller
We aim at evaluating elementary and special functions using small tables and small, rectangular, multipliers. To do that, we show how accurate polynomial approximations whose order-1 coefficients are small in size (a few bits only) can be computed. We compare the obtained results with similar work in the recent literature.
{"title":"\"Partially rounded\" small-order approximations for accurate, hardware-oriented, table-based methods","authors":"J. Muller","doi":"10.1109/ARITH.2003.1207668","DOIUrl":"https://doi.org/10.1109/ARITH.2003.1207668","url":null,"abstract":"We aim at evaluating elementary and special functions using small tables and small, rectangular, multipliers. To do that, we show how accurate polynomial approximations whose order-1 coefficients are small in size (a few bits only) can be computed. We compare the obtained results with similar work in the recent literature.","PeriodicalId":399928,"journal":{"name":"Proceedings 2003 16th IEEE Symposium on Computer Arithmetic","volume":"433 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116279869","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-15DOI: 10.1109/ARITH.2003.1207673
J. Harrison
One approach to testing and/or proving correctness of a floating-point algorithm computing a function f is based on finding input floating-point numbers a such that the exact result f(a) is very close to a "rounding boundary", i.e. a floating-point number or a midpoint between them. We show how to do this for the reciprocal function by utilizing prime factorizations. We present the method and show examples, as well as making a fairly detailed study of its expected and worst-case behavior. We point out how this analysis of reciprocals can be useful in analyzing certain reciprocal algorithms, and also show how the approach can be trivially adapted to the reciprocal square root function.
{"title":"Isolating critical cases for reciprocals using integer factorization","authors":"J. Harrison","doi":"10.1109/ARITH.2003.1207673","DOIUrl":"https://doi.org/10.1109/ARITH.2003.1207673","url":null,"abstract":"One approach to testing and/or proving correctness of a floating-point algorithm computing a function f is based on finding input floating-point numbers a such that the exact result f(a) is very close to a \"rounding boundary\", i.e. a floating-point number or a midpoint between them. We show how to do this for the reciprocal function by utilizing prime factorizations. We present the method and show examples, as well as making a fairly detailed study of its expected and worst-case behavior. We point out how this analysis of reciprocals can be useful in analyzing certain reciprocal algorithms, and also show how the approach can be trivially adapted to the reciprocal square root function.","PeriodicalId":399928,"journal":{"name":"Proceedings 2003 16th IEEE Symposium on Computer Arithmetic","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129977070","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-15DOI: 10.1109/ARITH.2003.1207685
S. Cotofana, C. Lageweg, S. Vassiliadis
We investigate the implementation of basic arithmetic functions, such as addition and multiplication, in single electron tunneling (SET) technology. First, we describe the SET equivalents of Boolean CMOS gates and threshold logic gates. Second, we propose a set of building blocks, which can be utilized for a novel design style, namely arithmetic operations performed by direct manipulation of the location of individual electrons within the system. Using this new set of building blocks, we propose several novel approaches for computing addition related arithmetic operations via the controlled transport of charge (individual electrons). In particular, we prove the following: n-bit addition can be implemented with a depth-2 network built with O(n) circuit elements; n-input parity can be computed with a depth-2 network constructed with O(n) circuit elements and the same applies for n/logn counters; multiple operand addition of m n-bit operands can be implemented with a depth-2 network using O(mn) circuit elements; and finally n-bit multiplication can be implemented with a depth-3 network built with O(n) circuit elements.
{"title":"On computing addition related arithmetic operations via controlled transport of charge","authors":"S. Cotofana, C. Lageweg, S. Vassiliadis","doi":"10.1109/ARITH.2003.1207685","DOIUrl":"https://doi.org/10.1109/ARITH.2003.1207685","url":null,"abstract":"We investigate the implementation of basic arithmetic functions, such as addition and multiplication, in single electron tunneling (SET) technology. First, we describe the SET equivalents of Boolean CMOS gates and threshold logic gates. Second, we propose a set of building blocks, which can be utilized for a novel design style, namely arithmetic operations performed by direct manipulation of the location of individual electrons within the system. Using this new set of building blocks, we propose several novel approaches for computing addition related arithmetic operations via the controlled transport of charge (individual electrons). In particular, we prove the following: n-bit addition can be implemented with a depth-2 network built with O(n) circuit elements; n-input parity can be computed with a depth-2 network constructed with O(n) circuit elements and the same applies for n/logn counters; multiple operand addition of m n-bit operands can be implemented with a depth-2 network using O(mn) circuit elements; and finally n-bit multiplication can be implemented with a depth-3 network built with O(n) circuit elements.","PeriodicalId":399928,"journal":{"name":"Proceedings 2003 16th IEEE Symposium on Computer Arithmetic","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122033659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-15DOI: 10.1109/ARITH.2003.1207656
Nicolas Boullis, A. Tisserand
We present some improvements on the optimization of hardware multiplication by constant matrices. We focus on the automatic generation of circuits that involve constant matrix multiplication (CMM), i.e. multiplication of a vector by a constant matrix. The proposed method, based on number recoding and dedicated common sub-expression factorization algorithms was implemented in a VHDL generator. The obtained results on several applications have been implemented on FPGAs and compared to previous solutions. Up to 40% area and speed savings are achieved.
{"title":"Some optimizations of hardware multiplication by constant matrices","authors":"Nicolas Boullis, A. Tisserand","doi":"10.1109/ARITH.2003.1207656","DOIUrl":"https://doi.org/10.1109/ARITH.2003.1207656","url":null,"abstract":"We present some improvements on the optimization of hardware multiplication by constant matrices. We focus on the automatic generation of circuits that involve constant matrix multiplication (CMM), i.e. multiplication of a vector by a constant matrix. The proposed method, based on number recoding and dedicated common sub-expression factorization algorithms was implemented in a VHDL generator. The obtained results on several applications have been implemented on FPGAs and compared to previous solutions. Up to 40% area and speed savings are achieved.","PeriodicalId":399928,"journal":{"name":"Proceedings 2003 16th IEEE Symposium on Computer Arithmetic","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126494470","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-15DOI: 10.1109/ARITH.2003.1207687
N. Burgess
We introduce a method for extracting the core of a residue number system (RNS) number within the RNS, this affording a new method for scaling RNS numbers. Suppose an RNS comprises a set of coprime moduli, m/sub i/, with /spl Pi/m/sub i/=M. We describe a method for approximately scaling such an RNS number by a subset of the moduli, /spl Pi/m/sub j/=M/sub J//spl ap//spl radic/M, with the characteristic that all computations are performed using the original moduli and one other nonmaintained short wordlength modulus.
{"title":"Scaling an RNS number using the core function","authors":"N. Burgess","doi":"10.1109/ARITH.2003.1207687","DOIUrl":"https://doi.org/10.1109/ARITH.2003.1207687","url":null,"abstract":"We introduce a method for extracting the core of a residue number system (RNS) number within the RNS, this affording a new method for scaling RNS numbers. Suppose an RNS comprises a set of coprime moduli, m/sub i/, with /spl Pi/m/sub i/=M. We describe a method for approximately scaling such an RNS number by a subset of the moduli, /spl Pi/m/sub j/=M/sub J//spl ap//spl radic/M, with the characteristic that all computations are performed using the original moduli and one other nonmaintained short wordlength modulus.","PeriodicalId":399928,"journal":{"name":"Proceedings 2003 16th IEEE Symposium on Computer Arithmetic","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123242625","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-15DOI: 10.1109/ARITH.2003.1207659
Mark McCann, N. Pippenger
SRT division, as it was discovered in the late 1950s represented an important improvement in the speed of division algorithms for computers at the time. A variant of SRT division is still commonly implemented in computers today. Although some bounds on the performance of the original SRT division method were obtained, a great many questions remained unanswered. The original version of SRT division is described as a dynamical system. This enables us to bring modern dynamical systems theory, a relatively new development in mathematics, to bear on an older problem. In doing so, we are able to show that SRT division is ergodic, and is even Bernoulli, for all real divisors and dividends. With the Bernoulli property, we are able to use entropy to prove that the natural extensions of SRT division are isomorphic by way of the Kolmogorov-Ornstein theorem. We demonstrate how our methods and results can be applied to a much larger class of division algorithms.
{"title":"SRT division algorithms as dynamical systems","authors":"Mark McCann, N. Pippenger","doi":"10.1109/ARITH.2003.1207659","DOIUrl":"https://doi.org/10.1109/ARITH.2003.1207659","url":null,"abstract":"SRT division, as it was discovered in the late 1950s represented an important improvement in the speed of division algorithms for computers at the time. A variant of SRT division is still commonly implemented in computers today. Although some bounds on the performance of the original SRT division method were obtained, a great many questions remained unanswered. The original version of SRT division is described as a dynamical system. This enables us to bring modern dynamical systems theory, a relatively new development in mathematics, to bear on an older problem. In doing so, we are able to show that SRT division is ergodic, and is even Bernoulli, for all real divisors and dividends. With the Bernoulli property, we are able to use entropy to prove that the natural extensions of SRT division are isomorphic by way of the Kolmogorov-Ornstein theorem. We demonstrate how our methods and results can be applied to a much larger class of division algorithms.","PeriodicalId":399928,"journal":{"name":"Proceedings 2003 16th IEEE Symposium on Computer Arithmetic","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128638857","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-15DOI: 10.1109/ARITH.2003.1207667
E. Schwarz
Almost twenty years ago the IEEE 754 binary floating-point standard was adopted. Since then almost every microprocessor as well as many programming languages have defined the floating-point arithmetic to be IEEE 754 compliant. From the many years experience in implementing the standard in hardware and writing floating-point programs, there have been numerous suggestions for revisions. All IEEE standards must undergo a review process every 5 years or be dropped as an active standard. For past reviews this standard was extended without much discussion. But finally in January 2001 an in-depth review was started. A committee was formed and over the past two years many revisions have been evaluated. The most extensive change to the standard is to adopt formats for decimal floating-point arithmetic. This proposal creates decimal floating-point data formats for 32, 64, and 128 bits. Decimal floating-point arithmetic provides an exact representation of displayed numbers and provides a precise round at decimal radix point. This type of arithmetic is required in financial calculations. Some experts argue that decimal will replace binary due to its ability to represent decimal numbers exactly, while others think that binary will remain the key floating-point format due to its speed of execution and its more regular spacing of intervals. Another once controversial proposal is the addition of fused multiply-add. This operation only causes one rounding error, while in most implementations, provides twice the performance of separate operations. Other additions to the standard include a quadword format and many predicate functions such as comparison operators like greater than. Also operators for maximum and minimum have been accepted that after hours of arguing now favor a numeric result over a NaN. There are also deletions such as the single extended and double extended formats. And there are some items that are deleted in one meeting and resurrected in the following meeting such as signaling NaNs. Over the past two years of committee review there has been many proposals discussed. This panel discussion will enlighten the audience to the additions, deletions, and some of the current controversial proposals. The panel will consist of : • David Hough, Sun Microsystems, Editor of the Standard – Overview • Mike Cowlishaw, IBM Corp., Decimal Floating-Point Software Advocate • David Bailey, Lawrence Berkeley Lab., Quadword Precision Advocate • David Matula, Southern Methodist University, Academics / Industry Consultant • Eric Schwarz, IBM Corp., Decimal Floating-Point Hardware – Panel Chair
{"title":"Revisions to the IEEE 754 standard for floating-point arithmetic","authors":"E. Schwarz","doi":"10.1109/ARITH.2003.1207667","DOIUrl":"https://doi.org/10.1109/ARITH.2003.1207667","url":null,"abstract":"Almost twenty years ago the IEEE 754 binary floating-point standard was adopted. Since then almost every microprocessor as well as many programming languages have defined the floating-point arithmetic to be IEEE 754 compliant. From the many years experience in implementing the standard in hardware and writing floating-point programs, there have been numerous suggestions for revisions. All IEEE standards must undergo a review process every 5 years or be dropped as an active standard. For past reviews this standard was extended without much discussion. But finally in January 2001 an in-depth review was started. A committee was formed and over the past two years many revisions have been evaluated. The most extensive change to the standard is to adopt formats for decimal floating-point arithmetic. This proposal creates decimal floating-point data formats for 32, 64, and 128 bits. Decimal floating-point arithmetic provides an exact representation of displayed numbers and provides a precise round at decimal radix point. This type of arithmetic is required in financial calculations. Some experts argue that decimal will replace binary due to its ability to represent decimal numbers exactly, while others think that binary will remain the key floating-point format due to its speed of execution and its more regular spacing of intervals. Another once controversial proposal is the addition of fused multiply-add. This operation only causes one rounding error, while in most implementations, provides twice the performance of separate operations. Other additions to the standard include a quadword format and many predicate functions such as comparison operators like greater than. Also operators for maximum and minimum have been accepted that after hours of arguing now favor a numeric result over a NaN. There are also deletions such as the single extended and double extended formats. And there are some items that are deleted in one meeting and resurrected in the following meeting such as signaling NaNs. Over the past two years of committee review there has been many proposals discussed. This panel discussion will enlighten the audience to the additions, deletions, and some of the current controversial proposals. The panel will consist of : • David Hough, Sun Microsystems, Editor of the Standard – Overview • Mike Cowlishaw, IBM Corp., Decimal Floating-Point Software Advocate • David Bailey, Lawrence Berkeley Lab., Quadword Precision Advocate • David Matula, Southern Methodist University, Academics / Industry Consultant • Eric Schwarz, IBM Corp., Decimal Floating-Point Hardware – Panel Chair","PeriodicalId":399928,"journal":{"name":"Proceedings 2003 16th IEEE Symposium on Computer Arithmetic","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126021560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-15DOI: 10.1109/ARITH.2003.1207672
D. Stehlé, V. Lefèvre, P. Zimmermann
We propose a new algorithm to find worst cases for correct rounding of an analytic function. We first reduce this problem to the real small value problem - i.e. for polynomials with real coefficients. Then we show that this second problem can be solved efficiently, by extending Coppersmith's work on the integer small value problem - for polynomials with integer coefficients - using lattice reduction (D. Coppersmith, 1996; 2001). For floating-point numbers with a mantissa less than N, and a polynomial approximation of degree d, our algorithm finds all worst cases at distance < N/sup -d2//(2d+1) from a machine number in time O(N/sup ((d+1)/(2d+1))+/spl epsiv//). For d=2, this improves on the O(N/sup 2/(3+/spl epsiv/)/) complexity from Lefevre's algorithm (V. Lefevre, 2000; V. Lefevre et al., 2001) to O(N/sup 3/(5+/spl epsiv/)/). We exhibit some new worst cases found using our algorithm, for double-extended and quadruple precision. For larger d, our algorithm can be used to check that there exist no worst cases at distance < N/sup -k/ in time O(N/sup (1/2)+O(1/k)/).
{"title":"Worst cases and lattice reduction","authors":"D. Stehlé, V. Lefèvre, P. Zimmermann","doi":"10.1109/ARITH.2003.1207672","DOIUrl":"https://doi.org/10.1109/ARITH.2003.1207672","url":null,"abstract":"We propose a new algorithm to find worst cases for correct rounding of an analytic function. We first reduce this problem to the real small value problem - i.e. for polynomials with real coefficients. Then we show that this second problem can be solved efficiently, by extending Coppersmith's work on the integer small value problem - for polynomials with integer coefficients - using lattice reduction (D. Coppersmith, 1996; 2001). For floating-point numbers with a mantissa less than N, and a polynomial approximation of degree d, our algorithm finds all worst cases at distance < N/sup -d2//(2d+1) from a machine number in time O(N/sup ((d+1)/(2d+1))+/spl epsiv//). For d=2, this improves on the O(N/sup 2/(3+/spl epsiv/)/) complexity from Lefevre's algorithm (V. Lefevre, 2000; V. Lefevre et al., 2001) to O(N/sup 3/(5+/spl epsiv/)/). We exhibit some new worst cases found using our algorithm, for double-extended and quadruple precision. For larger d, our algorithm can be used to check that there exist no worst cases at distance < N/sup -k/ in time O(N/sup (1/2)+O(1/k)/).","PeriodicalId":399928,"journal":{"name":"Proceedings 2003 16th IEEE Symposium on Computer Arithmetic","volume":"29 7","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114025506","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-15DOI: 10.1109/ARITH.2003.1207662
E. Schwarz, M. Schmookler, S. D. Trong
Denormalized numbers are the most difficult type of numbers to implement in floating-point units. They are so complex that some designs have elected to handle them in software rather than hardware. This has resulted in execution times in the tens of thousands of cycles, which has made denormalized numbers useless to programmers. This does not have to happen. With a small amount of additional hardware, denormalized numbers and underflows can be handled close to the speed of normalized numbers. We will summarize the little known techniques for handling denormalized numbers. Most of the techniques discussed have only been discussed in filed or pending patent applications.
{"title":"Hardware implementations of denormalized numbers","authors":"E. Schwarz, M. Schmookler, S. D. Trong","doi":"10.1109/ARITH.2003.1207662","DOIUrl":"https://doi.org/10.1109/ARITH.2003.1207662","url":null,"abstract":"Denormalized numbers are the most difficult type of numbers to implement in floating-point units. They are so complex that some designs have elected to handle them in software rather than hardware. This has resulted in execution times in the tens of thousands of cycles, which has made denormalized numbers useless to programmers. This does not have to happen. With a small amount of additional hardware, denormalized numbers and underflows can be handled close to the speed of normalized numbers. We will summarize the little known techniques for handling denormalized numbers. Most of the techniques discussed have only been discussed in filed or pending patent applications.","PeriodicalId":399928,"journal":{"name":"Proceedings 2003 16th IEEE Symposium on Computer Arithmetic","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121250391","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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