Message-passing mechanism is commonly used to preserve data coherency in distributed systems. This paper presents an algorithm for insertion of minimal message-passing in system-level design to guarantee data coherency. The target architecture is a multi-component heterogeneous system, where some components have local memory (or they are memory components by themselves). The algorithm enables automatic insertion of message-passing during system-level design to relieve designers from tedious and error-prone manual work. The optimal solution given by the algorithm also ensures the quality of automatic insertion. Experiments show that the automatic approach achieves a productivity gain of 200X over manual refinement.
{"title":"Optimal message-passing for data coherency in distributed architecture","authors":"D. Gajski, J. Peng","doi":"10.1145/581199.581206","DOIUrl":"https://doi.org/10.1145/581199.581206","url":null,"abstract":"Message-passing mechanism is commonly used to preserve data coherency in distributed systems. This paper presents an algorithm for insertion of minimal message-passing in system-level design to guarantee data coherency. The target architecture is a multi-component heterogeneous system, where some components have local memory (or they are memory components by themselves). The algorithm enables automatic insertion of message-passing during system-level design to relieve designers from tedious and error-prone manual work. The optimal solution given by the algorithm also ensures the quality of automatic insertion. Experiments show that the automatic approach achieves a productivity gain of 200X over manual refinement.","PeriodicalId":413693,"journal":{"name":"15th International Symposium on System Synthesis, 2002.","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121935693","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. Lauwereins, Chun Wong, P. Marchal, J. Vounckx, Patrick David, S. Himpe, F. Catthoor, Peng Yang
This paper addresses the problem of mapping an application, which is highly dynamic in the future, onto a heterogeneous multiprocessor platform in an energy efficient way. A two-phase scheduling method is used for that purpose. By exploring the Pareto curves and scenarios generated at design time, the run-time scheduler can easily find a good scheduling at a very low overhead, satisfying the system constraints and minimizing the energy consumption. A real-life example from a 3D quality of service kernel is used to show the effectiveness of our method.
{"title":"Managing dynamic concurrent tasks in embedded real-time multimedia systems","authors":"R. Lauwereins, Chun Wong, P. Marchal, J. Vounckx, Patrick David, S. Himpe, F. Catthoor, Peng Yang","doi":"10.1145/581225.581226","DOIUrl":"https://doi.org/10.1145/581225.581226","url":null,"abstract":"This paper addresses the problem of mapping an application, which is highly dynamic in the future, onto a heterogeneous multiprocessor platform in an energy efficient way. A two-phase scheduling method is used for that purpose. By exploring the Pareto curves and scenarios generated at design time, the run-time scheduler can easily find a good scheduling at a very low overhead, satisfying the system constraints and minimizing the energy consumption. A real-life example from a 3D quality of service kernel is used to show the effectiveness of our method.","PeriodicalId":413693,"journal":{"name":"15th International Symposium on System Synthesis, 2002.","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131667805","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Nicolau, N. Dutt, Rajesh K. Gupta, N. Savoiu, Mehrdad Reshadi, S. Gupta
We introduce a new approach, "Dynamic Common Sub-expression Elimination (CSE)", that dynamically eliminates common sub-expressions based on new opportunities created during scheduling of control-intensive designs. Classical CSE techniques fail to eliminate several common sub-expressions in control-intensive designs due to the presence of a complex mix of control and data-flow. Aggressive speculative code motions employed to schedule control-intensive designs often re-order, speculate and duplicate operations, hence changing the control flow between the operations with common sub-expressions. This leads to new opportunities for applying CSE dynamically. We have implemented dynamic CSE in a high-level synthesis framework called Spark and present results for experiments performed using various combinations of CSE and dynamic CSE. The benchmarks used consist of four functional blocks derived from two moderately complex industrial-strength applications, namely, MPEG-1 and the GIMP image processing tool. Our dynamic CSE techniques result in improvements of up to 22% in the controller size and up to 31% in performance; easily surpassing the improvements obtained by the traditional CSE approach. We also observe an unexpected (and significant) reduction in the number of registers using our approach.
{"title":"Dynamic common sub-expression elimination during scheduling in high-level synthesis","authors":"A. Nicolau, N. Dutt, Rajesh K. Gupta, N. Savoiu, Mehrdad Reshadi, S. Gupta","doi":"10.1145/581199.581256","DOIUrl":"https://doi.org/10.1145/581199.581256","url":null,"abstract":"We introduce a new approach, \"Dynamic Common Sub-expression Elimination (CSE)\", that dynamically eliminates common sub-expressions based on new opportunities created during scheduling of control-intensive designs. Classical CSE techniques fail to eliminate several common sub-expressions in control-intensive designs due to the presence of a complex mix of control and data-flow. Aggressive speculative code motions employed to schedule control-intensive designs often re-order, speculate and duplicate operations, hence changing the control flow between the operations with common sub-expressions. This leads to new opportunities for applying CSE dynamically. We have implemented dynamic CSE in a high-level synthesis framework called Spark and present results for experiments performed using various combinations of CSE and dynamic CSE. The benchmarks used consist of four functional blocks derived from two moderately complex industrial-strength applications, namely, MPEG-1 and the GIMP image processing tool. Our dynamic CSE techniques result in improvements of up to 22% in the controller size and up to 31% in performance; easily surpassing the improvements obtained by the traditional CSE approach. We also observe an unexpected (and significant) reduction in the number of registers using our approach.","PeriodicalId":413693,"journal":{"name":"15th International Symposium on System Synthesis, 2002.","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120949325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
H. Yasuura, N. Takagi, S. Ravi, M. Torla, C. Gebotys
SoC is one of the important components of social and personal information systems, which directly influence with our life, property and privacy Security technology is now embedded into various hardware and software of SoC and SoC designers should be concerned with security issues. Cryptography requires heavy computation and wireless communication requests architecture and protocols for security. In design process of SoC, choice of IP's and design data control also significantly affect on the security of the systems that uses the SoC. In this panel, we will have discussions on the security on SoC from various viewpoints. System architecture, circuit complexity, test and validation, energy consumption, security policy, and design methodology are discussed for exploring research directions of secure system synthesis.
{"title":"Special session: security on SoC","authors":"H. Yasuura, N. Takagi, S. Ravi, M. Torla, C. Gebotys","doi":"10.1145/581199.581242","DOIUrl":"https://doi.org/10.1145/581199.581242","url":null,"abstract":"SoC is one of the important components of social and personal information systems, which directly influence with our life, property and privacy Security technology is now embedded into various hardware and software of SoC and SoC designers should be concerned with security issues. Cryptography requires heavy computation and wireless communication requests architecture and protocols for security. In design process of SoC, choice of IP's and design data control also significantly affect on the security of the systems that uses the SoC. In this panel, we will have discussions on the security on SoC from various viewpoints. System architecture, circuit complexity, test and validation, energy consumption, security policy, and design methodology are discussed for exploring research directions of secure system synthesis.","PeriodicalId":413693,"journal":{"name":"15th International Symposium on System Synthesis, 2002.","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116875732","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We present a system-level design and programming method for embedded multiprocessor systems. The aim of the method is to improve the design time and design quality by providing a structured approach for implementing process networks. We use process networks as re-usable and architecture-independent functional specifications. The method facilitates the cost-driven and constraint-driven source code transformation of process networks into architecture-specific implementations in the form of communicating tasks. We apply the method to implement a JPEG decoding process network in software on a set of MIPS processors. We apply three transformations to optimize synchronization rates and data transfers and to exploit data parallelism for this target architecture. We evaluate the impact of the source code transformations and the performance of the resulting implementations in terms of design time, execution time, and code size. The results show that process networks can be implemented quickly and efficiently on embedded multiprocessor systems.
{"title":"Multiprocessor mapping of process networks: a JPEG decoding case study","authors":"de Kock, Philips","doi":"10.1145/581199.581216","DOIUrl":"https://doi.org/10.1145/581199.581216","url":null,"abstract":"We present a system-level design and programming method for embedded multiprocessor systems. The aim of the method is to improve the design time and design quality by providing a structured approach for implementing process networks. We use process networks as re-usable and architecture-independent functional specifications. The method facilitates the cost-driven and constraint-driven source code transformation of process networks into architecture-specific implementations in the form of communicating tasks. We apply the method to implement a JPEG decoding process network in software on a set of MIPS processors. We apply three transformations to optimize synchronization rates and data transfers and to exploit data parallelism for this target architecture. We evaluate the impact of the source code transformations and the performance of the resulting implementations in terms of design time, execution time, and code size. The results show that process networks can be implemented quickly and efficiently on embedded multiprocessor systems.","PeriodicalId":413693,"journal":{"name":"15th International Symposium on System Synthesis, 2002.","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125692756","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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