Pub Date : 2017-12-06DOI: 10.1109/EPTC.2017.8277541
M. D. Rotaru, Mahmoud Wagih
Recent work by Intel [1,2] has shown that it is possible to reduce the loss of transmission lines through innovative routing. The “vertical trench” proposed in Intel's work [1,2] showed a 20% reduction in the differential insertion loss. In this work a detailed discussion on the reasons why this novel routing approach can reduce the loss of the differential lines as well as analysis on the design variables of and their effects on the performance of a differential transmission line employing the vertical trench is undertaken. It is also shown through simulation that similar improvements in the differential insertion loss can be obtained through simply increasing the thickness of the of metal for the differential pair.
{"title":"Analysis and design of low loss differential transmission line structures for high speed applications","authors":"M. D. Rotaru, Mahmoud Wagih","doi":"10.1109/EPTC.2017.8277541","DOIUrl":"https://doi.org/10.1109/EPTC.2017.8277541","url":null,"abstract":"Recent work by Intel [1,2] has shown that it is possible to reduce the loss of transmission lines through innovative routing. The “vertical trench” proposed in Intel's work [1,2] showed a 20% reduction in the differential insertion loss. In this work a detailed discussion on the reasons why this novel routing approach can reduce the loss of the differential lines as well as analysis on the design variables of and their effects on the performance of a differential transmission line employing the vertical trench is undertaken. It is also shown through simulation that similar improvements in the differential insertion loss can be obtained through simply increasing the thickness of the of metal for the differential pair.","PeriodicalId":414232,"journal":{"name":"2017 IEEE 19th Electronics Packaging Technology Conference (EPTC)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114995372","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/EPTC.2017.8277582
Nobuhito Komuro, Yuta Daijima, Shinya Imabayashi
The solder resist is an ink which covers the surface of the printed wiring board (PWB) and serves as an insulating film for protecting the circuit pattern. “Resist” has the role of preventing solder (= solder) from adhering to unnecessary parts in the mounting of parts, as it means “to resist” and “tolerate”. At the same time, it protects the circuit pattern from dust, heat and moisture as a permanent protective film to maintain insulation.
{"title":"Development of next generation solder resist","authors":"Nobuhito Komuro, Yuta Daijima, Shinya Imabayashi","doi":"10.1109/EPTC.2017.8277582","DOIUrl":"https://doi.org/10.1109/EPTC.2017.8277582","url":null,"abstract":"The solder resist is an ink which covers the surface of the printed wiring board (PWB) and serves as an insulating film for protecting the circuit pattern. “Resist” has the role of preventing solder (= solder) from adhering to unnecessary parts in the mounting of parts, as it means “to resist” and “tolerate”. At the same time, it protects the circuit pattern from dust, heat and moisture as a permanent protective film to maintain insulation.","PeriodicalId":414232,"journal":{"name":"2017 IEEE 19th Electronics Packaging Technology Conference (EPTC)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115141321","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/EPTC.2017.8277588
A. Hensel, Klaus Kohlmann von Platen, J. Franke
This paper describes and discusses a novel manufacturing process that enables an advanced top-level interconnection for power electronic applications. The commonly used aluminum bond wire process, where a friction welded connection is performed by the usage of ultrasonic on the substrate as well as on the semiconductor, is replaced by copper as a wire material. Thus, the overall performance of power electronic modules can be increased significantly because of the preeminent material characteristics of copper [1]. However, the higher hardness and lower ductility of copper in comparison to aluminum presuppose a functional coating on the silicon layers that absorbs the high bonding forces and protects the crystal structures from shattering. Different approaches for a selective copper metallization like galvanic metallization have been investigated and provide usable coating quality. Disadvantageously the processes are neither very flexible nor cost-effective and have also a bad environmental impact. The technology described in the following uses a current stabilized argon plasma to melt single copper particles which are then accelerated towards the substrate. Upon impact, the coating material solidifies and creates a diffusion-based adhesive layer on which the copper bonding process can be performed.
{"title":"Investigations of copper wire bonding capability on plasma based additive copper metallizations","authors":"A. Hensel, Klaus Kohlmann von Platen, J. Franke","doi":"10.1109/EPTC.2017.8277588","DOIUrl":"https://doi.org/10.1109/EPTC.2017.8277588","url":null,"abstract":"This paper describes and discusses a novel manufacturing process that enables an advanced top-level interconnection for power electronic applications. The commonly used aluminum bond wire process, where a friction welded connection is performed by the usage of ultrasonic on the substrate as well as on the semiconductor, is replaced by copper as a wire material. Thus, the overall performance of power electronic modules can be increased significantly because of the preeminent material characteristics of copper [1]. However, the higher hardness and lower ductility of copper in comparison to aluminum presuppose a functional coating on the silicon layers that absorbs the high bonding forces and protects the crystal structures from shattering. Different approaches for a selective copper metallization like galvanic metallization have been investigated and provide usable coating quality. Disadvantageously the processes are neither very flexible nor cost-effective and have also a bad environmental impact. The technology described in the following uses a current stabilized argon plasma to melt single copper particles which are then accelerated towards the substrate. Upon impact, the coating material solidifies and creates a diffusion-based adhesive layer on which the copper bonding process can be performed.","PeriodicalId":414232,"journal":{"name":"2017 IEEE 19th Electronics Packaging Technology Conference (EPTC)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121208185","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/EPTC.2017.8277533
S. Manoharan, Stevan Hunter, P. McCluskey
Wire bond evaluation is crucial in determining its quality. With the increase in use of copper wire bonds, this becomes even more important due to its nature to induce defects such as pad cracking. Bond shear testing is a widely used method to assess wire bond quality. Standards for evaluating wirebonds by shear test are in place (JEDEC, ASTM, IEC, etc.) however, they do not prescribe factors that affect results, making it difficult to compare the quality of bonds made in different conditions. Bond pad thickness is a major factor, studied in detail in this work. It is shown from a design of experiment and through finite element analysis, that bond pad thickness affects the bond shear strength value, while the IMC % coverage and shear mode are not dependent on pad thickness.
{"title":"Bond pad effects on the shear strength of copper wire bonds","authors":"S. Manoharan, Stevan Hunter, P. McCluskey","doi":"10.1109/EPTC.2017.8277533","DOIUrl":"https://doi.org/10.1109/EPTC.2017.8277533","url":null,"abstract":"Wire bond evaluation is crucial in determining its quality. With the increase in use of copper wire bonds, this becomes even more important due to its nature to induce defects such as pad cracking. Bond shear testing is a widely used method to assess wire bond quality. Standards for evaluating wirebonds by shear test are in place (JEDEC, ASTM, IEC, etc.) however, they do not prescribe factors that affect results, making it difficult to compare the quality of bonds made in different conditions. Bond pad thickness is a major factor, studied in detail in this work. It is shown from a design of experiment and through finite element analysis, that bond pad thickness affects the bond shear strength value, while the IMC % coverage and shear mode are not dependent on pad thickness.","PeriodicalId":414232,"journal":{"name":"2017 IEEE 19th Electronics Packaging Technology Conference (EPTC)","volume":"136 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127501630","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/EPTC.2017.8277441
Wayne Ng, K. Sweatman, Keisuke Kumagai, K. Takamura, T. Nishimura, S. Letz, A. Schletz
Nano-particle sintering silver (Ag) paste has recently become a topic of much discussion in commercial and academic circles and has been the subject of many papers at international technical conferences. Sintered Ag is one of the candidates for the replacement of high-lead (Pb) alloys such as Pb-5Sn and Pb-5Sn-2.5Ag in semiconductors, an application that is still exempt from the RoHS restrictions on Pb in electrical and electronic equipment. Although the EU Restriction on Hazardous Substances (RoHS) exemption has been extended to 2021 there is still a lot of interest in the use of sintered Ag in semiconductor die attach because it can survive the higher operating temperatures of more advanced SiC and GaAs power semiconductors. The demand for these advanced higher efficiency power semiconductors is expected to increase as electric and hybrid vehicles, renewable energy and smart electricity grids are more widely adopted and this provides further justification for the development of sintered Ag bonding technology. One of the advantages of sintered Ag is that it can form a joint at temperatures comparable with those used in die attach with high-Pb solder but once the process is completed will not melt until the temperature exceeds the 961°C melting point of Ag. In this paper, the authors report the results of power cycling of insulated-gate bipolar transistor (IGBT) semiconductors built using two variants of Ag sintering paste with a range of process parameters with the intention of determining the sensitivity of the bond life to such variations. Included in the experimental program as benchmarks are semiconductors built with conventional Pb-5Sn alloy and Pb-free alloy, SAC305. The semiconductor subjected to power cycling were subsequently subjected to examination by confocal scanning acoustic microscopy (CSAM) and cross-sectioning and scanning electron microscopy to determine the failure mechanisms. No fatigue cracks were observed in the sintered Ag joint regardless type of Ag sintering material used and the processing parameters. The dominant failure mechanism in the sintered Ag bonds was delamination. In the benchmark bonding materials, Pb5Sn and SAC305, classic solder fatigue failure appeared to be the dominant failure mechanism.
{"title":"The correlation between sintered silver joint reliability and pressure assisted sintering parameters","authors":"Wayne Ng, K. Sweatman, Keisuke Kumagai, K. Takamura, T. Nishimura, S. Letz, A. Schletz","doi":"10.1109/EPTC.2017.8277441","DOIUrl":"https://doi.org/10.1109/EPTC.2017.8277441","url":null,"abstract":"Nano-particle sintering silver (Ag) paste has recently become a topic of much discussion in commercial and academic circles and has been the subject of many papers at international technical conferences. Sintered Ag is one of the candidates for the replacement of high-lead (Pb) alloys such as Pb-5Sn and Pb-5Sn-2.5Ag in semiconductors, an application that is still exempt from the RoHS restrictions on Pb in electrical and electronic equipment. Although the EU Restriction on Hazardous Substances (RoHS) exemption has been extended to 2021 there is still a lot of interest in the use of sintered Ag in semiconductor die attach because it can survive the higher operating temperatures of more advanced SiC and GaAs power semiconductors. The demand for these advanced higher efficiency power semiconductors is expected to increase as electric and hybrid vehicles, renewable energy and smart electricity grids are more widely adopted and this provides further justification for the development of sintered Ag bonding technology. One of the advantages of sintered Ag is that it can form a joint at temperatures comparable with those used in die attach with high-Pb solder but once the process is completed will not melt until the temperature exceeds the 961°C melting point of Ag. In this paper, the authors report the results of power cycling of insulated-gate bipolar transistor (IGBT) semiconductors built using two variants of Ag sintering paste with a range of process parameters with the intention of determining the sensitivity of the bond life to such variations. Included in the experimental program as benchmarks are semiconductors built with conventional Pb-5Sn alloy and Pb-free alloy, SAC305. The semiconductor subjected to power cycling were subsequently subjected to examination by confocal scanning acoustic microscopy (CSAM) and cross-sectioning and scanning electron microscopy to determine the failure mechanisms. No fatigue cracks were observed in the sintered Ag joint regardless type of Ag sintering material used and the processing parameters. The dominant failure mechanism in the sintered Ag bonds was delamination. In the benchmark bonding materials, Pb5Sn and SAC305, classic solder fatigue failure appeared to be the dominant failure mechanism.","PeriodicalId":414232,"journal":{"name":"2017 IEEE 19th Electronics Packaging Technology Conference (EPTC)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123219135","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/EPTC.2017.8277518
Patrik Carazzetti, F. Balon, M. Hoffmann, J. Weichart, A. Erhart, Ewald Strolz
This work analyzes the key performance of two different multi-chamber PVD systems used in volume WLP manufacturing. These are the Cluster-type and the Indexer-type platforms, respectively. It is emphasized how the faster wafer handling, which is a unique characteristic of the Indexer concept, results in throughput of production flows exceeding 50 wafers/hour. Moreover, the strategies of degas, cooling and sputter-etch implemented in the process-of-records executed by Indexer allow for wafer processing at lower temperature regimes and result in 50% lower contact resistance baseline. This work reports Rc values well below 1.0 mOhm measured on single-contact Kelvin structures. The Indexer system presented promotes itself as the ideal high-productivity PVD platform capable to tackle the ever-increasing manufacturing challenges arising from the progressive shrinkage of the critical device dimensions of next-generation WLCSP and FOWLP.
{"title":"Indexer PVD platform — The key enabler for high productivity and low contact resistance for next-generation WLP applications","authors":"Patrik Carazzetti, F. Balon, M. Hoffmann, J. Weichart, A. Erhart, Ewald Strolz","doi":"10.1109/EPTC.2017.8277518","DOIUrl":"https://doi.org/10.1109/EPTC.2017.8277518","url":null,"abstract":"This work analyzes the key performance of two different multi-chamber PVD systems used in volume WLP manufacturing. These are the Cluster-type and the Indexer-type platforms, respectively. It is emphasized how the faster wafer handling, which is a unique characteristic of the Indexer concept, results in throughput of production flows exceeding 50 wafers/hour. Moreover, the strategies of degas, cooling and sputter-etch implemented in the process-of-records executed by Indexer allow for wafer processing at lower temperature regimes and result in 50% lower contact resistance baseline. This work reports Rc values well below 1.0 mOhm measured on single-contact Kelvin structures. The Indexer system presented promotes itself as the ideal high-productivity PVD platform capable to tackle the ever-increasing manufacturing challenges arising from the progressive shrinkage of the critical device dimensions of next-generation WLCSP and FOWLP.","PeriodicalId":414232,"journal":{"name":"2017 IEEE 19th Electronics Packaging Technology Conference (EPTC)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123226845","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/EPTC.2017.8277544
O. Yauw, Jie Wu, Andrew Tan, I. Qin, Aashish Shah, J. Yang, G. Schulze
Vertical stacking of thin die in memory packages as tall as 16 layers and 32 layers is common in high volume production. 3D NAND flash memory makers are also announcing and realizing their production ramps for 64 layers. 3D die stacking enables device integration flexibility and enhancements in electrical performance. Thinner package requirements drive die thicknesses to below 25um. Assembly equipment manufacturers utilize state of the art thin wafer technologies in areas of wafer backgrinding, dicing, wafer handling, thin die attach and stacking, wire bonding on thin overhang die, and wire looping motions for ultra low loops. Material suppliers are developing materials to accompany these latest equipment advancements. Low adhesion wafer tape to ease thin die picking, thin Die Attach Film (DAF) going below 10um thickness, and ultra fine bonding wire at 0.6mil and less, are some of the examples. In this paper, we will focus on two areas: 1) thin die attachment up to 16 layers with die thicknesses of 15um and 25um, and DAF thicknesses of 5um and 10um, and 2) wire bonding on thin and overhanging die stacks. Finite element modelling indicating stress distribution on the die during thin die picking in die attach and overhang wire bonding, will be discussed and used as the basis of developing solutions to overcome die cracks and inconsistent bond qualities. These solutions include thin die tooling designs, pick processes for die attach, wire bonding processes on thin die with long overhang distance, and ultra low loop processes involving long inboard wire length and high die stack height.
{"title":"Leading edge die stacking and wire bonding technologies for advanced 3D memory packages","authors":"O. Yauw, Jie Wu, Andrew Tan, I. Qin, Aashish Shah, J. Yang, G. Schulze","doi":"10.1109/EPTC.2017.8277544","DOIUrl":"https://doi.org/10.1109/EPTC.2017.8277544","url":null,"abstract":"Vertical stacking of thin die in memory packages as tall as 16 layers and 32 layers is common in high volume production. 3D NAND flash memory makers are also announcing and realizing their production ramps for 64 layers. 3D die stacking enables device integration flexibility and enhancements in electrical performance. Thinner package requirements drive die thicknesses to below 25um. Assembly equipment manufacturers utilize state of the art thin wafer technologies in areas of wafer backgrinding, dicing, wafer handling, thin die attach and stacking, wire bonding on thin overhang die, and wire looping motions for ultra low loops. Material suppliers are developing materials to accompany these latest equipment advancements. Low adhesion wafer tape to ease thin die picking, thin Die Attach Film (DAF) going below 10um thickness, and ultra fine bonding wire at 0.6mil and less, are some of the examples. In this paper, we will focus on two areas: 1) thin die attachment up to 16 layers with die thicknesses of 15um and 25um, and DAF thicknesses of 5um and 10um, and 2) wire bonding on thin and overhanging die stacks. Finite element modelling indicating stress distribution on the die during thin die picking in die attach and overhang wire bonding, will be discussed and used as the basis of developing solutions to overcome die cracks and inconsistent bond qualities. These solutions include thin die tooling designs, pick processes for die attach, wire bonding processes on thin die with long overhang distance, and ultra low loop processes involving long inboard wire length and high die stack height.","PeriodicalId":414232,"journal":{"name":"2017 IEEE 19th Electronics Packaging Technology Conference (EPTC)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127028340","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/EPTC.2017.8277580
Yongdian Han, Siming Zhang, H. Jing, Jun Wei, F. H. Bu, Lei Zhao, X. Lv, Lianyong Xu
With the aim of developing highly conductive ink for writing electronics on heat-sensitive substrates, Ag nanospheres and nanoplates were mixed to synthesize hybrid inks. Five kinds of hybrid ink and two types of pure ink were written to square shape on Epson photo paper using rollerball pens and sintered at a low temperature (100 V). The microstructure, electrical resistivity, surface porosity, hardness and flexibility of silver patterns were systematically investigated and compared. It was observed that the optimal mixing ratio of nanospheres and nanoplates was 1:1, which equipped the directly written pattern with excellent electrical and mechanical properties. The electrical resistivity was 0.103 μΩ·m, which was only 6.5 times of bulk silver. The enhancement compared to pure silver nanospheres or nanoplates based ink was owing to the combined action of nanospheres and nanoplates. It was a valued way to prepare Ag nanoink with good performance for printed/written electronics.
{"title":"Ag nanoparticles — Based hybrid Ink with low metallization temperature","authors":"Yongdian Han, Siming Zhang, H. Jing, Jun Wei, F. H. Bu, Lei Zhao, X. Lv, Lianyong Xu","doi":"10.1109/EPTC.2017.8277580","DOIUrl":"https://doi.org/10.1109/EPTC.2017.8277580","url":null,"abstract":"With the aim of developing highly conductive ink for writing electronics on heat-sensitive substrates, Ag nanospheres and nanoplates were mixed to synthesize hybrid inks. Five kinds of hybrid ink and two types of pure ink were written to square shape on Epson photo paper using rollerball pens and sintered at a low temperature (100 V). The microstructure, electrical resistivity, surface porosity, hardness and flexibility of silver patterns were systematically investigated and compared. It was observed that the optimal mixing ratio of nanospheres and nanoplates was 1:1, which equipped the directly written pattern with excellent electrical and mechanical properties. The electrical resistivity was 0.103 μΩ·m, which was only 6.5 times of bulk silver. The enhancement compared to pure silver nanospheres or nanoplates based ink was owing to the combined action of nanospheres and nanoplates. It was a valued way to prepare Ag nanoink with good performance for printed/written electronics.","PeriodicalId":414232,"journal":{"name":"2017 IEEE 19th Electronics Packaging Technology Conference (EPTC)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122025319","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/EPTC.2017.8277481
A. Denoyo, A. Tan, J. Berte, Robert Altar
A reliable green packaging solution that can withstand the Pb-free 260°C reflow requirement during actual board mount assembly while maintaining its existing moisture sensitivity level (MSL) classification, is now a must in the semiconductor industry. And given with the said requirement, various improvements were considered such as process and material changes just to ensure improved adhesion between different material interfaces. External lead finish options includes the use of pure tin or Pre-Plated Frames (PPF) — the nickel-palladium-gold/silver (NiPdAu/Ag), but the PPF option is preferred to prevent leadframe oxidation, support factory automation and cycle time reduction. Thus, the objective of the study is to investigate the effect and behavior of the pre-plated frames with different surface finish morphologies on how it affects and improves the adhesion between the mold-leadframe interfaces thereby reducing if not eliminating the delamination seen after moisture soak. Per investigation, results showed roughening indeed improves the adhesion achieving MSL 1 without any form of delamination seen in all interface. Furthermore, the occurrence of delamination on the molded unit is very much dependent on the type or level of roughness of the material used.
{"title":"Moisture sensitivity level one (1) packaging solution for a nickel-palladium-gold (NiPdAu) Pre-Plated frames","authors":"A. Denoyo, A. Tan, J. Berte, Robert Altar","doi":"10.1109/EPTC.2017.8277481","DOIUrl":"https://doi.org/10.1109/EPTC.2017.8277481","url":null,"abstract":"A reliable green packaging solution that can withstand the Pb-free 260°C reflow requirement during actual board mount assembly while maintaining its existing moisture sensitivity level (MSL) classification, is now a must in the semiconductor industry. And given with the said requirement, various improvements were considered such as process and material changes just to ensure improved adhesion between different material interfaces. External lead finish options includes the use of pure tin or Pre-Plated Frames (PPF) — the nickel-palladium-gold/silver (NiPdAu/Ag), but the PPF option is preferred to prevent leadframe oxidation, support factory automation and cycle time reduction. Thus, the objective of the study is to investigate the effect and behavior of the pre-plated frames with different surface finish morphologies on how it affects and improves the adhesion between the mold-leadframe interfaces thereby reducing if not eliminating the delamination seen after moisture soak. Per investigation, results showed roughening indeed improves the adhesion achieving MSL 1 without any form of delamination seen in all interface. Furthermore, the occurrence of delamination on the molded unit is very much dependent on the type or level of roughness of the material used.","PeriodicalId":414232,"journal":{"name":"2017 IEEE 19th Electronics Packaging Technology Conference (EPTC)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126779612","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/EPTC.2017.8277508
Ming-Han Wang, Ian Hu, RichardYC Chen, Chang-Lin Yeh, M. Shih, D. Tarng
SiP modules, integrates multi-function components in a package, are widely applied in consumer electronics and IoT, such as Wifi module, GPS module and RF module, etc. Dual side molding module is a more advanced device type, who integrate all the components on the both surfaces of the substrate to effectively reduce the module area. By process strip warpage control is one of the crucial matters for assembly in order to have good yield and high automatic manufacture efficiency. Finite element method is a powerful tool for strip warpage evaluation; however, dual side SiP module strip requires enormous elements to describe its details. A useful model simplification method was proposed in this study. The several layers substrate was simplified as a homogeneous material by numerical tensile and thermal expansion tests to obtain the substrate bulk material properties of modulus and thermal expansion coefficient. The simplified substrate not only helps for efficiency computing, but also can be a transition zone for the different component layout of top and bottom substrate surfaces successfully mesh in the simulation model. Birth and death method was used to investigate by process strip warpage, the evaluation results help to reduce the risk comes from strip warpage. According to the well validated simulation model, for process improvement, firstly SMT and molding top side has better performance for strip warpage; for EMC improvement, bottom side choose high shrinkage EMC or top side select low shrinkage EMC can well control strip warpage.
{"title":"Strip warpage assessment of dual side molding SiP module","authors":"Ming-Han Wang, Ian Hu, RichardYC Chen, Chang-Lin Yeh, M. Shih, D. Tarng","doi":"10.1109/EPTC.2017.8277508","DOIUrl":"https://doi.org/10.1109/EPTC.2017.8277508","url":null,"abstract":"SiP modules, integrates multi-function components in a package, are widely applied in consumer electronics and IoT, such as Wifi module, GPS module and RF module, etc. Dual side molding module is a more advanced device type, who integrate all the components on the both surfaces of the substrate to effectively reduce the module area. By process strip warpage control is one of the crucial matters for assembly in order to have good yield and high automatic manufacture efficiency. Finite element method is a powerful tool for strip warpage evaluation; however, dual side SiP module strip requires enormous elements to describe its details. A useful model simplification method was proposed in this study. The several layers substrate was simplified as a homogeneous material by numerical tensile and thermal expansion tests to obtain the substrate bulk material properties of modulus and thermal expansion coefficient. The simplified substrate not only helps for efficiency computing, but also can be a transition zone for the different component layout of top and bottom substrate surfaces successfully mesh in the simulation model. Birth and death method was used to investigate by process strip warpage, the evaluation results help to reduce the risk comes from strip warpage. According to the well validated simulation model, for process improvement, firstly SMT and molding top side has better performance for strip warpage; for EMC improvement, bottom side choose high shrinkage EMC or top side select low shrinkage EMC can well control strip warpage.","PeriodicalId":414232,"journal":{"name":"2017 IEEE 19th Electronics Packaging Technology Conference (EPTC)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123921339","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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