Virtualization has become a very important technology which has been adopted in many enterprise computing systems and data centers. Virtualization makes resource management and maintenance easier, and can decrease energy consumption through resource consolidation. To develop and employ sophisticated resource management, accurate power and performance models of the hardware resources in a virtualized environment are needed. Based on extensive experiments and measurements, this paper presents accurate power and performance models for a high performance multi-core server system with virtualization.
{"title":"Power and Performance Modeling in a Virtualized Server System","authors":"Massoud Pedram, Inkwon Hwang","doi":"10.1109/ICPPW.2010.76","DOIUrl":"https://doi.org/10.1109/ICPPW.2010.76","url":null,"abstract":"Virtualization has become a very important technology which has been adopted in many enterprise computing systems and data centers. Virtualization makes resource management and maintenance easier, and can decrease energy consumption through resource consolidation. To develop and employ sophisticated resource management, accurate power and performance models of the hardware resources in a virtualized environment are needed. Based on extensive experiments and measurements, this paper presents accurate power and performance models for a high performance multi-core server system with virtualization.","PeriodicalId":415472,"journal":{"name":"2010 39th International Conference on Parallel Processing Workshops","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126681378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
It is imperative to consider the concept of sustainable portable computing as the role of such devices increases our lives. With the emergence of the cloud computing paradigm, there will be an increased reliance on wireless communication from portable computing devices to more powerful centralized servers. This paradigm shift to `thin-clients' presents an opportunity to make portable computing more sustainable by shifting more functionality to centralized servers. Reduced functionality needed on these devices could mean a slower rate of hardware replacement. This could significantly cut the electronic waste that is currently attributed to the frequent replacements of these devices. One of the challenges in such a paradigm shift to thin portable clients through reduced local computation would be the additional burden imposed on the wireless communication technologies used. Wireless communication technologies must be improved to handle the additional burden that will be imposed. Any proposed wireless technology must also be energy-efficient to maximize the operating life time of these battery operated, energy-constrained devices. Software approaches to achieve energy-efficient operation are preferable as they reduce the dumping of existing hardware due to upgrades or replacements, and help reduce electronic waste. This paper discusses these challenges and describes one way to move forward towards sustainable portable computing by considering application scenarios based on cloud computing and communication through software-defined cognitive radios.
{"title":"Towards Sustainability in Portable Computing through Cloud Computing and Cognitive Radios","authors":"V. Namboodiri","doi":"10.1109/ICPPW.2010.69","DOIUrl":"https://doi.org/10.1109/ICPPW.2010.69","url":null,"abstract":"It is imperative to consider the concept of sustainable portable computing as the role of such devices increases our lives. With the emergence of the cloud computing paradigm, there will be an increased reliance on wireless communication from portable computing devices to more powerful centralized servers. This paradigm shift to `thin-clients' presents an opportunity to make portable computing more sustainable by shifting more functionality to centralized servers. Reduced functionality needed on these devices could mean a slower rate of hardware replacement. This could significantly cut the electronic waste that is currently attributed to the frequent replacements of these devices. One of the challenges in such a paradigm shift to thin portable clients through reduced local computation would be the additional burden imposed on the wireless communication technologies used. Wireless communication technologies must be improved to handle the additional burden that will be imposed. Any proposed wireless technology must also be energy-efficient to maximize the operating life time of these battery operated, energy-constrained devices. Software approaches to achieve energy-efficient operation are preferable as they reduce the dumping of existing hardware due to upgrades or replacements, and help reduce electronic waste. This paper discusses these challenges and describes one way to move forward towards sustainable portable computing by considering application scenarios based on cloud computing and communication through software-defined cognitive radios.","PeriodicalId":415472,"journal":{"name":"2010 39th International Conference on Parallel Processing Workshops","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133167439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Previous research has demonstrated the potential benefits of thermal aware load placement and thermal mapping in cool-intensive environments such as data centers. However, it has proved difficult to apply existing techniques to live data centers because of models that are either unrealistic, require extensive sensing instrumentation, or because their creation is disruptive to the data center services. The work presented in this paper discusses techniques and their associated challenges with respect to creating an adaptive and non-invasive method of creating realistic and low-complexity thermal models using built-in and ambient sensors. Uses of these techniques can vary from assessing the thermal efficiency of the data center to designing a thermal-aware job scheduler to lower total cost of ownership (TCO). Specifically, this paper proposes: i) a non-invasive thermal modeling software architecture that uses on-board, ambient and software sensors ii) and four different ways of leveraging the gathered data from an experimental application of the architecture to improve the greenness of the data center and our understanding of the thermal behavior of a data center.
{"title":"Non-invasive Thermal Modeling Techniques Using Ambient Sensors for Greening Data Centers","authors":"Michael Jonas, G. Varsamopoulos, S. Gupta","doi":"10.1109/ICPPW.2010.67","DOIUrl":"https://doi.org/10.1109/ICPPW.2010.67","url":null,"abstract":"Previous research has demonstrated the potential benefits of thermal aware load placement and thermal mapping in cool-intensive environments such as data centers. However, it has proved difficult to apply existing techniques to live data centers because of models that are either unrealistic, require extensive sensing instrumentation, or because their creation is disruptive to the data center services. The work presented in this paper discusses techniques and their associated challenges with respect to creating an adaptive and non-invasive method of creating realistic and low-complexity thermal models using built-in and ambient sensors. Uses of these techniques can vary from assessing the thermal efficiency of the data center to designing a thermal-aware job scheduler to lower total cost of ownership (TCO). Specifically, this paper proposes: i) a non-invasive thermal modeling software architecture that uses on-board, ambient and software sensors ii) and four different ways of leveraging the gathered data from an experimental application of the architecture to improve the greenness of the data center and our understanding of the thermal behavior of a data center.","PeriodicalId":415472,"journal":{"name":"2010 39th International Conference on Parallel Processing Workshops","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133907978","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Understanding and tuning the performance of complex applications on modern hardware are challenging tasks, requiring understanding of the algorithms, implementation, compiler optimizations, and underlying architecture. Many tools exist for measuring and analyzing the runtime performance of applications. Obtaining sufficiently detailed performance data and comparing it with the peak performance of an architecture are one path to understanding the behavior of a particular algorithm implementation. A complementary approach relies on the analysis of the source code itself, coupling it with a simplified architecture description to arrive at performance estimates that can provide a more meaningful upper bound than the peak hardware performance. We present a tool for estimating upper performance bounds of C/C++ applications through static compiler analysis. It generates parameterized expressions for different types of memory accesses and integer and floating-point computations. We then incorporate architectural parameters to estimate upper bounds on the performance of an application on a particular system. We present validation results for several codes on two architectures.
{"title":"Generating Performance Bounds from Source Code","authors":"S. Narayanan, B. Norris, P. Hovland","doi":"10.1109/ICPPW.2010.37","DOIUrl":"https://doi.org/10.1109/ICPPW.2010.37","url":null,"abstract":"Understanding and tuning the performance of complex applications on modern hardware are challenging tasks, requiring understanding of the algorithms, implementation, compiler optimizations, and underlying architecture. Many tools exist for measuring and analyzing the runtime performance of applications. Obtaining sufficiently detailed performance data and comparing it with the peak performance of an architecture are one path to understanding the behavior of a particular algorithm implementation. A complementary approach relies on the analysis of the source code itself, coupling it with a simplified architecture description to arrive at performance estimates that can provide a more meaningful upper bound than the peak hardware performance. We present a tool for estimating upper performance bounds of C/C++ applications through static compiler analysis. It generates parameterized expressions for different types of memory accesses and integer and floating-point computations. We then incorporate architectural parameters to estimate upper bounds on the performance of an application on a particular system. We present validation results for several codes on two architectures.","PeriodicalId":415472,"journal":{"name":"2010 39th International Conference on Parallel Processing Workshops","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121918244","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
C. Olschanowsky, A. Snavely, Mitesh R. Meswani, L. Carrington
The speed of the memory subsystem often constrains the performance of large-scale parallel applications. Experts tune such applications to use hierarchical memory subsystems efficiently. Hardware accelerators, such as GPUs, can potentially improve memory performance beyond the capabilities of traditional hierarchical systems. However, the addition of such specialized hardware complicates code porting and tuning. During porting and tuning expert application engineers manually browse source code and identify memory access patterns that are candidates for optimization and tuning. HPC applications typically contain thousands to hundreds of thousands of lines of code, creating a labor-intensive challenge for the expert. PIR, PMaC’s Static Idiom Recognizer, automates the pattern recognition process. PIR recognizes specified patterns and tags the source code where they appear using static analysis. This paper describes the PIR implementation and defines a subset of idioms commonly found in HPC applications. We examine the effectiveness of the tool, demonstrating 95% identification accuracy and present the results of using PIR on two HPC applications.
{"title":"PIR: PMaC's Idiom Recognizer","authors":"C. Olschanowsky, A. Snavely, Mitesh R. Meswani, L. Carrington","doi":"10.1109/ICPPW.2010.36","DOIUrl":"https://doi.org/10.1109/ICPPW.2010.36","url":null,"abstract":"The speed of the memory subsystem often constrains the performance of large-scale parallel applications. Experts tune such applications to use hierarchical memory subsystems efficiently. Hardware accelerators, such as GPUs, can potentially improve memory performance beyond the capabilities of traditional hierarchical systems. However, the addition of such specialized hardware complicates code porting and tuning. During porting and tuning expert application engineers manually browse source code and identify memory access patterns that are candidates for optimization and tuning. HPC applications typically contain thousands to hundreds of thousands of lines of code, creating a labor-intensive challenge for the expert. PIR, PMaC’s Static Idiom Recognizer, automates the pattern recognition process. PIR recognizes specified patterns and tags the source code where they appear using static analysis. This paper describes the PIR implementation and defines a subset of idioms commonly found in HPC applications. We examine the effectiveness of the tool, demonstrating 95% identification accuracy and present the results of using PIR on two HPC applications.","PeriodicalId":415472,"journal":{"name":"2010 39th International Conference on Parallel Processing Workshops","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116732248","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Xin Liu, Jingyu Zhou, Daqiang Zhang, Yao Shen, M. Guo
Many SoCs adopt multicore architectures. As a result, embedded programmers are also facing the challenge of parallel programming. We propose a parallel skeleton library that can be used on embedded multicores. Our library is implemented in standard C++ using template features. We propose two parallel skeletons to support common program patterns on multicores. In our skeleton library, programmers can easily choose underlying parallel implementations with no code changes. Experimental results show that many applications can take advantage of these two skeletons for performance improvement, sometimes better than hand-parallelized code.
{"title":"A Parallel Skeleton Library for Embedded Multicores","authors":"Xin Liu, Jingyu Zhou, Daqiang Zhang, Yao Shen, M. Guo","doi":"10.1109/ICPPW.2010.21","DOIUrl":"https://doi.org/10.1109/ICPPW.2010.21","url":null,"abstract":"Many SoCs adopt multicore architectures. As a result, embedded programmers are also facing the challenge of parallel programming. We propose a parallel skeleton library that can be used on embedded multicores. Our library is implemented in standard C++ using template features. We propose two parallel skeletons to support common program patterns on multicores. In our skeleton library, programmers can easily choose underlying parallel implementations with no code changes. Experimental results show that many applications can take advantage of these two skeletons for performance improvement, sometimes better than hand-parallelized code.","PeriodicalId":415472,"journal":{"name":"2010 39th International Conference on Parallel Processing Workshops","volume":"293 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116568000","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
When stricken by a catastrophic natural disaster, the efficiency of disaster response operation is very critical to life saving. However, communication systems, including cellular networks, were usually crashed due to various causes making the coordination among a large number of disorganized disaster response workers extremely difficult. Unfortunately, rapid deployment of many existing emergency communication systems relies on a good transportation system, which is usually not available in a catastrophic natural disaster. We designed a multi-hop walkie-talkie-like communication system based on P2Pnet platform, which is a MANET P2P network constructed using volunteers’ laptops. This system can support a large number of voluntary workers in the early hours of a catastrophic natural disaster when external assistance is blocked by the paralyzed transportation system. The multi-hop version can help to bypass the obstacles that block face-to-face communication as well as direct WiFi communication links. We wish to stimulate the research on the emergency communication systems that is inexpensive and easy to deploy for future catastrophic natural disasters.
{"title":"A Multi-hop Walkie-Talkie-Like Emergency Communication System for Catastrophic Natural Disasters","authors":"Y. Lien, Li-Cheng Chi, Chih-Chieh Huang","doi":"10.1109/ICPPW.2010.77","DOIUrl":"https://doi.org/10.1109/ICPPW.2010.77","url":null,"abstract":"When stricken by a catastrophic natural disaster, the efficiency of disaster response operation is very critical to life saving. However, communication systems, including cellular networks, were usually crashed due to various causes making the coordination among a large number of disorganized disaster response workers extremely difficult. Unfortunately, rapid deployment of many existing emergency communication systems relies on a good transportation system, which is usually not available in a catastrophic natural disaster. We designed a multi-hop walkie-talkie-like communication system based on P2Pnet platform, which is a MANET P2P network constructed using volunteers’ laptops. This system can support a large number of voluntary workers in the early hours of a catastrophic natural disaster when external assistance is blocked by the paralyzed transportation system. The multi-hop version can help to bypass the obstacles that block face-to-face communication as well as direct WiFi communication links. We wish to stimulate the research on the emergency communication systems that is inexpensive and easy to deploy for future catastrophic natural disasters.","PeriodicalId":415472,"journal":{"name":"2010 39th International Conference on Parallel Processing Workshops","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114824566","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Intrusion detection is one of the most important services in a smart home, which requires to monitor intrusion events and to react against them. A Wireless Sensor and Actor Network (WSAN) has a set of sensor nodes for monitoring events and a set of high capability nodes, called actor nodes, for reacting to the events. It can provide an infrastructure for building the intrusion detection system in a smart home. We need to jointly consider fault-tolerance and timeliness issues because sensor nodes are likely to be influenced by failures (e.g., dead battery) and need to deliver packets in real time over wireless links vulnerable to interference caused by walls, floors or furniture. In this paper, we propose Optimal Multipath Planning (or OMP), which is based on Edmonds-Karp maximum flow algorithm and Goldberg and Tarjan minimum cost flow algorithm, for WSANs to set up paths to deliver intrusion event notification from event sources to actors in a smart home. The planning is optimal in the sense that it sets up the maximum number of node-disjoint paths of links with the minimized expected transmission count (ETX). We also evaluate OMP’s performance by simulations and compare it with the minimum cost planning using Dijkstra algorithm to show its advantages.
入侵检测是智能家居中最重要的服务之一，它需要监控入侵事件并对其做出反应。无线传感器和参与者网络(WSAN)具有一组用于监视事件的传感器节点和一组用于对事件作出反应的高性能节点(称为参与者节点)。它可以为智能家居中入侵检测系统的构建提供基础设施。我们需要共同考虑容错和及时性问题，因为传感器节点很可能受到故障(例如，电池耗尽)的影响，并且需要通过易受墙壁、地板或家具干扰的无线链路实时传输数据包。本文提出了基于Edmonds-Karp最大流算法和Goldberg and Tarjan最小成本流算法的最优多路径规划(OMP)，用于WSANs建立路径，将入侵事件通知从事件源传递到智能家居中的参与者。该规划是最优的，因为它以最小的期望传输计数(ETX)建立了最大数量的节点不相交的链路路径。我们还通过仿真评估了OMP的性能，并将其与使用Dijkstra算法的最小成本规划进行了比较，以显示其优势。
{"title":"Optimal Multipath Planning for Intrusion Detection in Smart Homes Using Wireless Sensor and Actor Networks","authors":"Yung-Liang Lai, Jehn-Ruey Jiang","doi":"10.1109/ICPPW.2010.83","DOIUrl":"https://doi.org/10.1109/ICPPW.2010.83","url":null,"abstract":"Intrusion detection is one of the most important services in a smart home, which requires to monitor intrusion events and to react against them. A Wireless Sensor and Actor Network (WSAN) has a set of sensor nodes for monitoring events and a set of high capability nodes, called actor nodes, for reacting to the events. It can provide an infrastructure for building the intrusion detection system in a smart home. We need to jointly consider fault-tolerance and timeliness issues because sensor nodes are likely to be influenced by failures (e.g., dead battery) and need to deliver packets in real time over wireless links vulnerable to interference caused by walls, floors or furniture. In this paper, we propose Optimal Multipath Planning (or OMP), which is based on Edmonds-Karp maximum flow algorithm and Goldberg and Tarjan minimum cost flow algorithm, for WSANs to set up paths to deliver intrusion event notification from event sources to actors in a smart home. The planning is optimal in the sense that it sets up the maximum number of node-disjoint paths of links with the minimized expected transmission count (ETX). We also evaluate OMP’s performance by simulations and compare it with the minimum cost planning using Dijkstra algorithm to show its advantages.","PeriodicalId":415472,"journal":{"name":"2010 39th International Conference on Parallel Processing Workshops","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123044081","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a Tabu search based approach for the topology synthesis of application-specific multicore architectures using an automated design technique. The Tabu search method incorporates multiple objectives in order to generate an optimal NoC topology which accounts for both power and performance factors. The method generates a system-level floorplan in each major stage of the topology synthesis. By incorporating the floorplan information, it is possible to attain accurate values for power consumption of the routers and physical links, as well as manage the interconnections within the system. The technique also includes a contention analyzer that assesses performance and omits any potential bottlenecks. The contention analyzer uses a Layered Queuing Network approach to model the rendezvous interactions amongst system components. Several experiments are conducted using various SoC benchmark applications to compare the power and performance outcomes of the proposed technique.
{"title":"Power and Performance Tabu Search Based Multicore Network-on-Chip Design","authors":"A. Tino, G. Khan","doi":"10.1109/ICPPW.2010.22","DOIUrl":"https://doi.org/10.1109/ICPPW.2010.22","url":null,"abstract":"This paper presents a Tabu search based approach for the topology synthesis of application-specific multicore architectures using an automated design technique. The Tabu search method incorporates multiple objectives in order to generate an optimal NoC topology which accounts for both power and performance factors. The method generates a system-level floorplan in each major stage of the topology synthesis. By incorporating the floorplan information, it is possible to attain accurate values for power consumption of the routers and physical links, as well as manage the interconnections within the system. The technique also includes a contention analyzer that assesses performance and omits any potential bottlenecks. The contention analyzer uses a Layered Queuing Network approach to model the rendezvous interactions amongst system components. Several experiments are conducted using various SoC benchmark applications to compare the power and performance outcomes of the proposed technique.","PeriodicalId":415472,"journal":{"name":"2010 39th International Conference on Parallel Processing Workshops","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124428733","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
V. Srinivasan, N. Parihar, Vivek Khurana, Ada Gavrilovska
Embedded platforms are becoming increasingly more resource-rich (e.g. processing speeds, number of cores, memory, and communication rates). As a result, they are being transformed from `closed', fixed-function devices to programmable and flexible platforms capable of supporting diverse types of services. One approach to enabling service diversity jointly with proper isolation of key critical functionality is to leverage platform virtualization technology. Toward this end, this paper first describes an approach to virtualizing System-on-a-Chip (SoC) platforms, and next explores the opportunities for shared use of such virtualized SoC devices by multiple concurrently executing services. The research is conducted on the Intel Tolapai SoC which integrates an x86 core with a crypto accelerator, and using the Xen hypervisor.
{"title":"A Split Driver Approach to Soc Virtualization - Challenges and Opportunities","authors":"V. Srinivasan, N. Parihar, Vivek Khurana, Ada Gavrilovska","doi":"10.1109/ICPPW.2010.19","DOIUrl":"https://doi.org/10.1109/ICPPW.2010.19","url":null,"abstract":"Embedded platforms are becoming increasingly more resource-rich (e.g. processing speeds, number of cores, memory, and communication rates). As a result, they are being transformed from `closed', fixed-function devices to programmable and flexible platforms capable of supporting diverse types of services. One approach to enabling service diversity jointly with proper isolation of key critical functionality is to leverage platform virtualization technology. Toward this end, this paper first describes an approach to virtualizing System-on-a-Chip (SoC) platforms, and next explores the opportunities for shared use of such virtualized SoC devices by multiple concurrently executing services. The research is conducted on the Intel Tolapai SoC which integrates an x86 core with a crypto accelerator, and using the Xen hypervisor.","PeriodicalId":415472,"journal":{"name":"2010 39th International Conference on Parallel Processing Workshops","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114879625","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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