Pub Date : 2019-01-01DOI: 10.31838/ijccts/05.02.05
{"title":"Dynamic Smart Alert Service for Women Safety System ","authors":"","doi":"10.31838/ijccts/05.02.05","DOIUrl":"https://doi.org/10.31838/ijccts/05.02.05","url":null,"abstract":"","PeriodicalId":415674,"journal":{"name":"International Journal of communication and computer Technologies","volume":"314 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115868266","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-01-01DOI: 10.31838/ijccts/07.02.03
R. Denicashelus, B.Deebikaa, S.Hariram
Today's technology is improved to a greater extent for the betterment of people, but there are some people with disabilities like blindness. In order to overcome their problem a smart stick is designed with GPS-GSM module, ultrasonic sensor that would help them in their way to identify obstacle. Ultrasonic sensors calculate the distance of the obstacles around the visually impaired person to guide the user towards the necessary path. This paper describes about how each components would help them. This also helps to find the stick if it is lost. The tool says that, the smart walking stick that alerts visually-impaired persons over obstacles, fire, and water and could help them in walking with less accident.
{"title":"EMBEDDED ASSISTIVE STICK FOR VISUALLY IMPAIRED PEOPLE","authors":"R. Denicashelus, B.Deebikaa, S.Hariram","doi":"10.31838/ijccts/07.02.03","DOIUrl":"https://doi.org/10.31838/ijccts/07.02.03","url":null,"abstract":"Today's technology is improved to a greater extent for the betterment of people, but there are some people with \u0000disabilities like blindness. In order to overcome their problem a smart stick is designed with GPS-GSM module, \u0000ultrasonic sensor that would help them in their way to identify obstacle. Ultrasonic sensors calculate the distance \u0000of the obstacles around the visually impaired person to guide the user towards the necessary path. This paper \u0000describes about how each components would help them. This also helps to find the stick if it is lost. The tool says \u0000that, the smart walking stick that alerts visually-impaired persons over obstacles, fire, and water and could help \u0000them in walking with less accident.","PeriodicalId":415674,"journal":{"name":"International Journal of communication and computer Technologies","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116042033","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-01-01DOI: 10.31838/ijccts/01.02.13
{"title":"VEBEK-Working & Functionalities ","authors":"","doi":"10.31838/ijccts/01.02.13","DOIUrl":"https://doi.org/10.31838/ijccts/01.02.13","url":null,"abstract":"","PeriodicalId":415674,"journal":{"name":"International Journal of communication and computer Technologies","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125008573","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-01-01DOI: 10.31838/ijccts/01.01.06
M. Nithya
Network security has always been an important issue and its application is ready to perform powerful pattern matching to protect against virus attacks, spam and Trojan horses. However, attacks such as spam, spyware, worms, viruses, and phishing target the application layer rather than the network layer. Therefore, traditional firewalls no longer provide enough protection. However, the solutions in the literature for firewalls are not scalable, and they do not address the difficulty of an antivirus. The goal is to provide a systematic virus detection software solution for network security for computer systems. Instead of placing entire matching patterns on a chip, our solution is based on an antivirus processor that works as much of the filtering information as possible onto a reference memory. The infrequently accessing off-reference data to make the matching mechanism scalable to large pattern sets. In the first stage, the filtering engine can filter out more than 93.1% of data as safe, using a merged shift table. Only 6.9% or less of potentially unsafe data must be precisely checked in the second stage by the exact-matching engine from off-reference memory. In addition to that Dual port BITCAM processing program is used along with the Exact Matching Engine and Bloom Filter process. This Dual port BITCAM processes next to the exact matching engine and bloom filter process. This Dual port BITCAM process is placed exclusively for obtaining higher throughput. To reduce the memory gap and to improve the performance, we also propose three algorithms are used: 1) a skipping algorithm; 2) a cache method; and 3) a prefetching mechanism.
{"title":"ADVANCE VIRUS DETECTION USING COMBINED TECHNIQUES OF PATTERN MATCHING AND DYNAMIC INSTRUCTION SEQUENCES ","authors":"M. Nithya","doi":"10.31838/ijccts/01.01.06","DOIUrl":"https://doi.org/10.31838/ijccts/01.01.06","url":null,"abstract":"Network security has always been an important issue and its application is ready to perform powerful pattern matching to protect against virus attacks, spam and Trojan horses. However, attacks such as spam, spyware, worms, viruses, and phishing target the application layer rather than the network layer. Therefore, traditional firewalls no longer provide enough protection. However, the solutions in the literature for firewalls are not scalable, and they do not address the difficulty of an antivirus. The goal is to provide a systematic virus detection software solution for network security for computer systems. Instead of placing entire matching patterns on a chip, our solution is based on an antivirus processor that works as much of the filtering information as possible onto a reference memory. The infrequently accessing off-reference data to make the matching mechanism scalable to large pattern sets. In the first stage, the filtering engine can filter out more than 93.1% of data as safe, using a merged shift table. Only 6.9% or less of potentially unsafe data must be precisely checked in the second stage by the exact-matching engine from off-reference memory. In addition to that Dual port BITCAM processing program is used along with the Exact Matching Engine and Bloom Filter process. This Dual port BITCAM processes next to the exact matching engine and bloom filter process. This Dual port BITCAM process is placed exclusively for obtaining higher throughput. To reduce the memory gap and to improve the performance, we also propose three algorithms are used: 1) a skipping algorithm; 2) a cache method; and 3) a prefetching mechanism.","PeriodicalId":415674,"journal":{"name":"International Journal of communication and computer Technologies","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129793150","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-01-01DOI: 10.31838/ijccts/07.sp01.08
R. Gokila, P. Arunkumar, S. Deepakkumar, Athul Ravi, S. Sakthivel
Intelligent mirrors, which continue the works today and will take its place in the future technology, provide both mirror and computer aided information services to its users.. The user command is recognized by Raspberry PI through the micro phone in the mirror, in-built microphone and speaker is used for communicate with the mirror. That mirror shows time, calendar, reminders and headlines.
{"title":"HOME AUTOMATION USING SMART MIRROR WITH RASPBERRY PI","authors":"R. Gokila, P. Arunkumar, S. Deepakkumar, Athul Ravi, S. Sakthivel","doi":"10.31838/ijccts/07.sp01.08","DOIUrl":"https://doi.org/10.31838/ijccts/07.sp01.08","url":null,"abstract":"Intelligent mirrors, which continue the works today and will take its place in the future technology, provide both \u0000mirror and computer aided information services to its users.. The user command is recognized by Raspberry PI \u0000through the micro phone in the mirror, in-built microphone and speaker is used for communicate with the mirror. \u0000That mirror shows time, calendar, reminders and headlines.","PeriodicalId":415674,"journal":{"name":"International Journal of communication and computer Technologies","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132247913","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-01-01DOI: 10.31838/ijccts/01.01.04
{"title":"A Reliable ATM Protocol and Comparative Analysis on Various Parameters with Other ATM Protocols ","authors":"","doi":"10.31838/ijccts/01.01.04","DOIUrl":"https://doi.org/10.31838/ijccts/01.01.04","url":null,"abstract":"","PeriodicalId":415674,"journal":{"name":"International Journal of communication and computer Technologies","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134475760","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-01-01DOI: 10.31838/ijccts/04.01.07
M. MangayarkarasiRVanitha, K. SakthivelRDr.Bharanitharan
Polygonal approximation detects a set of feature points on the boundary of a shape that constitute the vertices of the shape. In particular, shape representation by polygonal approximation has become a popular technique due to its easiness, locality and compression. This paper presents a survey of methods that detects a set of dominant points that constitute the boundary of a 2D digital planar curve with an iterative procedure and a comparison of the polygonal approximation algorithms on various shapes with varying number of dominant points is made along with the demerits of each of the techniques
{"title":"A Survey of suboptimal polygonal approximation methods ","authors":"M. MangayarkarasiRVanitha, K. SakthivelRDr.Bharanitharan","doi":"10.31838/ijccts/04.01.07","DOIUrl":"https://doi.org/10.31838/ijccts/04.01.07","url":null,"abstract":"Polygonal approximation detects a set of feature points on the boundary of a shape that constitute the vertices of the shape. In particular, shape representation by polygonal approximation has become a popular technique due to its easiness, locality and compression. This paper presents a survey of methods that detects a set of dominant points that constitute the boundary of a 2D digital planar curve with an iterative procedure and a comparison of the polygonal approximation algorithms on various shapes with varying number of dominant points is made along with the demerits of each of the techniques","PeriodicalId":415674,"journal":{"name":"International Journal of communication and computer Technologies","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124942154","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-01-01DOI: 10.31838/ijccts/05.02.08
S.Surender K.Venkatachalam and V.Gowrishankar
This paper describes a CMOS current-steering digital-to-analog converter with a full-swing output signal. In a Wireless system the quality of the communication link is main criteria, for great distance transmission it is necessary to convert analog signal into digital signal at input side, same as convert digital signal to analog signal at output side. In the Existing DAC, 6 Binary inputs to 63 thermometer-coded (unary) outputs will use 6-input NOR and NAND logic gate, and the timing delay of these gates are very different. As the clock rate rising, it will cause error decoding problems.so we propose the 6 to 63 thermometer decoder by 2 section decoding. There is two 3 to 7 thermometer decoder for column and row decoder. This scheme reduces the error decoding problems. A new scheme of the quaternary driver and an output current cell composed of both nMOS and pMOS.The nMOS operates from the power supply to the half of the supply. The pMOS operates independently from the half of the supply to the ground voltage. Then, the final output voltage is obtained through a multiplexer that is driven by a quaternary driver that selects the optimized current cell. The circuit is simulated using 180nm Complementary Metal-oxide Semiconductor technology at a power supply voltage of 3.0 V on Tanner tool and the power consumption is about 17.8 mW. The proposed Current Steering Digital to Analog converter are schematic using Tanner S-EDIT and simulation of the proposed work is done using Tanner TEDIT. The waveform analysis is done using Tanner W-EDIT software
{"title":"6-bit, 180nm Digital to Analog Converter (DAC) Using Tanner EDA Tool for Low Power Applications ","authors":"S.Surender K.Venkatachalam and V.Gowrishankar","doi":"10.31838/ijccts/05.02.08","DOIUrl":"https://doi.org/10.31838/ijccts/05.02.08","url":null,"abstract":"This paper describes a CMOS current-steering digital-to-analog converter with a full-swing output signal. In a Wireless system the quality of the communication link is main criteria, for great distance transmission it is necessary to convert analog signal into digital signal at input side, same as convert digital signal to analog signal at output side. In the Existing DAC, 6 Binary inputs to 63 thermometer-coded (unary) outputs will use 6-input NOR and NAND logic gate, and the timing delay of these gates are very different. As the clock rate rising, it will cause error decoding problems.so we propose the 6 to 63 thermometer decoder by 2 section decoding. There is two 3 to 7 thermometer decoder for column and row decoder. This scheme reduces the error decoding problems. A new scheme of the quaternary driver and an output current cell composed of both nMOS and pMOS.The nMOS operates from the power supply to the half of the supply. The pMOS operates independently from the half of the supply to the ground voltage. Then, the final output voltage is obtained through a multiplexer that is driven by a quaternary driver that selects the optimized current cell. The circuit is simulated using 180nm Complementary Metal-oxide Semiconductor technology at a power supply voltage of 3.0 V on Tanner tool and the power consumption is about 17.8 mW. The proposed Current Steering Digital to Analog converter are schematic using Tanner S-EDIT and simulation of the proposed work is done using Tanner TEDIT. The waveform analysis is done using Tanner W-EDIT software","PeriodicalId":415674,"journal":{"name":"International Journal of communication and computer Technologies","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130057378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-01-01DOI: 10.31838/ijccts/02.01.03
R. Saveetha
For many applications from the areas of cryptography and coding, finite field multiplication is the most resource and time consuming operation. In this paper, optimized high performance parallel GF(2 233 ) multipliers for an FPGA realization were designed and the time and area complexities were analyzed. One of the multipliers uses a new hybrid structure to implement the Karatsuba algorithm. For increasing performance, we make excessive use of pipelining and efficient control techniques and use a modern state-of-the-art FPGA technology. As a result we have, to our knowledge, the first hardware realization of sub quadratic arithmetic and currently the fastest and most efficient implementation of 233 bit finite field multipliers.
{"title":"Analysis on FPGA Designs of Parallel High Performance Multipliers ","authors":"R. Saveetha","doi":"10.31838/ijccts/02.01.03","DOIUrl":"https://doi.org/10.31838/ijccts/02.01.03","url":null,"abstract":"For many applications from the areas of cryptography and coding, finite field multiplication is the most resource and time consuming operation. In this paper, optimized high performance parallel GF(2 233 ) multipliers for an FPGA realization were designed and the time and area complexities were analyzed. One of the multipliers uses a new hybrid structure to implement the Karatsuba algorithm. For increasing performance, we make excessive use of pipelining and efficient control techniques and use a modern state-of-the-art FPGA technology. As a result we have, to our knowledge, the first hardware realization of sub quadratic arithmetic and currently the fastest and most efficient implementation of 233 bit finite field multipliers.","PeriodicalId":415674,"journal":{"name":"International Journal of communication and computer Technologies","volume":"58 7-8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130584624","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：