René Noël, G. Valdés, Marcello Visconti, H. Astudillo
Extreme programming (XP) suggests replacing planned up-front design with evolutionary design, which advises implementing the simplest solution that satisfies the current iteration's requirements. However, the literature records several instances where development teams have argued for the naturalness of, and need for, planned design. This paper describes two experimental studies that compared both approaches regarding product quality and programmer productivity. Results from both studies show that (1) there is no significant difference of product quality, independently of the subjects' experience, but (2) novices are more productive when allowed to use planned design.
{"title":"Deconstructing Agile Processes: Would Planned Design Be Helpful in XP Projects?","authors":"René Noël, G. Valdés, Marcello Visconti, H. Astudillo","doi":"10.1109/SCCC.2008.14","DOIUrl":"https://doi.org/10.1109/SCCC.2008.14","url":null,"abstract":"Extreme programming (XP) suggests replacing planned up-front design with evolutionary design, which advises implementing the simplest solution that satisfies the current iteration's requirements. However, the literature records several instances where development teams have argued for the naturalness of, and need for, planned design. This paper describes two experimental studies that compared both approaches regarding product quality and programmer productivity. Results from both studies show that (1) there is no significant difference of product quality, independently of the subjects' experience, but (2) novices are more productive when allowed to use planned design.","PeriodicalId":415835,"journal":{"name":"2008 International Conference of the Chilean Computer Science Society","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127371715","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The Raise specification language (RSL) is a broad spectrum modeling language which supports a wide range of specification styles. In order to apply verification techniques based on model checking to descriptions of concurrent systems in RSL, we translate RSL specifications into the input language CSPM of the FDR model checker. FDR is a well-established model checker for the process algebra CSP. However, we need to show that the analysis performed in FDR carry over to the original RSL specifications. For this purpose, we define a syntactic and semantic translation between RSL and CSPM, and show that this translation is in fact a strong bisimulation which preserves various properties such as traces and deadlock. Finally, we have built a tool which automates the translation of RSL specifications into CSPM following this approach.
{"title":"A Translation from RSL to CSP","authors":"Abigail Parisaca Vargas, S. Tarifa, C. George","doi":"10.1109/SCCC.2008.20","DOIUrl":"https://doi.org/10.1109/SCCC.2008.20","url":null,"abstract":"The Raise specification language (RSL) is a broad spectrum modeling language which supports a wide range of specification styles. In order to apply verification techniques based on model checking to descriptions of concurrent systems in RSL, we translate RSL specifications into the input language CSPM of the FDR model checker. FDR is a well-established model checker for the process algebra CSP. However, we need to show that the analysis performed in FDR carry over to the original RSL specifications. For this purpose, we define a syntactic and semantic translation between RSL and CSPM, and show that this translation is in fact a strong bisimulation which preserves various properties such as traces and deadlock. Finally, we have built a tool which automates the translation of RSL specifications into CSPM following this approach.","PeriodicalId":415835,"journal":{"name":"2008 International Conference of the Chilean Computer Science Society","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125809806","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Component-based software development must deal with the fact that in practical settings, components information may be incomplete, imprecise and uncertain. Architects wanting to evaluate candidate architectures regarding requirements satisfaction need to use whatever information be available about components, however imperfect. This article introduces constraint programming as a formal technique to generate, evaluate and select composite COTS-based software systems (CCSS). This formalization systematically uses components imperfect information, to evaluate and rank CCSS, according to functional and non-functional requirements. The use of constraint programming allows architects to generate and evaluate alternative solutions within reasonable time and computational resources. The proposed approach is illustrated with a running example taken from the literature.
{"title":"Weak Constraint Programming to Identify Alternative Composite COTS-Based Software Systems from Imperfect Information","authors":"C. B. Castro, H. Astudillo","doi":"10.1109/SCCC.2008.15","DOIUrl":"https://doi.org/10.1109/SCCC.2008.15","url":null,"abstract":"Component-based software development must deal with the fact that in practical settings, components information may be incomplete, imprecise and uncertain. Architects wanting to evaluate candidate architectures regarding requirements satisfaction need to use whatever information be available about components, however imperfect. This article introduces constraint programming as a formal technique to generate, evaluate and select composite COTS-based software systems (CCSS). This formalization systematically uses components imperfect information, to evaluate and rank CCSS, according to functional and non-functional requirements. The use of constraint programming allows architects to generate and evaluate alternative solutions within reasonable time and computational resources. The proposed approach is illustrated with a running example taken from the literature.","PeriodicalId":415835,"journal":{"name":"2008 International Conference of the Chilean Computer Science Society","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126990617","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
G. Gracioli, Danillo Moura Santos, R. Matos, L. Wanner, A. A. Fröhlich
One of the tasks of an operating system is to handle time events. Traditionally, time management is based on periodic interrupts from one of the system's hardware timers (ticks). However, this approach has some limitations, as lack of precision, large overhead, and large power consumption. These limitations have motivated the use of non-periodic timers (e.g. one-shot timers), specially in specific-purpose operating systems with timing restrictions, such as embedded, real-time, and multimedia systems. This work presents a comparison between one-shot and periodic time implementations in the time management abstractions in EPOS (embedded parallel operating system). We compare both implementations in terms of memory footprint, number of context switches, number of interrupt handler executions and run time in different execution scenarios.
{"title":"One-Shot Time Management Analysis in EPOS","authors":"G. Gracioli, Danillo Moura Santos, R. Matos, L. Wanner, A. A. Fröhlich","doi":"10.1109/SCCC.2008.13","DOIUrl":"https://doi.org/10.1109/SCCC.2008.13","url":null,"abstract":"One of the tasks of an operating system is to handle time events. Traditionally, time management is based on periodic interrupts from one of the system's hardware timers (ticks). However, this approach has some limitations, as lack of precision, large overhead, and large power consumption. These limitations have motivated the use of non-periodic timers (e.g. one-shot timers), specially in specific-purpose operating systems with timing restrictions, such as embedded, real-time, and multimedia systems. This work presents a comparison between one-shot and periodic time implementations in the time management abstractions in EPOS (embedded parallel operating system). We compare both implementations in terms of memory footprint, number of context switches, number of interrupt handler executions and run time in different execution scenarios.","PeriodicalId":415835,"journal":{"name":"2008 International Conference of the Chilean Computer Science Society","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115229062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper we present a novel approach to establish correspondences between connected components in a sequence of binary images. This matching method is formulated using mathematical morphology concepts which are also used in an interpolation technique where correspondences between sets must be established. The work presents some examples of interpolated images sequences where our matching method shows a satisfactorily results.
{"title":"Sets Matching in Binary Images Using Mathematical Morphology","authors":"Javier Vidal, J. Crespo","doi":"10.1109/SCCC.2008.17","DOIUrl":"https://doi.org/10.1109/SCCC.2008.17","url":null,"abstract":"In this paper we present a novel approach to establish correspondences between connected components in a sequence of binary images. This matching method is formulated using mathematical morphology concepts which are also used in an interpolation technique where correspondences between sets must be established. The work presents some examples of interpolated images sequences where our matching method shows a satisfactorily results.","PeriodicalId":415835,"journal":{"name":"2008 International Conference of the Chilean Computer Science Society","volume":"156 2-3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121874652","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Bounded model checking (BMC) is an efficient verification technique designed originally for synchronous systems. Recently, however, several studies have been conducted that attempt to apply BMC to concurrent systems. In this paper, we propose a BMC encoding for systems modeled as synchronized products of transition systems. Our encoding generates compact formulas compared to basic methods, and thus decreases the execution time needed for the SAT-solving process. The correctness and effectiveness of the proposed method is shown through several experimentations.
{"title":"BMC Encoding for Concurrent Systems","authors":"Manitra Rakotoarisoa, E. Pastor","doi":"10.1109/SCCC.2008.22","DOIUrl":"https://doi.org/10.1109/SCCC.2008.22","url":null,"abstract":"Bounded model checking (BMC) is an efficient verification technique designed originally for synchronous systems. Recently, however, several studies have been conducted that attempt to apply BMC to concurrent systems. In this paper, we propose a BMC encoding for systems modeled as synchronized products of transition systems. Our encoding generates compact formulas compared to basic methods, and thus decreases the execution time needed for the SAT-solving process. The correctness and effectiveness of the proposed method is shown through several experimentations.","PeriodicalId":415835,"journal":{"name":"2008 International Conference of the Chilean Computer Science Society","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114800907","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The study of variability in software development has become increasingly important in recent years. The research areas in which this is involved range from software specialization to product lines. A common mechanism to represent the variability in a product line is by means of feature models. However, the relationship between these models and UML design models is not straightforward. The contribution of this work is the proposal of an extension of UML statecharts, which consists of introducing variability in their main components, so that the behavior of product lines can be specified. This is accomplished via the use of feature models, in order to describe the common and variant components, in such a way that, starting from different feature configurations, concrete state machines corresponding to different products of a line can be obtained.
{"title":"Behavior Specification of Product Lines via Feature Models and UML Statecharts with Variabilities","authors":"Ariel Gonzalez, C. Luna","doi":"10.1109/SCCC.2008.19","DOIUrl":"https://doi.org/10.1109/SCCC.2008.19","url":null,"abstract":"The study of variability in software development has become increasingly important in recent years. The research areas in which this is involved range from software specialization to product lines. A common mechanism to represent the variability in a product line is by means of feature models. However, the relationship between these models and UML design models is not straightforward. The contribution of this work is the proposal of an extension of UML statecharts, which consists of introducing variability in their main components, so that the behavior of product lines can be specified. This is accomplished via the use of feature models, in order to describe the common and variant components, in such a way that, starting from different feature configurations, concrete state machines corresponding to different products of a line can be obtained.","PeriodicalId":415835,"journal":{"name":"2008 International Conference of the Chilean Computer Science Society","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123618358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Laura C. De Giusti, Franco Chichizola, M. Naiouf, A. D. Giusti
An automatic task-to-processor mapping algorithm is analyzed in parallel systems that run over loosely coupled distributed architectures. This research is based on the TTIGHa model that allows predicting parallel application performance running over heterogeneous architectures. In particular, the heterogeneity of both processors and communications is taken into consideration. From the results obtained with the TTIGHa model, the MATEHa algorithm for task-to-processors assignment is presented and its implementation is analyzed. Experimental results working on subsets of two-cluster heterogeneous machines are presented, analyzing the resulting mapping scheme with MATEHa and two previous mapping methods: MATE and HEFT. Finally, the algorithm robustness is considered based on the variation of model parameters: inter-process communication times and processing times.
{"title":"Mapping Tasks to Processors in Heterogeneous Multiprocessor Architectures: The MATEHa Algorithm","authors":"Laura C. De Giusti, Franco Chichizola, M. Naiouf, A. D. Giusti","doi":"10.1109/SCCC.2008.11","DOIUrl":"https://doi.org/10.1109/SCCC.2008.11","url":null,"abstract":"An automatic task-to-processor mapping algorithm is analyzed in parallel systems that run over loosely coupled distributed architectures. This research is based on the TTIGHa model that allows predicting parallel application performance running over heterogeneous architectures. In particular, the heterogeneity of both processors and communications is taken into consideration. From the results obtained with the TTIGHa model, the MATEHa algorithm for task-to-processors assignment is presented and its implementation is analyzed. Experimental results working on subsets of two-cluster heterogeneous machines are presented, analyzing the resulting mapping scheme with MATEHa and two previous mapping methods: MATE and HEFT. Finally, the algorithm robustness is considered based on the variation of model parameters: inter-process communication times and processing times.","PeriodicalId":415835,"journal":{"name":"2008 International Conference of the Chilean Computer Science Society","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130929037","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Since 90's, several new approaches providing solutions to integrated or federated systems have been defined. In particular, with respect to geographic information systems, proposals of integration did not take long time to appear. However, applicability of many of those approaches is still unlikely. In this context, we introduce an ontology-based approach - the GeoMergeP system - aiming at improving the capabilities of the integration process. In this paper we propose a methodology composed of two main process, semantic enrichment (by adding information about the ISO 19100 standard) and merging. The last one performs some tasks automatically and guides the user in performing other tasks for which his/her intervention is required. Finally, a plugin of the ontology editor, Protege, is presented showing how the method is implemented through a case study.
{"title":"GeoMergeP: Supporting an Ontological Approach to Geographic Information Integration","authors":"Agustina Buccella, Laura Perez, A. Cechich","doi":"10.1109/SCCC.2008.9","DOIUrl":"https://doi.org/10.1109/SCCC.2008.9","url":null,"abstract":"Since 90's, several new approaches providing solutions to integrated or federated systems have been defined. In particular, with respect to geographic information systems, proposals of integration did not take long time to appear. However, applicability of many of those approaches is still unlikely. In this context, we introduce an ontology-based approach - the GeoMergeP system - aiming at improving the capabilities of the integration process. In this paper we propose a methodology composed of two main process, semantic enrichment (by adding information about the ISO 19100 standard) and merging. The last one performs some tasks automatically and guides the user in performing other tasks for which his/her intervention is required. Finally, a plugin of the ontology editor, Protege, is presented showing how the method is implemented through a case study.","PeriodicalId":415835,"journal":{"name":"2008 International Conference of the Chilean Computer Science Society","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128470379","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Cádiz, Boris Mejías, Jorge Vallejos, K. Mens, P. V. Roy, W. Meuter
Many ambient intelligence (AmI) scenarios fit perfectly for auto-generated distributed networks, but they assume the existence of good enough network topology organizing the connected devices. AmI scenarios need to handle an unanticipated number of participants and inappropriate distributed network topologies can affect the network's efficiency by making it unstable and hard to manage. This paper introduces PALTA, a self-adapting hybrid topology capable of dynamically adjusting its configuration by using a combination of existing topologies. PALTA allows the incremental construction of self-maintained distributed networks which take advantage of the current network state.
{"title":"PALTA: Peer-to-peer AdaptabLe Topology for Ambient intelligence","authors":"A. Cádiz, Boris Mejías, Jorge Vallejos, K. Mens, P. V. Roy, W. Meuter","doi":"10.1109/SCCC.2008.16","DOIUrl":"https://doi.org/10.1109/SCCC.2008.16","url":null,"abstract":"Many ambient intelligence (AmI) scenarios fit perfectly for auto-generated distributed networks, but they assume the existence of good enough network topology organizing the connected devices. AmI scenarios need to handle an unanticipated number of participants and inappropriate distributed network topologies can affect the network's efficiency by making it unstable and hard to manage. This paper introduces PALTA, a self-adapting hybrid topology capable of dynamically adjusting its configuration by using a combination of existing topologies. PALTA allows the incremental construction of self-maintained distributed networks which take advantage of the current network state.","PeriodicalId":415835,"journal":{"name":"2008 International Conference of the Chilean Computer Science Society","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127586607","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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