Pub Date : 1998-08-24DOI: 10.1109/MTDT.1998.705958
N. Park, E. Lombardi
This paper presents new algorithms for yield enhancement of redundant memories. These algorithms are based on the technique of spare cutting for a redundant memory chip in which repair is implemented by row/column deletion. Different approaches are proposed: some of these approaches are based on a fully exhaustive process, while others try to heuristically reduce the computational overhead involved in determining the repair-solution of a redundant memory. Conditions for unidirectional and bidirectional cutting (i.e. cutting either along the rows and/or columns of the memory) are analyzed.
{"title":"Repair of memory arrays by cutting","authors":"N. Park, E. Lombardi","doi":"10.1109/MTDT.1998.705958","DOIUrl":"https://doi.org/10.1109/MTDT.1998.705958","url":null,"abstract":"This paper presents new algorithms for yield enhancement of redundant memories. These algorithms are based on the technique of spare cutting for a redundant memory chip in which repair is implemented by row/column deletion. Different approaches are proposed: some of these approaches are based on a fully exhaustive process, while others try to heuristically reduce the computational overhead involved in determining the repair-solution of a redundant memory. Conditions for unidirectional and bidirectional cutting (i.e. cutting either along the rows and/or columns of the memory) are analyzed.","PeriodicalId":420476,"journal":{"name":"Proceedings. International Workshop on Memory Technology, Design and Testing (Cat. No.98TB100236)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-08-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127181562","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-08-24DOI: 10.1109/MTDT.1998.705956
J. Zhao, F. Meyer, E. Lombardi
This paper presents three new approaches for testing interconnects of random access memories (RAM). These algorithms are referred to as the Adaptive Diagnosis Algorithm (ADA), the Consecutive Diagnosis Algorithm (CDA) and the Adaptive Diagnosis Algorithm with Repair (ADAR). For diagnosis, ADA requires max{n+1,p} WRITE and max{n,p} READ, while CDA requires max{n+1,p} WRITE and n+p READ, where n(m) is the number of address (data) lines and p is the least integer such that C/sub p/2//sup p//spl ges/m. A different scenario referred to as maximal diagnosis, is considered next. Maximal diagnosis refers as the full diagnosis of all detectable and diagnosable faults in the interconnect with no repair. ADAR utilizes various test iterations to achieve maximal diagnosis; between each pair of iterations, repair of the diagnosed lines takes place. In ADAR, two repair and three test iterations are required. ADAR requires a total of 2n+m+3 WRITE and 3n+m+1 READ.
{"title":"Adaptive approaches for fault detection and diagnosis of interconnects of random access memories","authors":"J. Zhao, F. Meyer, E. Lombardi","doi":"10.1109/MTDT.1998.705956","DOIUrl":"https://doi.org/10.1109/MTDT.1998.705956","url":null,"abstract":"This paper presents three new approaches for testing interconnects of random access memories (RAM). These algorithms are referred to as the Adaptive Diagnosis Algorithm (ADA), the Consecutive Diagnosis Algorithm (CDA) and the Adaptive Diagnosis Algorithm with Repair (ADAR). For diagnosis, ADA requires max{n+1,p} WRITE and max{n,p} READ, while CDA requires max{n+1,p} WRITE and n+p READ, where n(m) is the number of address (data) lines and p is the least integer such that C/sub p/2//sup p//spl ges/m. A different scenario referred to as maximal diagnosis, is considered next. Maximal diagnosis refers as the full diagnosis of all detectable and diagnosable faults in the interconnect with no repair. ADAR utilizes various test iterations to achieve maximal diagnosis; between each pair of iterations, repair of the diagnosed lines takes place. In ADAR, two repair and three test iterations are required. ADAR requires a total of 2n+m+3 WRITE and 3n+m+1 READ.","PeriodicalId":420476,"journal":{"name":"Proceedings. International Workshop on Memory Technology, Design and Testing (Cat. No.98TB100236)","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-08-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122300286","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-08-24DOI: 10.1109/MTDT.1998.705957
Gianluca Battaglini, B. Ciciani
A new stochastic method is introduced for calculating the manufacturing field of fault-tolerant VLSI/WSI systems. This method is an improvement on a previous method based on a Markov chain. This new method gives a higher lower bound value of the field with respect to other methods based on the same assumptions. This improvement is obtained by the consideration of reconfiguration strategies based on the knowledge of the fault patterns and the redundancy levels. The proposed method is easy to use in parametric studies of the field of a chip versus redundancy level and very versatile for inclusion in CAM/CAD programming environments.
{"title":"An improved analytical yield evaluation method for redundant RAM's","authors":"Gianluca Battaglini, B. Ciciani","doi":"10.1109/MTDT.1998.705957","DOIUrl":"https://doi.org/10.1109/MTDT.1998.705957","url":null,"abstract":"A new stochastic method is introduced for calculating the manufacturing field of fault-tolerant VLSI/WSI systems. This method is an improvement on a previous method based on a Markov chain. This new method gives a higher lower bound value of the field with respect to other methods based on the same assumptions. This improvement is obtained by the consideration of reconfiguration strategies based on the knowledge of the fault patterns and the redundancy levels. The proposed method is easy to use in parametric studies of the field of a chip versus redundancy level and very versatile for inclusion in CAM/CAD programming environments.","PeriodicalId":420476,"journal":{"name":"Proceedings. International Workshop on Memory Technology, Design and Testing (Cat. No.98TB100236)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-08-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129668745","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-08-24DOI: 10.1109/MTDT.1998.705942
P. Diodato, L. Noda, Y. Wong, J. M. Drynan, C. Liu, K. Lee, R. Dail, W. S. Lindenberger, A. C. Dumbri, M. DePaolis, J. Clemens, W. Troutman, M. Nakamae
The desire to enhance memory bandwidth in high performance computing components is overwhelming, and early attempts to combine large memories with high performance logic in a single silicon integrated circuit are numerous. However, existing implementations of a combined (merged) memory-logic technology are unsatisfactory (because of high cost) and complicated (because the technologies used for high-performance logic and high-density memory are disparate). The research reported here will explain the joint technology development of two corporations working on a merged memory-logic technology in terms of: (1) memory cell design comparisons, (2) transistor and capacitor specifications, (3) process technology tradeoffs, and (4) circuit simulations.
{"title":"Merged DRAM-logic in the year 2001","authors":"P. Diodato, L. Noda, Y. Wong, J. M. Drynan, C. Liu, K. Lee, R. Dail, W. S. Lindenberger, A. C. Dumbri, M. DePaolis, J. Clemens, W. Troutman, M. Nakamae","doi":"10.1109/MTDT.1998.705942","DOIUrl":"https://doi.org/10.1109/MTDT.1998.705942","url":null,"abstract":"The desire to enhance memory bandwidth in high performance computing components is overwhelming, and early attempts to combine large memories with high performance logic in a single silicon integrated circuit are numerous. However, existing implementations of a combined (merged) memory-logic technology are unsatisfactory (because of high cost) and complicated (because the technologies used for high-performance logic and high-density memory are disparate). The research reported here will explain the joint technology development of two corporations working on a merged memory-logic technology in terms of: (1) memory cell design comparisons, (2) transistor and capacitor specifications, (3) process technology tradeoffs, and (4) circuit simulations.","PeriodicalId":420476,"journal":{"name":"Proceedings. International Workshop on Memory Technology, Design and Testing (Cat. No.98TB100236)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-08-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123793646","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-08-24DOI: 10.1109/MTDT.1998.705947
Jian Liu, R. Makki
We present an overview of power supply current testing of SRAMs and propose a test method to improve the CMOS SRAM test efficiency by using on-chip dynamic power supply current sensors. It is shown that the test method provides full observability of cell switching and allows for a significant reduction in test time. The test length is O(n) including coupling faults.
{"title":"SRAM test using on-chip dynamic power supply current sensor","authors":"Jian Liu, R. Makki","doi":"10.1109/MTDT.1998.705947","DOIUrl":"https://doi.org/10.1109/MTDT.1998.705947","url":null,"abstract":"We present an overview of power supply current testing of SRAMs and propose a test method to improve the CMOS SRAM test efficiency by using on-chip dynamic power supply current sensors. It is shown that the test method provides full observability of cell switching and allows for a significant reduction in test time. The test length is O(n) including coupling faults.","PeriodicalId":420476,"journal":{"name":"Proceedings. International Workshop on Memory Technology, Design and Testing (Cat. No.98TB100236)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-08-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127373290","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-08-24DOI: 10.1109/MTDT.1998.705946
D. Aadsen, L. Fenstermaker, F. Higgins, Ilyoung Kim, J. Lewandowski, J. J. Nagy
The increasing use of two parted register files (one read port and one write port) has introduced complications in complete, accurate testing. This is especially true when the memories appear as embedded cores in Systems On Chips. In this paper, we describe a new fault effect that has been observed, a basic algorithm for detecting this fault, and enhance a well known classic algorithm for memory testing to detect these faults.
{"title":"Test algorithm for memory cell disturb failures","authors":"D. Aadsen, L. Fenstermaker, F. Higgins, Ilyoung Kim, J. Lewandowski, J. J. Nagy","doi":"10.1109/MTDT.1998.705946","DOIUrl":"https://doi.org/10.1109/MTDT.1998.705946","url":null,"abstract":"The increasing use of two parted register files (one read port and one write port) has introduced complications in complete, accurate testing. This is especially true when the memories appear as embedded cores in Systems On Chips. In this paper, we describe a new fault effect that has been observed, a basic algorithm for detecting this fault, and enhance a well known classic algorithm for memory testing to detect these faults.","PeriodicalId":420476,"journal":{"name":"Proceedings. International Workshop on Memory Technology, Design and Testing (Cat. No.98TB100236)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-08-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133752413","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-08-24DOI: 10.1109/MTDT.1998.705949
S. Murray
Summary form only given, as follows. In today's highly competitive, cost-driven market, commercial memory manufacturers are forced to increase total bit counts and densities while reducing test times. As a result, many performance parameters are now being guaranteed by design or sample testing rather than by full functional verification of each device. This situation is complicated by the drive for lower power consumption (i.e. lower supply voltage) which compromises operating margins. In addition, the consumer electronics market's tendency to dispose of components, rather than repair them, and shorter product life cycles have reduced the manufacturer's feedback on failure modes in typical use. This minimized approach to performance verification poses a problem for manufacturers involved in high reliability applications, such as medical implantable, military, automotive, and aerospace, who often perform additional testing on their own. To insure high reliability memory in their implantable medical electronics, Medtronic has developed a methodology for the performance verification of commercial SRAMs which accommodates the lack of design and fabrication information typically available at the manufacturer. The following points are covered: problems of black box design verification, practical methods for performance verification, example results and production test optimization.
{"title":"A user's approach to characterization and test of commercially available SRAMs","authors":"S. Murray","doi":"10.1109/MTDT.1998.705949","DOIUrl":"https://doi.org/10.1109/MTDT.1998.705949","url":null,"abstract":"Summary form only given, as follows. In today's highly competitive, cost-driven market, commercial memory manufacturers are forced to increase total bit counts and densities while reducing test times. As a result, many performance parameters are now being guaranteed by design or sample testing rather than by full functional verification of each device. This situation is complicated by the drive for lower power consumption (i.e. lower supply voltage) which compromises operating margins. In addition, the consumer electronics market's tendency to dispose of components, rather than repair them, and shorter product life cycles have reduced the manufacturer's feedback on failure modes in typical use. This minimized approach to performance verification poses a problem for manufacturers involved in high reliability applications, such as medical implantable, military, automotive, and aerospace, who often perform additional testing on their own. To insure high reliability memory in their implantable medical electronics, Medtronic has developed a methodology for the performance verification of commercial SRAMs which accommodates the lack of design and fabrication information typically available at the manufacturer. The following points are covered: problems of black box design verification, practical methods for performance verification, example results and production test optimization.","PeriodicalId":420476,"journal":{"name":"Proceedings. International Workshop on Memory Technology, Design and Testing (Cat. No.98TB100236)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-08-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117019117","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-08-24DOI: 10.1109/MTDT.1998.705950
Kun-Jin Lin, Cheng-Wen Wu
Functional tests for content-addressable memories (CAMs) are presented in this paper. The fault models considered are based on physical defects. In order to make our approach suited to various application specific CAMs, we propose tests which require only three fundamental types of operation, and the test results can be observed entirely from the single-bit match/hit output. A complete, compact test is also proposed, which has reasonable test length for modern high-density and large-capacity CAMs.
{"title":"Functional testing of content-addressable memories","authors":"Kun-Jin Lin, Cheng-Wen Wu","doi":"10.1109/MTDT.1998.705950","DOIUrl":"https://doi.org/10.1109/MTDT.1998.705950","url":null,"abstract":"Functional tests for content-addressable memories (CAMs) are presented in this paper. The fault models considered are based on physical defects. In order to make our approach suited to various application specific CAMs, we propose tests which require only three fundamental types of operation, and the test results can be observed entirely from the single-bit match/hit output. A complete, compact test is also proposed, which has reasonable test length for modern high-density and large-capacity CAMs.","PeriodicalId":420476,"journal":{"name":"Proceedings. International Workshop on Memory Technology, Design and Testing (Cat. No.98TB100236)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-08-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127828405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-08-24DOI: 10.1109/MTDT.1998.705938
X. Sun
In this paper an integrated open CAD methodology for low power designs used by the DSP56800 family with embedded memory is described. Special consideration for embedded memory design is taken in the CAD system. The productivity improvement and IP sharing requirements for IC design drove the design of the integrated open CAD system. In order to reach design targets, select the best low power design implementation and reduce cycle time to market, the CAD system described in this paper is needed.
{"title":"An integrated open CAD system for DSP design with embedded memory","authors":"X. Sun","doi":"10.1109/MTDT.1998.705938","DOIUrl":"https://doi.org/10.1109/MTDT.1998.705938","url":null,"abstract":"In this paper an integrated open CAD methodology for low power designs used by the DSP56800 family with embedded memory is described. Special consideration for embedded memory design is taken in the CAD system. The productivity improvement and IP sharing requirements for IC design drove the design of the integrated open CAD system. In order to reach design targets, select the best low power design implementation and reduce cycle time to market, the CAD system described in this paper is needed.","PeriodicalId":420476,"journal":{"name":"Proceedings. International Workshop on Memory Technology, Design and Testing (Cat. No.98TB100236)","volume":"141 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-08-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123248608","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-08-24DOI: 10.1109/MTDT.1998.705955
T. Monnier, F. M. Roche, G. Cathébras
The purpose of this work is to design a flip-flop hardened to Single Event Upset (SEU) for space radiation environment. The design hardening technique is based on the use of two D-latch hardened both to static and dynamic SEU by the concepts of high impedance state and nMOS feedback.
{"title":"Flip-flop hardening for space applications","authors":"T. Monnier, F. M. Roche, G. Cathébras","doi":"10.1109/MTDT.1998.705955","DOIUrl":"https://doi.org/10.1109/MTDT.1998.705955","url":null,"abstract":"The purpose of this work is to design a flip-flop hardened to Single Event Upset (SEU) for space radiation environment. The design hardening technique is based on the use of two D-latch hardened both to static and dynamic SEU by the concepts of high impedance state and nMOS feedback.","PeriodicalId":420476,"journal":{"name":"Proceedings. International Workshop on Memory Technology, Design and Testing (Cat. No.98TB100236)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-08-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121472348","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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