Pub Date : 2013-04-27DOI: 10.1109/SIECPC.2013.6550782
N. M. Ali, S. Harun, R. Parvizi, H. Ahmad
This paper presents an experimental finding of a tunable multiwavelength Brillouin-erbium fiber laser with a double-Brillouin-frequency spacing in a figure-of-eight cofiguration. This double-frequency shifter is formed by incorporating a four-port circulator to isolate and circulate the odd-Stokes signals through a gain medium of a 10 km long nonzero dispersion shifted fiber (NZ-DSF). The ebium gain block amplifies the output even-order Stokes signals formed in a ring cavity. Tip to 15 lasing lines with a wavelength spacing of 0.173 nm have been realized at a 980 nm pump power of 50 mW with a Brillouin pump of 3 dBm. The multiwavelength laser source demonstrates a 10 nm tuning range from 1552 to 1562 nm with the optical signal-to-noise ratio of the desired output channels at around 34.5 dB.
{"title":"Brillouin erbium fiber laser generation in a figure-of-eight configuration with double brillouin frequency spacing","authors":"N. M. Ali, S. Harun, R. Parvizi, H. Ahmad","doi":"10.1109/SIECPC.2013.6550782","DOIUrl":"https://doi.org/10.1109/SIECPC.2013.6550782","url":null,"abstract":"This paper presents an experimental finding of a tunable multiwavelength Brillouin-erbium fiber laser with a double-Brillouin-frequency spacing in a figure-of-eight cofiguration. This double-frequency shifter is formed by incorporating a four-port circulator to isolate and circulate the odd-Stokes signals through a gain medium of a 10 km long nonzero dispersion shifted fiber (NZ-DSF). The ebium gain block amplifies the output even-order Stokes signals formed in a ring cavity. Tip to 15 lasing lines with a wavelength spacing of 0.173 nm have been realized at a 980 nm pump power of 50 mW with a Brillouin pump of 3 dBm. The multiwavelength laser source demonstrates a 10 nm tuning range from 1552 to 1562 nm with the optical signal-to-noise ratio of the desired output channels at around 34.5 dB.","PeriodicalId":427798,"journal":{"name":"2013 Saudi International Electronics, Communications and Photonics Conference","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121025878","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-27DOI: 10.1109/SIECPC.2013.6550982
J. R. van der Merwe, L. Linde, W. D. du Plessis, J. V. van Wyk
The detection of cellular communications signals was investigated, and a prototype detector was implemented. Global System for Mobile Communications (GSM) signals were detected in recorded data and the correct frequency channel was determined. Inter-channel interference (ICI) was observed and methods to reduce it are discussed. Detection was achieved at a lower signal-to-noise ratio (SNR) than is required by a base transceiver station (BTS), thereby demonstrating the potential to detect mobiles at long range.
{"title":"Cellular communication signal identification, detection and analysis","authors":"J. R. van der Merwe, L. Linde, W. D. du Plessis, J. V. van Wyk","doi":"10.1109/SIECPC.2013.6550982","DOIUrl":"https://doi.org/10.1109/SIECPC.2013.6550982","url":null,"abstract":"The detection of cellular communications signals was investigated, and a prototype detector was implemented. Global System for Mobile Communications (GSM) signals were detected in recorded data and the correct frequency channel was determined. Inter-channel interference (ICI) was observed and methods to reduce it are discussed. Detection was achieved at a lower signal-to-noise ratio (SNR) than is required by a base transceiver station (BTS), thereby demonstrating the potential to detect mobiles at long range.","PeriodicalId":427798,"journal":{"name":"2013 Saudi International Electronics, Communications and Photonics Conference","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115023541","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-27DOI: 10.1109/SIECPC.2013.6550774
Alaa R. Al-Taee, F. Yuan, A. Ye
A new improved RC modeling for on-chip interconnects derived from pi-configuration of AWE-Based RLC model is presented. A platform utilized to generate all-possible T- and pi configurations of RC, RLC and RLCG models using GAM, TPN, and AWE methods is proposed. 18 different RC, RLC, and RLCG models are generated based on this platform. The pi-configuration of AWE-RLC model provides the best performance. This model is mapped into an improved RC model to preserve the accuracy of the RLC model while keeping the simplicity of the RC model. As compared with conventional RC model, the simulation results of interconnect's delay with buffer insertion show that the proposed RC model improves the delay by 20.5%, reduces the number of required buffers by 24%, and the buffer sizes by 32%.
{"title":"A new simple RC modeling for on-chip interconnects with its applications to buffer insertion","authors":"Alaa R. Al-Taee, F. Yuan, A. Ye","doi":"10.1109/SIECPC.2013.6550774","DOIUrl":"https://doi.org/10.1109/SIECPC.2013.6550774","url":null,"abstract":"A new improved RC modeling for on-chip interconnects derived from pi-configuration of AWE-Based RLC model is presented. A platform utilized to generate all-possible T- and pi configurations of RC, RLC and RLCG models using GAM, TPN, and AWE methods is proposed. 18 different RC, RLC, and RLCG models are generated based on this platform. The pi-configuration of AWE-RLC model provides the best performance. This model is mapped into an improved RC model to preserve the accuracy of the RLC model while keeping the simplicity of the RC model. As compared with conventional RC model, the simulation results of interconnect's delay with buffer insertion show that the proposed RC model improves the delay by 20.5%, reduces the number of required buffers by 24%, and the buffer sizes by 32%.","PeriodicalId":427798,"journal":{"name":"2013 Saudi International Electronics, Communications and Photonics Conference","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114572704","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-27DOI: 10.1109/SIECPC.2013.6550792
M. Bahaidarah, Hesham Al-Obaisi, Tariq Al-Sharif, Mosab Al-Zahrani, Mohammad Awedh, Yasser M. Seddiq
Soft-core processors on Field Programmable Gate Array (FPGA) chips are becoming an increasingly popular solution to support application-specific customization. However, any change in the assembly code of the implemented processor requires re-implement and download the soft-core on FPGA. This paper presents a FPGA realization of a run-time loading technique for a 32-bit MIPS (Microprocessor without Interlocked Pipeline Stages) processor. The update of MIPS code is done without having to resynthesize, place and route, and reload the soft-core. The design consists of three main blocks: a microprocessor soft-core, a software tool and a universal asynchronous receiver/transmitter (UART). The software tools sets the content of the instruction memory space of the processor without having to go through the FPGA implementation process. The FPGA implements MIPS soft-core processor as well as the UART receiver. The software tool communicates with the softcore via UART. To demonstrate the proposed technique, we wrote an UP/DOWN counter assembly code. The design architecture is coded using Verilog based on top-down hierarchical design methodology and realized in Spartan-3E FPGA using Xilinx ISE 14.2. Based on the FPGA implementation results, the maximum operating frequency of the CPU is found to be 43.17 MHz.
现场可编程门阵列(FPGA)芯片上的软核处理器正成为支持特定应用定制的日益流行的解决方案。但是，所实现处理器的汇编代码的任何更改都需要在FPGA上重新实现和下载软核。本文介绍了一种32位MIPS(无互锁流水线级的微处理器)处理器运行时加载技术的FPGA实现。MIPS代码的更新无需重新合成、放置和路由以及重新加载软核即可完成。该设计由三个主要模块组成:微处理器软核、软件工具和通用异步收发器(UART)。软件工具无需经过FPGA实现过程即可设置处理器的指令存储器空间的内容。FPGA实现了MIPS软核处理器和UART接收器。软件工具通过UART与软核通信。为了演示所提出的技术，我们编写了一个UP/DOWN计数器汇编代码。设计架构使用基于自顶向下分层设计方法的Verilog进行编码，并使用Xilinx ISE 14.2在Spartan-3E FPGA上实现。根据FPGA的实现结果，CPU的最大工作频率为43.17 MHz。
{"title":"A novel technique for run-time loading for MIPS soft-core processor","authors":"M. Bahaidarah, Hesham Al-Obaisi, Tariq Al-Sharif, Mosab Al-Zahrani, Mohammad Awedh, Yasser M. Seddiq","doi":"10.1109/SIECPC.2013.6550792","DOIUrl":"https://doi.org/10.1109/SIECPC.2013.6550792","url":null,"abstract":"Soft-core processors on Field Programmable Gate Array (FPGA) chips are becoming an increasingly popular solution to support application-specific customization. However, any change in the assembly code of the implemented processor requires re-implement and download the soft-core on FPGA. This paper presents a FPGA realization of a run-time loading technique for a 32-bit MIPS (Microprocessor without Interlocked Pipeline Stages) processor. The update of MIPS code is done without having to resynthesize, place and route, and reload the soft-core. The design consists of three main blocks: a microprocessor soft-core, a software tool and a universal asynchronous receiver/transmitter (UART). The software tools sets the content of the instruction memory space of the processor without having to go through the FPGA implementation process. The FPGA implements MIPS soft-core processor as well as the UART receiver. The software tool communicates with the softcore via UART. To demonstrate the proposed technique, we wrote an UP/DOWN counter assembly code. The design architecture is coded using Verilog based on top-down hierarchical design methodology and realized in Spartan-3E FPGA using Xilinx ISE 14.2. Based on the FPGA implementation results, the maximum operating frequency of the CPU is found to be 43.17 MHz.","PeriodicalId":427798,"journal":{"name":"2013 Saudi International Electronics, Communications and Photonics Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129443905","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-27DOI: 10.1109/SIECPC.2013.6550769
A. Najar, A. Al-Jabr, A. Ben Slimane, M. Alsunaidi, T. Ng, B. Ooi, R. Sougrat, D. Anjum
Porous silicon nanowires (PSiNWs) have been prepared by metal-assisted chemical etching method on the n-Si substrate. The presence of nano-pores with pore size ranging between 10-50nm in SiNWs was confirmed by electron tomography (ET) in the transmission electron microscope (TEM). The PSiNWs give strong photoluminescence peak at red wavelength. Ultra-low reflectance of <;5% span over wavelength 250 nm to 1050 nm has been measured. The finite-difference time-domain (FDTD) method has been employed to model the optical reflectance for both Si wafer and PSiNWs. Our calculation results are in agreement with the measured reflectance from nanowires length of 6 μm and 60% porosity. The low reflectance is attributed to the effective graded index of PSiNWs and enhancement of multiple optical scattering from the pores and nanowires. PSiNW structures with low surface reflectance can potentially serve as an antireflection layer for Sibased photovoltaic devices.
{"title":"Effective antireflection properties of porous silicon nanowires for photovoltaic applications","authors":"A. Najar, A. Al-Jabr, A. Ben Slimane, M. Alsunaidi, T. Ng, B. Ooi, R. Sougrat, D. Anjum","doi":"10.1109/SIECPC.2013.6550769","DOIUrl":"https://doi.org/10.1109/SIECPC.2013.6550769","url":null,"abstract":"Porous silicon nanowires (PSiNWs) have been prepared by metal-assisted chemical etching method on the n-Si substrate. The presence of nano-pores with pore size ranging between 10-50nm in SiNWs was confirmed by electron tomography (ET) in the transmission electron microscope (TEM). The PSiNWs give strong photoluminescence peak at red wavelength. Ultra-low reflectance of <;5% span over wavelength 250 nm to 1050 nm has been measured. The finite-difference time-domain (FDTD) method has been employed to model the optical reflectance for both Si wafer and PSiNWs. Our calculation results are in agreement with the measured reflectance from nanowires length of 6 μm and 60% porosity. The low reflectance is attributed to the effective graded index of PSiNWs and enhancement of multiple optical scattering from the pores and nanowires. PSiNW structures with low surface reflectance can potentially serve as an antireflection layer for Sibased photovoltaic devices.","PeriodicalId":427798,"journal":{"name":"2013 Saudi International Electronics, Communications and Photonics Conference","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130408366","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-27DOI: 10.1109/SIECPC.2013.6550798
W. Tawfik, W. Farooq, Z. Alahmed, M. Sarfraz, K. Ahmad, F. Yakuphanoglu
Nanostructured thin films of cadmium oxide (CdO) have been synthesized using sol-gel technique on slide glass substrates. Thickness of the film is about 250 nm with average grain sizes of CdO in the range of 93-250 nm. Laser induced breakdown spectroscopy (LIBS) is used to investigate the synthesized CdO thin film. We have investigated LIBS spectrum of CdO thin film in air atmosphere using Spectrolaser-7000 system with 100 mJ fundamental laser beam from Nd:YaG laser and varied delay times from 200 ns to 2 microseconds. Many atomic and ionic lines of Cd were resolved and the variation with the delay time was studied. The plasma parameters have also been studied for Cd 508.58 nm. It is found that plasma cooled very fast after 500 ns as compared to the bulk material. The later showed that the recombination processes are growing very fast with time for nanostructured CdO thin film.
{"title":"Characterization and analysis of nanostructured CdO thin film using LIBS technique","authors":"W. Tawfik, W. Farooq, Z. Alahmed, M. Sarfraz, K. Ahmad, F. Yakuphanoglu","doi":"10.1109/SIECPC.2013.6550798","DOIUrl":"https://doi.org/10.1109/SIECPC.2013.6550798","url":null,"abstract":"Nanostructured thin films of cadmium oxide (CdO) have been synthesized using sol-gel technique on slide glass substrates. Thickness of the film is about 250 nm with average grain sizes of CdO in the range of 93-250 nm. Laser induced breakdown spectroscopy (LIBS) is used to investigate the synthesized CdO thin film. We have investigated LIBS spectrum of CdO thin film in air atmosphere using Spectrolaser-7000 system with 100 mJ fundamental laser beam from Nd:YaG laser and varied delay times from 200 ns to 2 microseconds. Many atomic and ionic lines of Cd were resolved and the variation with the delay time was studied. The plasma parameters have also been studied for Cd 508.58 nm. It is found that plasma cooled very fast after 500 ns as compared to the bulk material. The later showed that the recombination processes are growing very fast with time for nanostructured CdO thin film.","PeriodicalId":427798,"journal":{"name":"2013 Saudi International Electronics, Communications and Photonics Conference","volume":"155 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126509761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-27DOI: 10.1109/SIECPC.2013.6550764
Amr Ali, A. Hussein, A. El-Rouby, M. Mahmoud, A. Wassal
As the usage of very large scale integration (VLSI) in computers continues to increase, debugging of timing problems on actual hardware becomes more and more difficult. The post-layout gate-level simulation constitutes a critical design step for timing closure. The major drawback of traditional post-layout gate-level simulation is its long analysis time, which increases as design complexity increases. An alternative method is static timing analysis (STA), which can reduce analysis time. Going deeper through the nanometer technology, new STA techniques have to be present to provide more accurate results for cell delay models characterization. New STA techniques now go for current source based models (CSM) which are based on modeling MOSFETs as trans-conductance. In this paper, a SW engine is presented and used to perform a comparison on accuracy and speed between the default STA technique based on library lookup tables (LUT) and a proposed CSM-based technique for combinational logic cells. Moreover, an adaptive technique, which is based on utilizing both the LUT and CSM methods, is presented. The adaptive technique uses the method with the more accurate delay results when solving for circuits combined of NAND2X0, NOR2X0 and INVX0 standard cells. Also, provides the calculation for some metrics like (arrival time and slack delay values at each node in the combinational circuit).
{"title":"Accurate timing analysis of combinational logic cells engine using adaptive technique based on current source model","authors":"Amr Ali, A. Hussein, A. El-Rouby, M. Mahmoud, A. Wassal","doi":"10.1109/SIECPC.2013.6550764","DOIUrl":"https://doi.org/10.1109/SIECPC.2013.6550764","url":null,"abstract":"As the usage of very large scale integration (VLSI) in computers continues to increase, debugging of timing problems on actual hardware becomes more and more difficult. The post-layout gate-level simulation constitutes a critical design step for timing closure. The major drawback of traditional post-layout gate-level simulation is its long analysis time, which increases as design complexity increases. An alternative method is static timing analysis (STA), which can reduce analysis time. Going deeper through the nanometer technology, new STA techniques have to be present to provide more accurate results for cell delay models characterization. New STA techniques now go for current source based models (CSM) which are based on modeling MOSFETs as trans-conductance. In this paper, a SW engine is presented and used to perform a comparison on accuracy and speed between the default STA technique based on library lookup tables (LUT) and a proposed CSM-based technique for combinational logic cells. Moreover, an adaptive technique, which is based on utilizing both the LUT and CSM methods, is presented. The adaptive technique uses the method with the more accurate delay results when solving for circuits combined of NAND2X0, NOR2X0 and INVX0 standard cells. Also, provides the calculation for some metrics like (arrival time and slack delay values at each node in the combinational circuit).","PeriodicalId":427798,"journal":{"name":"2013 Saudi International Electronics, Communications and Photonics Conference","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122208258","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-27DOI: 10.1109/SIECPC.2013.6550773
Chao Shen, T. Ng, B. Ooi, D. Cha
Micro-structured group-III-nitrides are considered as promising strain relief structures for high efficiency solid state lighting. In this work, the strain field in InGaN/GaN multiquantum wells (MQWs) micro-pillars is investigated using micro-Raman spectroscopy and the design of micro-pillars were studied experimentally. We distinguished the strained and strain-relieved signatures of the GaN layer from the E2 phonon peak split from the Raman scattering signatures at 572 cm-1 and 568 cm-1, respectively. The extent of strain relief is examined considering the height and size of micro-pillars fabricated using focused ion beam (FIB) micro-machining technique. A significant strain relief can be achieved when one micro-machined through the entire epi-layers, 3 μm in our study. The dependence of strain relief on micro-pillar diameter (D) suggested that micro-pillar with D <; 3 μm showed high degree of strain relief. Our results shed new insights into designing strain-relieved InGaN/GaN microstructures for high brightness light emitting diode arrays.
{"title":"Strain relief InGaN/GaN MQW micro-pillars for high brightness LEDs","authors":"Chao Shen, T. Ng, B. Ooi, D. Cha","doi":"10.1109/SIECPC.2013.6550773","DOIUrl":"https://doi.org/10.1109/SIECPC.2013.6550773","url":null,"abstract":"Micro-structured group-III-nitrides are considered as promising strain relief structures for high efficiency solid state lighting. In this work, the strain field in InGaN/GaN multiquantum wells (MQWs) micro-pillars is investigated using micro-Raman spectroscopy and the design of micro-pillars were studied experimentally. We distinguished the strained and strain-relieved signatures of the GaN layer from the E2 phonon peak split from the Raman scattering signatures at 572 cm-1 and 568 cm-1, respectively. The extent of strain relief is examined considering the height and size of micro-pillars fabricated using focused ion beam (FIB) micro-machining technique. A significant strain relief can be achieved when one micro-machined through the entire epi-layers, 3 μm in our study. The dependence of strain relief on micro-pillar diameter (D) suggested that micro-pillar with D <; 3 μm showed high degree of strain relief. Our results shed new insights into designing strain-relieved InGaN/GaN microstructures for high brightness light emitting diode arrays.","PeriodicalId":427798,"journal":{"name":"2013 Saudi International Electronics, Communications and Photonics Conference","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132727722","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-27DOI: 10.1109/SIECPC.2013.6550793
M. Shedeed, G. Bahig, M. W. Elkharashi, M. Chen
Automotive systems are diverse, extensively interactive, and multi-disciplinary by nature. We propose a flow that integrates the different environments and tools needed for modeling and simulation of sub-components at each abstraction level, namely, Model in the Loop, Model-to-Software in the Loop, Software in the Loop, and Hardware in the Loop. The proposed flow verifies the system at each of these abstraction levels in the automotive domain. We present a systematic methodology and verification flow for a detailed migration procedure between these different abstraction levels to fulfill complicated automotive system requirements. Our flow has been tested using a brake-bywire anti-locking car system use case. Experimental results show the efficiency of the proposed flow in discovering early incorrect system behavior at each abstraction level. A common graphical test design and generation tool complements the proposed flow at each level to ensure that the generated tests address the same system functionality at each abstraction level and optimizes the cost of test design and generation.
{"title":"Functional design and verification of automotive embedded software: An integrated system verification flow","authors":"M. Shedeed, G. Bahig, M. W. Elkharashi, M. Chen","doi":"10.1109/SIECPC.2013.6550793","DOIUrl":"https://doi.org/10.1109/SIECPC.2013.6550793","url":null,"abstract":"Automotive systems are diverse, extensively interactive, and multi-disciplinary by nature. We propose a flow that integrates the different environments and tools needed for modeling and simulation of sub-components at each abstraction level, namely, Model in the Loop, Model-to-Software in the Loop, Software in the Loop, and Hardware in the Loop. The proposed flow verifies the system at each of these abstraction levels in the automotive domain. We present a systematic methodology and verification flow for a detailed migration procedure between these different abstraction levels to fulfill complicated automotive system requirements. Our flow has been tested using a brake-bywire anti-locking car system use case. Experimental results show the efficiency of the proposed flow in discovering early incorrect system behavior at each abstraction level. A common graphical test design and generation tool complements the proposed flow at each level to ensure that the generated tests address the same system functionality at each abstraction level and optimizes the cost of test design and generation.","PeriodicalId":427798,"journal":{"name":"2013 Saudi International Electronics, Communications and Photonics Conference","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114961556","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-04-27DOI: 10.1109/SIECPC.2013.6550975
I. Yahia, H. Zahran, M. El-sadek, A. Fatehmulla, W. Farooq, M. Aslam, S. Ali, M. Atif, F. Yakuphanoglu
Nano-structured platinum (Pt) thin film on fluorine doped tin oxide (FTO) coated on glass substrate was prepared via sputtering technique for quantum dot-sensitized solar cells (QDSSCs). Pt/FTO counter electrode surface morphology was studied using AFM images which revealed the nanorods collection on cylindrical tubes with film roughness 18.63 nm. Transmittance and reflectance measurements of FTO substrate as well as Pt/FTO were carried out in the wavelength range 200-2500 nm. Optical constants (n and k) were calculated at different wavelengths by applying Kramers-Kronig Transformations. The results obtained have been compared and discussed in terms of optimum conditions for a counter electrode. Our efforts are to establish a QDSSC based on nano Pt/FTO counter electrodes. Our work targets can enhance in the near future for photo-counter electrodes applied in QDSSCs.
{"title":"Optical properties of nano-structured Pt/FTO counter electrode for QDSSCs","authors":"I. Yahia, H. Zahran, M. El-sadek, A. Fatehmulla, W. Farooq, M. Aslam, S. Ali, M. Atif, F. Yakuphanoglu","doi":"10.1109/SIECPC.2013.6550975","DOIUrl":"https://doi.org/10.1109/SIECPC.2013.6550975","url":null,"abstract":"Nano-structured platinum (Pt) thin film on fluorine doped tin oxide (FTO) coated on glass substrate was prepared via sputtering technique for quantum dot-sensitized solar cells (QDSSCs). Pt/FTO counter electrode surface morphology was studied using AFM images which revealed the nanorods collection on cylindrical tubes with film roughness 18.63 nm. Transmittance and reflectance measurements of FTO substrate as well as Pt/FTO were carried out in the wavelength range 200-2500 nm. Optical constants (n and k) were calculated at different wavelengths by applying Kramers-Kronig Transformations. The results obtained have been compared and discussed in terms of optimum conditions for a counter electrode. Our efforts are to establish a QDSSC based on nano Pt/FTO counter electrodes. Our work targets can enhance in the near future for photo-counter electrodes applied in QDSSCs.","PeriodicalId":427798,"journal":{"name":"2013 Saudi International Electronics, Communications and Photonics Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124454534","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：