Pub Date : 2012-07-02DOI: 10.1109/HPCSim.2012.6266994
Idafen Santana-Pérez, M. Pérez-Hernández
Virtualized Infrastructures are a promising way for providing flexible and dynamic computing solutions for resource-consuming tasks. Scientific Workflows are one of these kind of tasks, as they need a large amount of computational resources during certain periods of time. To provide the best infrastructure configuration for a workflow it is necessary to explore as many providers as possible taking into account different criteria like Quality of Service, pricing, response time, network latency, etc. Moreover, each one of these new resources must be tuned to provide the tools and dependencies required by each of the steps of the workflow. Working with different infrastructure providers, either public or private using their own concepts and terms, and with a set of heterogeneous applications requires a framework for integrating all the information about these elements. This work proposes semantic technologies for describing and integrating all the information about the different components of the overall system and a set of policies created by the user. Based on this information a scheduling process will be performed to generate an infrastructure configuration defining the set of virtual machines that must be run and the tools that must be deployed on them.
{"title":"Semantic scheduling of virtualized infrastructures for scientific workflows","authors":"Idafen Santana-Pérez, M. Pérez-Hernández","doi":"10.1109/HPCSim.2012.6266994","DOIUrl":"https://doi.org/10.1109/HPCSim.2012.6266994","url":null,"abstract":"Virtualized Infrastructures are a promising way for providing flexible and dynamic computing solutions for resource-consuming tasks. Scientific Workflows are one of these kind of tasks, as they need a large amount of computational resources during certain periods of time. To provide the best infrastructure configuration for a workflow it is necessary to explore as many providers as possible taking into account different criteria like Quality of Service, pricing, response time, network latency, etc. Moreover, each one of these new resources must be tuned to provide the tools and dependencies required by each of the steps of the workflow. Working with different infrastructure providers, either public or private using their own concepts and terms, and with a set of heterogeneous applications requires a framework for integrating all the information about these elements. This work proposes semantic technologies for describing and integrating all the information about the different components of the overall system and a set of policies created by the user. Based on this information a scheduling process will be performed to generate an infrastructure configuration defining the set of virtual machines that must be run and the tools that must be deployed on them.","PeriodicalId":428764,"journal":{"name":"2012 International Conference on High Performance Computing & Simulation (HPCS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130941385","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-02DOI: 10.1109/HPCSim.2012.6266923
Haoyuan Ying, A. Jaiswal, K. Hofmann
3D ICs have emerged as promising solution for scalability, power consumption and performance demands of next generation Systems-on-Chip (SoCs). Along with the advantages, it also imposes lots of challenges in terms of cost, technological reliability, power, thermal budget and so forth. Networks-on-chip (NoCs), which is thoroughly investigated in 2D SoC design as scalable interconnects, is also well relevant to 3D IC Design. The cost of moving from 2D to 3D for any application should be justified with improvements in performance, power, latency and the utilization of Through-Silicon-Via (TSV). In this paper, we present two generalized routing algorithms for different reduced vertical channel density topologies, which can maintain the performance of the NoC and critically improve the utilization of TSV. The experiments for simulation were done in SystemC-RTL which can achieve more flexibility and maintain the cycle accuracy. From the experimental results in aspects of execution time, average throughput, system interconnect and TSV energy consumption, and TSV utilization, 50% vertical channel density topologies achieved the best trade-off for the given constrains.
{"title":"Deadlock-free routing algorithms for 3-dimension Networks-on-Chip with reduced vertical channel density topologies","authors":"Haoyuan Ying, A. Jaiswal, K. Hofmann","doi":"10.1109/HPCSim.2012.6266923","DOIUrl":"https://doi.org/10.1109/HPCSim.2012.6266923","url":null,"abstract":"3D ICs have emerged as promising solution for scalability, power consumption and performance demands of next generation Systems-on-Chip (SoCs). Along with the advantages, it also imposes lots of challenges in terms of cost, technological reliability, power, thermal budget and so forth. Networks-on-chip (NoCs), which is thoroughly investigated in 2D SoC design as scalable interconnects, is also well relevant to 3D IC Design. The cost of moving from 2D to 3D for any application should be justified with improvements in performance, power, latency and the utilization of Through-Silicon-Via (TSV). In this paper, we present two generalized routing algorithms for different reduced vertical channel density topologies, which can maintain the performance of the NoC and critically improve the utilization of TSV. The experiments for simulation were done in SystemC-RTL which can achieve more flexibility and maintain the cycle accuracy. From the experimental results in aspects of execution time, average throughput, system interconnect and TSV energy consumption, and TSV utilization, 50% vertical channel density topologies achieved the best trade-off for the given constrains.","PeriodicalId":428764,"journal":{"name":"2012 International Conference on High Performance Computing & Simulation (HPCS)","volume":"142 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134101663","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-02DOI: 10.1109/HPCSim.2012.6266998
Laura Fernández-Soria, J. Sánchez
Dendritic spines are a small protrusions from a neuron's dendrite that typically receives input from a single synapse of an axon. We propose an automatic method to obtain dendritic spines parameters, in terms of length, volume, angles and density.
{"title":"3D dendritic spine automatic detection and segmentation through samples obtained by confocal microscopy","authors":"Laura Fernández-Soria, J. Sánchez","doi":"10.1109/HPCSim.2012.6266998","DOIUrl":"https://doi.org/10.1109/HPCSim.2012.6266998","url":null,"abstract":"Dendritic spines are a small protrusions from a neuron's dendrite that typically receives input from a single synapse of an axon. We propose an automatic method to obtain dendritic spines parameters, in terms of length, volume, angles and density.","PeriodicalId":428764,"journal":{"name":"2012 International Conference on High Performance Computing & Simulation (HPCS)","volume":"228 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133818784","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-02DOI: 10.1109/HPCSim.2012.6266898
Aritz Barrondo, Andrei Tchernykh, S. E. Schaeffer, Johnatan E. Pecero
We address knowledge-free Bag-of-Tasks non-preemptive scheduling problem on heterogeneous grids, where scheduling decisions are free from information of resources and application characteristics. We consider a scheduling with task replications to overcome possible random bad resource allocation and ensure good performance. We analyze energy consumption of job allocation strategies based on variations of the replication threshold. In order to provide QoS and minimize energy consumption, we perform a joint analysis of two metrics. A case study is given and corresponding results indicate that proposed strategies reduce energy consumption without significant degradation in performance.
{"title":"Energy efficiency of knowledge-free scheduling in Peer-to-Peer Desktop Grids","authors":"Aritz Barrondo, Andrei Tchernykh, S. E. Schaeffer, Johnatan E. Pecero","doi":"10.1109/HPCSim.2012.6266898","DOIUrl":"https://doi.org/10.1109/HPCSim.2012.6266898","url":null,"abstract":"We address knowledge-free Bag-of-Tasks non-preemptive scheduling problem on heterogeneous grids, where scheduling decisions are free from information of resources and application characteristics. We consider a scheduling with task replications to overcome possible random bad resource allocation and ensure good performance. We analyze energy consumption of job allocation strategies based on variations of the replication threshold. In order to provide QoS and minimize energy consumption, we perform a joint analysis of two metrics. A case study is given and corresponding results indicate that proposed strategies reduce energy consumption without significant degradation in performance.","PeriodicalId":428764,"journal":{"name":"2012 International Conference on High Performance Computing & Simulation (HPCS)","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132749103","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-02DOI: 10.1109/HPCSim.2012.6266888
M. Villén-Altamirano
This paper is a tutorial on RESTART, a widely applicable accelerated simulation technique for estimating rare event probabilities. The method is based on performing a number of simulation retrials when the process enters regions of the state space where the chance of occurrence of the rare event is higher. The paper analyzes its efficiency, showing formulas for the gain obtained with respect to crude simulation and for the parameter values that maximize this gain. It also provides guidelines for the choice of the importance function, the function of the system state used for determining when retrials are made. Several examples on queuing networks and ultra reliable systems are exposed to illustrate the application of the guidelines and the efficiency achieved.
{"title":"Rare event simulation: The RESTART method","authors":"M. Villén-Altamirano","doi":"10.1109/HPCSim.2012.6266888","DOIUrl":"https://doi.org/10.1109/HPCSim.2012.6266888","url":null,"abstract":"This paper is a tutorial on RESTART, a widely applicable accelerated simulation technique for estimating rare event probabilities. The method is based on performing a number of simulation retrials when the process enters regions of the state space where the chance of occurrence of the rare event is higher. The paper analyzes its efficiency, showing formulas for the gain obtained with respect to crude simulation and for the parameter values that maximize this gain. It also provides guidelines for the choice of the importance function, the function of the system state used for determining when retrials are made. Several examples on queuing networks and ultra reliable systems are exposed to illustrate the application of the guidelines and the efficiency achieved.","PeriodicalId":428764,"journal":{"name":"2012 International Conference on High Performance Computing & Simulation (HPCS)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133497087","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-02DOI: 10.1109/HPCSim.2012.6266933
Gabriele Falace, Paolo Trunfio
Due to the decentralized nature of structured P2P systems, there is no a direct way for a single node of getting aggregate statistics about the whole network, such as its current size. In this paper we focus on the problem of estimating the size of one of the most popular structured P2P networks, Chord, using a sampling-based approach. With this approach, a node calculates an estimate of the network size after having queried a small number of its successors about some of their properties. We formally define three sampling-based algorithms that exploit well-known structural properties of a Chord network to derive an estimate of its size. An experimental evaluation was carried out through simulations to evaluate the accuracy of the three algorithms in different network scenarios. The evaluation allowed us to identify, among the three algorithms, a Ring Density Estimation (RDE) technique that was able to estimate the size of all the Chord networks considered with an average error of 2% or less, using only a few tens of sample nodes. Moreover, the simulation results showed that the RDE accuracy is not affected by dynamic network conditions, even in the presence of high nodes failure rates.
{"title":"An evaluation of sampling algorithms for estimating the size of a Chord network","authors":"Gabriele Falace, Paolo Trunfio","doi":"10.1109/HPCSim.2012.6266933","DOIUrl":"https://doi.org/10.1109/HPCSim.2012.6266933","url":null,"abstract":"Due to the decentralized nature of structured P2P systems, there is no a direct way for a single node of getting aggregate statistics about the whole network, such as its current size. In this paper we focus on the problem of estimating the size of one of the most popular structured P2P networks, Chord, using a sampling-based approach. With this approach, a node calculates an estimate of the network size after having queried a small number of its successors about some of their properties. We formally define three sampling-based algorithms that exploit well-known structural properties of a Chord network to derive an estimate of its size. An experimental evaluation was carried out through simulations to evaluate the accuracy of the three algorithms in different network scenarios. The evaluation allowed us to identify, among the three algorithms, a Ring Density Estimation (RDE) technique that was able to estimate the size of all the Chord networks considered with an average error of 2% or less, using only a few tens of sample nodes. Moreover, the simulation results showed that the RDE accuracy is not affected by dynamic network conditions, even in the presence of high nodes failure rates.","PeriodicalId":428764,"journal":{"name":"2012 International Conference on High Performance Computing & Simulation (HPCS)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114839247","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-02DOI: 10.1109/HPCSim.2012.6266924
Hana Krichene, M. Baklouti, M. Abid, P. Marquet, J. Dekeyser
The delay of instructions broadcast has a significant impact on the performance of Single Instruction Multiple Data (SIMD) architecture. This is especially true for massively parallel processing Systems-on-Chip (mppSoC), where the processing stage and that of setting up the communication mechanism need several clock periods. Subnetting is the strategy used to partition a single physical network into more than one smaller logical sub-networks (subnets). This technique better controls the broadcast instructions domain and the data traffic between network nodes. Furthermore, it allows to separate synchronous communications from asynchronous processing which maintains reliable communications and rapid processing through parallel processors. This paper describes the design of a communication model called broadcast with mask. This model is dedicated to mppSoC architecture with a huge number of processor elements because it maintains performances even when the number of processors increases. Simulation results and an FPGA implementation validate our approach.
{"title":"Broadcast with mask on a massively parallel processing on a chip","authors":"Hana Krichene, M. Baklouti, M. Abid, P. Marquet, J. Dekeyser","doi":"10.1109/HPCSim.2012.6266924","DOIUrl":"https://doi.org/10.1109/HPCSim.2012.6266924","url":null,"abstract":"The delay of instructions broadcast has a significant impact on the performance of Single Instruction Multiple Data (SIMD) architecture. This is especially true for massively parallel processing Systems-on-Chip (mppSoC), where the processing stage and that of setting up the communication mechanism need several clock periods. Subnetting is the strategy used to partition a single physical network into more than one smaller logical sub-networks (subnets). This technique better controls the broadcast instructions domain and the data traffic between network nodes. Furthermore, it allows to separate synchronous communications from asynchronous processing which maintains reliable communications and rapid processing through parallel processors. This paper describes the design of a communication model called broadcast with mask. This model is dedicated to mppSoC architecture with a huge number of processor elements because it maintains performances even when the number of processors increases. Simulation results and an FPGA implementation validate our approach.","PeriodicalId":428764,"journal":{"name":"2012 International Conference on High Performance Computing & Simulation (HPCS)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116038976","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-02DOI: 10.1109/HPCSim.2012.6266905
Julia D. Warnke-Sommer, Sachin Pawaskar, H. Ali
Current biomedical technologies are producing massive amounts of data on an unprecedented scale. The increasing complexity and growth rate of biological data has made bioinformatics data processing and analysis a key and computationally intensive task. High performance computing (HPC) has been successfully applied to major bioinformatics applications to reduce computational burden. However, a naïve approach for developing parallel bioinformatics applications may achieve a high degree of parallelism while unnecessarily expending computational resources and consuming high levels of energy. As the wealth of biological data and associated computational burden continues to increase, there has become a need for the development of energy efficient computational approaches in the bioinformatics domain. To address this issue, we have developed an energy-aware scheduling (EAS) model to run computationally intensive applications that takes both deadline requirements and energy factors into consideration. An example of a computationally demanding process that would benefit from our scheduling model is the assembly of short sequencing reads produced by next generation sequencing technologies. Next generation sequencing produces a very large number of short DNA reads from a biological sample. Multiple overlapping fragments must be aligned and merged into long stretches of contiguous sequence before any useful information can be gathered. The assembly problem is extremely difficult due to the complex nature of underlying genome structure and inherent biological error present in current sequencing technologies. We apply our EAS model to a newly proposed assembly algorithm called Merge and Traverse, giving us the ability to generate speedup profiles. Our EAS model was also able to dynamically adjust the number of nodes needed to meet given deadlines for different sets of reads.
{"title":"An energy-aware bioinformatics application for assembling short reads in high performance computing systems","authors":"Julia D. Warnke-Sommer, Sachin Pawaskar, H. Ali","doi":"10.1109/HPCSim.2012.6266905","DOIUrl":"https://doi.org/10.1109/HPCSim.2012.6266905","url":null,"abstract":"Current biomedical technologies are producing massive amounts of data on an unprecedented scale. The increasing complexity and growth rate of biological data has made bioinformatics data processing and analysis a key and computationally intensive task. High performance computing (HPC) has been successfully applied to major bioinformatics applications to reduce computational burden. However, a naïve approach for developing parallel bioinformatics applications may achieve a high degree of parallelism while unnecessarily expending computational resources and consuming high levels of energy. As the wealth of biological data and associated computational burden continues to increase, there has become a need for the development of energy efficient computational approaches in the bioinformatics domain. To address this issue, we have developed an energy-aware scheduling (EAS) model to run computationally intensive applications that takes both deadline requirements and energy factors into consideration. An example of a computationally demanding process that would benefit from our scheduling model is the assembly of short sequencing reads produced by next generation sequencing technologies. Next generation sequencing produces a very large number of short DNA reads from a biological sample. Multiple overlapping fragments must be aligned and merged into long stretches of contiguous sequence before any useful information can be gathered. The assembly problem is extremely difficult due to the complex nature of underlying genome structure and inherent biological error present in current sequencing technologies. We apply our EAS model to a newly proposed assembly algorithm called Merge and Traverse, giving us the ability to generate speedup profiles. Our EAS model was also able to dynamically adjust the number of nodes needed to meet given deadlines for different sets of reads.","PeriodicalId":428764,"journal":{"name":"2012 International Conference on High Performance Computing & Simulation (HPCS)","volume":"258 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122891204","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-02DOI: 10.1109/HPCSim.2012.6266892
Anthony Sulistio, Alexander Schulz, R. Keller, Panagiotis Kritikakos, Mourtzoukos Kostas, T. Varvarigou
The HPC-Europa2 project aims at uniting European scientists from various research areas with their respective scientific peers and collaborating in their specific fields, while making use of supercomputers at Europe's leading High Performance Computing (HPC) centers, i.e. BSC (Spain), CINECA (Italy), CSC (Finland), EPCC (UK), GENCI-CINES (France), HLRS (Germany), and SARA (Netherlands). In order to attract new fields and scientists from otherwise less HPC-involved scientific areas to the project, a live DVD has been built that provides parallel tools and libraries similar to the ones used by the aforementioned HPC centers (e.g. Torque, Paraver, and MPI). Thus, this live DVD emulates the environment of the platforms available at the HPC-Europa2 centers. By running the HPC-Europa2 live DVD under a hypervisor and/or booting from physical computers, users can build a virtual cluster, where they can learn more about parallel programming with recent tools and libraries without going through time-consuming installation procedures. As a result, the HPC-Europa2 live DVD provides a fool-proof e-learning and teaching experience.
{"title":"Building a virtual cluster using HPC-Europa2 live DVD","authors":"Anthony Sulistio, Alexander Schulz, R. Keller, Panagiotis Kritikakos, Mourtzoukos Kostas, T. Varvarigou","doi":"10.1109/HPCSim.2012.6266892","DOIUrl":"https://doi.org/10.1109/HPCSim.2012.6266892","url":null,"abstract":"The HPC-Europa2 project aims at uniting European scientists from various research areas with their respective scientific peers and collaborating in their specific fields, while making use of supercomputers at Europe's leading High Performance Computing (HPC) centers, i.e. BSC (Spain), CINECA (Italy), CSC (Finland), EPCC (UK), GENCI-CINES (France), HLRS (Germany), and SARA (Netherlands). In order to attract new fields and scientists from otherwise less HPC-involved scientific areas to the project, a live DVD has been built that provides parallel tools and libraries similar to the ones used by the aforementioned HPC centers (e.g. Torque, Paraver, and MPI). Thus, this live DVD emulates the environment of the platforms available at the HPC-Europa2 centers. By running the HPC-Europa2 live DVD under a hypervisor and/or booting from physical computers, users can build a virtual cluster, where they can learn more about parallel programming with recent tools and libraries without going through time-consuming installation procedures. As a result, the HPC-Europa2 live DVD provides a fool-proof e-learning and teaching experience.","PeriodicalId":428764,"journal":{"name":"2012 International Conference on High Performance Computing & Simulation (HPCS)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124705938","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-02DOI: 10.1109/HPCSim.2012.6266921
J. Núñez-Yáñez, A. Beldachi, A. Nabina, Mohammad Hosseinabady
This paper presents a toolset named NoRC (Network on a Reconfigurable Chip) designer and IP infrastructure designed to investigate the effects of partial dynamic reconfiguration in multicore designs mapped to commercial FPGAs. Dynamic reconfiguration means in this context that tiles and communication routers can be modified at run-time adapting to changes in application requirements, operating conditions and/or process variations. The NoRC system is oriented at avoiding any centralized control with functions mapped to tiles at runtime depending on processing capabilities and location. The dynamic nature of the platform means that following a request for an application from an external host any idle tile can be configured as a master able to make additional requests to nearby tiles or as a slave able to service the requests. NoRC designer is used in this paper to investigate possible task mapping strategies suitable for this type of adaptive platform and also the power and partial reconfiguration overheads of commercial FPGAs.
{"title":"Exploring dynamically reconfigurable multicore designs with NoRC designer","authors":"J. Núñez-Yáñez, A. Beldachi, A. Nabina, Mohammad Hosseinabady","doi":"10.1109/HPCSim.2012.6266921","DOIUrl":"https://doi.org/10.1109/HPCSim.2012.6266921","url":null,"abstract":"This paper presents a toolset named NoRC (Network on a Reconfigurable Chip) designer and IP infrastructure designed to investigate the effects of partial dynamic reconfiguration in multicore designs mapped to commercial FPGAs. Dynamic reconfiguration means in this context that tiles and communication routers can be modified at run-time adapting to changes in application requirements, operating conditions and/or process variations. The NoRC system is oriented at avoiding any centralized control with functions mapped to tiles at runtime depending on processing capabilities and location. The dynamic nature of the platform means that following a request for an application from an external host any idle tile can be configured as a master able to make additional requests to nearby tiles or as a slave able to service the requests. NoRC designer is used in this paper to investigate possible task mapping strategies suitable for this type of adaptive platform and also the power and partial reconfiguration overheads of commercial FPGAs.","PeriodicalId":428764,"journal":{"name":"2012 International Conference on High Performance Computing & Simulation (HPCS)","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124798298","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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