Pub Date : 2016-10-30DOI: 10.1109/ReConFig.2016.7857182
Paolo Di Febbo, S. Mattoccia, Carlo Dal Mutto
Image distortion correction is a critical preprocessing step for a variety of computer vision and image processing algorithms. Standard real-time software implementations are generally not suited for direct hardware porting, so appropriated versions need to be designed in order to obtain implementations deployable on FPGAs. In this paper, hardware-compatible techniques for image distortion correction are introduced and analyzed in details. The considered solutions are compared in terms of output quality by using a geometrical-error-based approach, with particular emphasis on robustness with respect to increasing lens distortion. The required amount of hardware resources is also estimated for each considered approach.
{"title":"Real-time image distortion correction: Analysis and evaluation of FPGA-compatible algorithms","authors":"Paolo Di Febbo, S. Mattoccia, Carlo Dal Mutto","doi":"10.1109/ReConFig.2016.7857182","DOIUrl":"https://doi.org/10.1109/ReConFig.2016.7857182","url":null,"abstract":"Image distortion correction is a critical preprocessing step for a variety of computer vision and image processing algorithms. Standard real-time software implementations are generally not suited for direct hardware porting, so appropriated versions need to be designed in order to obtain implementations deployable on FPGAs. In this paper, hardware-compatible techniques for image distortion correction are introduced and analyzed in details. The considered solutions are compared in terms of output quality by using a geometrical-error-based approach, with particular emphasis on robustness with respect to increasing lens distortion. The required amount of hardware resources is also estimated for each considered approach.","PeriodicalId":431909,"journal":{"name":"2016 International Conference on ReConFigurable Computing and FPGAs (ReConFig)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133316237","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ReConFig.2016.7857164
Akihiko Hamada, Hiroki Matsutani
Recently some researches to utilize big data efficiently have been made vigorously. To store and process big data, structured storages (NOSQLs) that have high degree of horizontal scalability have attracted a lot of attention. Key-value stores and column-oriented stores are known as famous examples of structured storages. Especially, column-oriented stores can store variable numbers of columns for each row while maintaining high scalability. Moreover, range queries (scan operations) are supported in column-oriented stores. This paper proposes hardware cache mechanism using FPGA NIC to accelerate column-oriented databases. In this paper, it is assumed that column-oriented stores running on database servers are accessed by clients via a network. This paper aims to improve performance and power efficiency of column-oriented stores by introducing an FPGA-based 10GbE network interface (NIC) and a hardware cache mechanism (HBC) implemented on the NIC. HBC stores query results (sorted rows) as a key-value form in the DRAM implemented on the FPGA NIC, and the requested data can be returned to clients immediately if the query result has been cached. Existing work that aims to accelerate structured storages by hardware have focused only on key-value stores while column-oriented stores that support range queries (scan operations) have not been addressed. HBC deploys methods that address data mappings and range queries of caches using specific data structures that can be represented in binary-tree forms and this paper shows HBC can accelerate range queries by hardware. In experiments of this paper, HBase is running on an application layer, while HBC is implemented on an FPGA-based NIC. This paper shows that improvement of power efficiency and significant performance improvement can be achieved by the proposed HBC and also pros and cons of the proposed HBC are discussed.
{"title":"Design and implementation of hardware cache mechanism and NIC for column-oriented databases","authors":"Akihiko Hamada, Hiroki Matsutani","doi":"10.1109/ReConFig.2016.7857164","DOIUrl":"https://doi.org/10.1109/ReConFig.2016.7857164","url":null,"abstract":"Recently some researches to utilize big data efficiently have been made vigorously. To store and process big data, structured storages (NOSQLs) that have high degree of horizontal scalability have attracted a lot of attention. Key-value stores and column-oriented stores are known as famous examples of structured storages. Especially, column-oriented stores can store variable numbers of columns for each row while maintaining high scalability. Moreover, range queries (scan operations) are supported in column-oriented stores. This paper proposes hardware cache mechanism using FPGA NIC to accelerate column-oriented databases. In this paper, it is assumed that column-oriented stores running on database servers are accessed by clients via a network. This paper aims to improve performance and power efficiency of column-oriented stores by introducing an FPGA-based 10GbE network interface (NIC) and a hardware cache mechanism (HBC) implemented on the NIC. HBC stores query results (sorted rows) as a key-value form in the DRAM implemented on the FPGA NIC, and the requested data can be returned to clients immediately if the query result has been cached. Existing work that aims to accelerate structured storages by hardware have focused only on key-value stores while column-oriented stores that support range queries (scan operations) have not been addressed. HBC deploys methods that address data mappings and range queries of caches using specific data structures that can be represented in binary-tree forms and this paper shows HBC can accelerate range queries by hardware. In experiments of this paper, HBase is running on an application layer, while HBC is implemented on an FPGA-based NIC. This paper shows that improvement of power efficiency and significant performance improvement can be achieved by the proposed HBC and also pros and cons of the proposed HBC are discussed.","PeriodicalId":431909,"journal":{"name":"2016 International Conference on ReConFigurable Computing and FPGAs (ReConFig)","volume":"49 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128375657","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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