Pub Date : 2013-10-02DOI: 10.1109/3DIC.2013.6702331
M. Brocard, C. Bermond, T. Lacrevaz, A. Farcy, P. L. Maitre, P. Scheer, P. Leduc, S. Chéramy, B. Fléchet
The introduction of TSVs is a major change of paradigm, which electrical impact on circuit functionality has to be carefully investigated. Specific test structures dedicated to characterize the substrate noise transfer function between aggressor TSVs and sensitive MOS transistors (N or P) were designed. For the first time, TSV to MOS gate and drain couplings were characterized through scattering parameter measurements up to 40 GHz. Substrate attenuation of perturbation generated by TSV increases from -60 dB to -20 dB with frequency. Coupling mechanism strongly depends on the MOS transistor state, up to 10 dB in difference being observed between ON and OFF. Coupling transfer function according of MOS transistor type is also extracted considering N, P, and isolated N MOS. Electrical coupling mechanism and dependency are explained through MOS to substrate coupling models, based on semi-conductor theory, enabling noise-based 3D design for future circuits.
{"title":"RF characterization of substrate coupling between TSV and MOS transistors in 3D integrated circuits","authors":"M. Brocard, C. Bermond, T. Lacrevaz, A. Farcy, P. L. Maitre, P. Scheer, P. Leduc, S. Chéramy, B. Fléchet","doi":"10.1109/3DIC.2013.6702331","DOIUrl":"https://doi.org/10.1109/3DIC.2013.6702331","url":null,"abstract":"The introduction of TSVs is a major change of paradigm, which electrical impact on circuit functionality has to be carefully investigated. Specific test structures dedicated to characterize the substrate noise transfer function between aggressor TSVs and sensitive MOS transistors (N or P) were designed. For the first time, TSV to MOS gate and drain couplings were characterized through scattering parameter measurements up to 40 GHz. Substrate attenuation of perturbation generated by TSV increases from -60 dB to -20 dB with frequency. Coupling mechanism strongly depends on the MOS transistor state, up to 10 dB in difference being observed between ON and OFF. Coupling transfer function according of MOS transistor type is also extracted considering N, P, and isolated N MOS. Electrical coupling mechanism and dependency are explained through MOS to substrate coupling models, based on semi-conductor theory, enabling noise-based 3D design for future circuits.","PeriodicalId":432423,"journal":{"name":"2013 IEEE International 3D Systems Integration Conference (3DIC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123763390","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-02DOI: 10.1109/3DIC.2013.6702342
V. Pangracious, H. Mehrez, Z. Marrakchi
The CMOS technology scaling has greatly improved the overall performance and density of the Mesh-based Field Programmable Gate Arrays (FPGAs), nonetheless the gap between FPGAs and ASICs in terms of logic density, speed and power consumption remains very wide mainly due the programming overhead. The logic density and area overhead is improved by using Tree-based FPGA architecture using Butterfly-Fat-Tree (BFT) based network topology. However the wire-length increases exponentially as the tree grows to higher levels. We have introduced a horizontally partitioned 3-dimensional (3D) design methodology to optimize the BFT based programmable interconnect delay of the Tree-based FPGA. In this paper we describe a 2 tier horizontally partitioned 3D stacked Tree-based FPGA demonstrator, designed and implemented using Tezzaron's 130nm, 3D technology. We finally evaluate the speed and area overhead of the proposed 3D Tree-based FPGA using the newly developed experimental design and evaluation methodology and show that the horizontally partitioned BFT programmable interconnect topology based 3D Tree-based FPGA improves speed by 2.06 times and reduce interconnect area by 2.8 times compared to 3D Mesh-based FPGA with identical logic resources.
{"title":"Designing a 3D tree-based FPGA: Optimization of butterfly programmable interconnect topology using 3D technology","authors":"V. Pangracious, H. Mehrez, Z. Marrakchi","doi":"10.1109/3DIC.2013.6702342","DOIUrl":"https://doi.org/10.1109/3DIC.2013.6702342","url":null,"abstract":"The CMOS technology scaling has greatly improved the overall performance and density of the Mesh-based Field Programmable Gate Arrays (FPGAs), nonetheless the gap between FPGAs and ASICs in terms of logic density, speed and power consumption remains very wide mainly due the programming overhead. The logic density and area overhead is improved by using Tree-based FPGA architecture using Butterfly-Fat-Tree (BFT) based network topology. However the wire-length increases exponentially as the tree grows to higher levels. We have introduced a horizontally partitioned 3-dimensional (3D) design methodology to optimize the BFT based programmable interconnect delay of the Tree-based FPGA. In this paper we describe a 2 tier horizontally partitioned 3D stacked Tree-based FPGA demonstrator, designed and implemented using Tezzaron's 130nm, 3D technology. We finally evaluate the speed and area overhead of the proposed 3D Tree-based FPGA using the newly developed experimental design and evaluation methodology and show that the horizontally partitioned BFT programmable interconnect topology based 3D Tree-based FPGA improves speed by 2.06 times and reduce interconnect area by 2.8 times compared to 3D Mesh-based FPGA with identical logic resources.","PeriodicalId":432423,"journal":{"name":"2013 IEEE International 3D Systems Integration Conference (3DIC)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123528776","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/3DIC.2013.6702376
D. Jung, Jonghyun Cho, Heegon Kim, Jonghoon J. Kim, Hongseok Kim, Joungho Kim, Hyun-Cheol Bae, Kwang-Seong Choi
Development of through silicon via (TSV) based 3 dimensional integrated circuit (3D-IC) has allowed reduction of form factor and power consumption with higher data transmission speed. Despite the great advantages, various types of defects cannot be avoided in continuously reducing scale of the components. The performance degradation caused by defects has to be analyzed to increase the yield of the products. In this paper, the effect of short defect in TSV channel is analyzed in frequency- and time-domain. A GSG-type daisy-chain structure with eight TSVs per channel is designed for 3D EM simulation and the results are obtained in S-parameter curves and TDR waveforms. Using 2-port analysis, the results from two ends of the channel are compared. The location of short defect is varied for case analysis. Under the assumption that the defect is located closer to one port than the other, the asymmetric structure results in distinguishable S11 and S22. Similarly, TDR waveforms from port 1 and port 2 are compared for fault isolation. By taking the difference between the results from port 1 and port 2, the short defect in TSV channel can be accurately detected and isolated.
{"title":"Fault isolation of short defect in through silicon via (TSV) based 3D-IC","authors":"D. Jung, Jonghyun Cho, Heegon Kim, Jonghoon J. Kim, Hongseok Kim, Joungho Kim, Hyun-Cheol Bae, Kwang-Seong Choi","doi":"10.1109/3DIC.2013.6702376","DOIUrl":"https://doi.org/10.1109/3DIC.2013.6702376","url":null,"abstract":"Development of through silicon via (TSV) based 3 dimensional integrated circuit (3D-IC) has allowed reduction of form factor and power consumption with higher data transmission speed. Despite the great advantages, various types of defects cannot be avoided in continuously reducing scale of the components. The performance degradation caused by defects has to be analyzed to increase the yield of the products. In this paper, the effect of short defect in TSV channel is analyzed in frequency- and time-domain. A GSG-type daisy-chain structure with eight TSVs per channel is designed for 3D EM simulation and the results are obtained in S-parameter curves and TDR waveforms. Using 2-port analysis, the results from two ends of the channel are compared. The location of short defect is varied for case analysis. Under the assumption that the defect is located closer to one port than the other, the asymmetric structure results in distinguishable S11 and S22. Similarly, TDR waveforms from port 1 and port 2 are compared for fault isolation. By taking the difference between the results from port 1 and port 2, the short defect in TSV channel can be accurately detected and isolated.","PeriodicalId":432423,"journal":{"name":"2013 IEEE International 3D Systems Integration Conference (3DIC)","volume":"22 13","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113976418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/3DIC.2013.6702389
Yang Yi, Yaping Zhou
Electrical modeling of Through Silicon Vias (TSVs) is very important for three dimensional (3D) system design and analysis. It has attracted much research attention in recent years. Most of the previous research focuses on fitting circuit parameters to the frequency response obtained from measurements or full-wave discretization based electromagnetic simulations. The extension of these methods to multiple TSVs can be challenging because of the significant increase in computational cost. In this paper, we proposed a novel circuit model for multiple TSVs. Since frequent switching of high speed signals can dynamically bias TSV metal insulator semiconductor (MIS) interface and allocate TSV MIS into accumulation or depletion regions, the TSV capacitance is nonlinear and dependent on the biasing of the TSVs. An analytical expression for capacitance is introduced and a new circuit model is proposed accordingly. The circuit model accurately captures all the parasitic elements of various TSVs arrangements and accounts for wide frequency range, high frequency skin effect, eddy currents in substrate, and metal oxide semiconductor (MOS) effect.
{"title":"A novel circuit model for multiple Through Silicon Vias (TSVs) in 3D IC","authors":"Yang Yi, Yaping Zhou","doi":"10.1109/3DIC.2013.6702389","DOIUrl":"https://doi.org/10.1109/3DIC.2013.6702389","url":null,"abstract":"Electrical modeling of Through Silicon Vias (TSVs) is very important for three dimensional (3D) system design and analysis. It has attracted much research attention in recent years. Most of the previous research focuses on fitting circuit parameters to the frequency response obtained from measurements or full-wave discretization based electromagnetic simulations. The extension of these methods to multiple TSVs can be challenging because of the significant increase in computational cost. In this paper, we proposed a novel circuit model for multiple TSVs. Since frequent switching of high speed signals can dynamically bias TSV metal insulator semiconductor (MIS) interface and allocate TSV MIS into accumulation or depletion regions, the TSV capacitance is nonlinear and dependent on the biasing of the TSVs. An analytical expression for capacitance is introduced and a new circuit model is proposed accordingly. The circuit model accurately captures all the parasitic elements of various TSVs arrangements and accounts for wide frequency range, high frequency skin effect, eddy currents in substrate, and metal oxide semiconductor (MOS) effect.","PeriodicalId":432423,"journal":{"name":"2013 IEEE International 3D Systems Integration Conference (3DIC)","volume":"127 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134373705","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/3DIC.2013.6702369
K. Ghosh, C. C. Yap, B. Tay, C. S. Tan
The availability of high density TSVs depends on how smart we miniaturize the interconnect dimension in 3D IC package. A number of considerations include controllable TSV aspect ratio, pitch, and material selection. The International Technology Roadmap for Semiconductors (ITRS) has proposed scaling of TSV diameter down to as low as 2 μm in the future. However, with TSV scaling, the resistance of the TSV increases significantly. Carbon nanotubes (CNTs) could be a potential alternative material to Cu for VLSI interconnects applications, including TSV, due to their outstanding electrical, mechanical, and thermal properties. Here, we demonstrate a method to integrate carbon nanotubes (CNTs)-filled TSV under 5 μm diameter that are connected by metal-lines at the bottom and show the facile route of fabrication at low temperature regime. The process challenges are highlighted.
{"title":"Integration of CNT in TSV (≤5 μm) for 3D IC application and its process challenges","authors":"K. Ghosh, C. C. Yap, B. Tay, C. S. Tan","doi":"10.1109/3DIC.2013.6702369","DOIUrl":"https://doi.org/10.1109/3DIC.2013.6702369","url":null,"abstract":"The availability of high density TSVs depends on how smart we miniaturize the interconnect dimension in 3D IC package. A number of considerations include controllable TSV aspect ratio, pitch, and material selection. The International Technology Roadmap for Semiconductors (ITRS) has proposed scaling of TSV diameter down to as low as 2 μm in the future. However, with TSV scaling, the resistance of the TSV increases significantly. Carbon nanotubes (CNTs) could be a potential alternative material to Cu for VLSI interconnects applications, including TSV, due to their outstanding electrical, mechanical, and thermal properties. Here, we demonstrate a method to integrate carbon nanotubes (CNTs)-filled TSV under 5 μm diameter that are connected by metal-lines at the bottom and show the facile route of fabrication at low temperature regime. The process challenges are highlighted.","PeriodicalId":432423,"journal":{"name":"2013 IEEE International 3D Systems Integration Conference (3DIC)","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132614244","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/3DIC.2013.6702348
Qiuling Zhu, Berkin Akin, H. Sumbul, Fazle Sadi, J. Hoe, L. Pileggi, F. Franchetti
This paper introduces a 3D-stacked logic-in-memory (LiM) system that integrates the 3D die-stacked DRAM architecture with the application-specific LiM IC to accelerate important data-intensive computing. The proposed system comprises a fine-grained rank-level 3D die-stacked DRAM device and extra LiM layers implementing logic-enhanced SRAM blocks that are dedicated to a particular application. Through silicon vias (TSVs) are used for vertical interconnections providing the required bandwidth to support the high performance LiM computing. We performed a comprehensive 3D DRAM design space exploration and exploit the efficient architectures to accelerate the computing that can balance the performance and power. Our experiments demonstrate orders of magnitude of performance and power efficiency improvements compared with the traditional multithreaded software implementation on modern CPU.
{"title":"A 3D-stacked logic-in-memory accelerator for application-specific data intensive computing","authors":"Qiuling Zhu, Berkin Akin, H. Sumbul, Fazle Sadi, J. Hoe, L. Pileggi, F. Franchetti","doi":"10.1109/3DIC.2013.6702348","DOIUrl":"https://doi.org/10.1109/3DIC.2013.6702348","url":null,"abstract":"This paper introduces a 3D-stacked logic-in-memory (LiM) system that integrates the 3D die-stacked DRAM architecture with the application-specific LiM IC to accelerate important data-intensive computing. The proposed system comprises a fine-grained rank-level 3D die-stacked DRAM device and extra LiM layers implementing logic-enhanced SRAM blocks that are dedicated to a particular application. Through silicon vias (TSVs) are used for vertical interconnections providing the required bandwidth to support the high performance LiM computing. We performed a comprehensive 3D DRAM design space exploration and exploit the efficient architectures to accelerate the computing that can balance the performance and power. Our experiments demonstrate orders of magnitude of performance and power efficiency improvements compared with the traditional multithreaded software implementation on modern CPU.","PeriodicalId":432423,"journal":{"name":"2013 IEEE International 3D Systems Integration Conference (3DIC)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124160485","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/3DIC.2013.6702365
Awet Yemane Weldezion, M. Grange, D. Pamunuwa, A. Jantsch, H. Tenhunen
This paper describes a powerful simulation platform that enables accurate simulations of numerous network configurations under realistic traffic patterns to predict the performance and power needs of a 3-D integrated system early in the design flow. The simulation platform can model virtually any sized 2-D or 3-D network configuration, providing low-cost and fast tradeoff evaluations of various systems architectures. The network simulator uses scalable RTL-level models that can be used for accurate power and timing analyses. We demonstrate the capability of our simulation model by analyzing the performance of various network topologies under spatio-temporal traffic patterns to show how the network topology can be adjusted to meet the performance requirements of a design before it is manufactured. The simulation results can be used to optimize the placement of cores and communication buses early in the flow. By using the model, standard applications such as mobile application processor, femto-cell base-stations on-chip and wide-IO TSV memory stacking can be simulated.
{"title":"A scalable multi-dimensional NoC simulation model for diverse spatio-temporal traffic patterns","authors":"Awet Yemane Weldezion, M. Grange, D. Pamunuwa, A. Jantsch, H. Tenhunen","doi":"10.1109/3DIC.2013.6702365","DOIUrl":"https://doi.org/10.1109/3DIC.2013.6702365","url":null,"abstract":"This paper describes a powerful simulation platform that enables accurate simulations of numerous network configurations under realistic traffic patterns to predict the performance and power needs of a 3-D integrated system early in the design flow. The simulation platform can model virtually any sized 2-D or 3-D network configuration, providing low-cost and fast tradeoff evaluations of various systems architectures. The network simulator uses scalable RTL-level models that can be used for accurate power and timing analyses. We demonstrate the capability of our simulation model by analyzing the performance of various network topologies under spatio-temporal traffic patterns to show how the network topology can be adjusted to meet the performance requirements of a design before it is manufactured. The simulation results can be used to optimize the placement of cores and communication buses early in the flow. By using the model, standard applications such as mobile application processor, femto-cell base-stations on-chip and wide-IO TSV memory stacking can be simulated.","PeriodicalId":432423,"journal":{"name":"2013 IEEE International 3D Systems Integration Conference (3DIC)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116818509","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/3DIC.2013.6702358
Mohammad A. Ahmed, M. Chrzanowska-Jeske
3D-IC design facilitates reduction in wirelength by vertically stacking dies. Through-silicon-vias (TSVs) are used to connect inter-die signals. The dynamic power consumption of interconnects in 3D-IC is contributed by wires, buffers and TSVs. The delay in interconnects for 3D-IC is greatly influence by TSV capacitance. In this paper we propose TSV capacitance-aware 3D floorplanning to reduce the delay and dynamic power consumption in 3D-interconnects. The TSVs with specified dimensions and pitch are positioned in islands. TSV islands offer advantages over individual TSVs like reduced stress impact and more efficient inclusion of redundancy. TSV capacitance depends on TSV dimensions, pitch and wire technology. TSV capacitance aware floorplanning reduces power consumption in interconnects on average by 7% when using Cu-TSVs and 9% for W-TSVs. The approach also reduces peak delay for nets using Cu based TSVs on average by 15% and W based TSVs by 21%.
{"title":"TSV capacitance aware 3-D floorplanning","authors":"Mohammad A. Ahmed, M. Chrzanowska-Jeske","doi":"10.1109/3DIC.2013.6702358","DOIUrl":"https://doi.org/10.1109/3DIC.2013.6702358","url":null,"abstract":"3D-IC design facilitates reduction in wirelength by vertically stacking dies. Through-silicon-vias (TSVs) are used to connect inter-die signals. The dynamic power consumption of interconnects in 3D-IC is contributed by wires, buffers and TSVs. The delay in interconnects for 3D-IC is greatly influence by TSV capacitance. In this paper we propose TSV capacitance-aware 3D floorplanning to reduce the delay and dynamic power consumption in 3D-interconnects. The TSVs with specified dimensions and pitch are positioned in islands. TSV islands offer advantages over individual TSVs like reduced stress impact and more efficient inclusion of redundancy. TSV capacitance depends on TSV dimensions, pitch and wire technology. TSV capacitance aware floorplanning reduces power consumption in interconnects on average by 7% when using Cu-TSVs and 9% for W-TSVs. The approach also reduces peak delay for nets using Cu based TSVs on average by 15% and W based TSVs by 21%.","PeriodicalId":432423,"journal":{"name":"2013 IEEE International 3D Systems Integration Conference (3DIC)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124795464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/3DIC.2013.6702355
Jae Hak Lee, H. Kim, J. Song, C. Lee, T. Ha
TSV (Through-Silicon Via) 3D packaging technology has been and continues to be investigated by many of the semiconductor manufacturer and research institute as a practical way to achieve higher performance and smaller form factors. Compared with conventional 2D packaging, this can increase packing density and reduce power consumption dramatically because of shorter interconnection by vertical directional stacking. So far 3D stacking technology based on W2W bonding has developed widely such as 3D Image sensor and 3D stacking memory because it has the advantage of easier alignment and higher throughput compared with chip-to-chip bonding. However, the wafer level 3D stacking method can be only applicable to products with high production yield because overall yield of 3D stacking chips depends on the yield of multiple stacked layers. In this paper, we suggested wafer level build-up stacking process using oxide bonding and molten metal filling newly, which temporary bonding process is unnecessary and demonstrated it through experiments. Thermal stress analysis was carried out to compare the structural reliability between conventional TSV and the proposed TSV model. The simulation results indicate that the proposed TSV model is more reliable than the conventional model with respect to stress in the stack chip.
{"title":"A study on wafer level TSV build-up integration method","authors":"Jae Hak Lee, H. Kim, J. Song, C. Lee, T. Ha","doi":"10.1109/3DIC.2013.6702355","DOIUrl":"https://doi.org/10.1109/3DIC.2013.6702355","url":null,"abstract":"TSV (Through-Silicon Via) 3D packaging technology has been and continues to be investigated by many of the semiconductor manufacturer and research institute as a practical way to achieve higher performance and smaller form factors. Compared with conventional 2D packaging, this can increase packing density and reduce power consumption dramatically because of shorter interconnection by vertical directional stacking. So far 3D stacking technology based on W2W bonding has developed widely such as 3D Image sensor and 3D stacking memory because it has the advantage of easier alignment and higher throughput compared with chip-to-chip bonding. However, the wafer level 3D stacking method can be only applicable to products with high production yield because overall yield of 3D stacking chips depends on the yield of multiple stacked layers. In this paper, we suggested wafer level build-up stacking process using oxide bonding and molten metal filling newly, which temporary bonding process is unnecessary and demonstrated it through experiments. Thermal stress analysis was carried out to compare the structural reliability between conventional TSV and the proposed TSV model. The simulation results indicate that the proposed TSV model is more reliable than the conventional model with respect to stress in the stack chip.","PeriodicalId":432423,"journal":{"name":"2013 IEEE International 3D Systems Integration Conference (3DIC)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127274942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-01DOI: 10.1109/3DIC.2013.6702391
Jonghyun Cho, Youngwoo Kim, Joungho Kim, V. Sundaram, R. Tummala
Electrical characteristics of glass interposer PDN is analyzed and compared with silicon interposer. Because of the low loss of glass substrate compared to silicon substrate, glass interposer has much smaller loss than silicon interposer. It helps low-loss signaling, but it generates sharp PDN resonance unlike silicon interposer. If glass interposer signal line has through-glass via (TGV), it experiences high loss at the resonance frequency. Also P/G noise is easily coupled to signal line and vice versa at that frequency. It would be problems for the glass interposer PDN design. To overcome these problems of glass interposer, several resonance suppression methods are proposed such as decoupling capacitor scheme, ground via.
{"title":"Analysis of glass interposer PDN and proposal of PDN resonance suppression methods","authors":"Jonghyun Cho, Youngwoo Kim, Joungho Kim, V. Sundaram, R. Tummala","doi":"10.1109/3DIC.2013.6702391","DOIUrl":"https://doi.org/10.1109/3DIC.2013.6702391","url":null,"abstract":"Electrical characteristics of glass interposer PDN is analyzed and compared with silicon interposer. Because of the low loss of glass substrate compared to silicon substrate, glass interposer has much smaller loss than silicon interposer. It helps low-loss signaling, but it generates sharp PDN resonance unlike silicon interposer. If glass interposer signal line has through-glass via (TGV), it experiences high loss at the resonance frequency. Also P/G noise is easily coupled to signal line and vice versa at that frequency. It would be problems for the glass interposer PDN design. To overcome these problems of glass interposer, several resonance suppression methods are proposed such as decoupling capacitor scheme, ground via.","PeriodicalId":432423,"journal":{"name":"2013 IEEE International 3D Systems Integration Conference (3DIC)","volume":"29 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132434437","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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