Pub Date : 2019-08-01DOI: 10.1109/NVMSA.2019.8863528
Fuyang Li, Qing'an Li, C. Xue
Since the energy source is unstable in energy harvesting powered systems, checkpointing is a must for the energy harvesting powered systems. Non-volatile memory is used for keeping the persistence for the systems. However, it may also bring new problems for the systems, which are the inconsistency errors induced during program execution. In this work, we propose a checkpointing-aware data allocation method to reduce the total cost of checkpointing and program execution without the inconsistency errors. The experimental results show that the proposed method achieves 71.2% dynamic energy consumption reduction of checkpointing and program execution, and 9.9% reduction of total checkpointing and program execution time on average compared to the previous work without the inconsistency errors.
{"title":"Checkpointing-aware Data Allocation for Energy Harvesting Powered Non-volatile Processors","authors":"Fuyang Li, Qing'an Li, C. Xue","doi":"10.1109/NVMSA.2019.8863528","DOIUrl":"https://doi.org/10.1109/NVMSA.2019.8863528","url":null,"abstract":"Since the energy source is unstable in energy harvesting powered systems, checkpointing is a must for the energy harvesting powered systems. Non-volatile memory is used for keeping the persistence for the systems. However, it may also bring new problems for the systems, which are the inconsistency errors induced during program execution. In this work, we propose a checkpointing-aware data allocation method to reduce the total cost of checkpointing and program execution without the inconsistency errors. The experimental results show that the proposed method achieves 71.2% dynamic energy consumption reduction of checkpointing and program execution, and 9.9% reduction of total checkpointing and program execution time on average compared to the previous work without the inconsistency errors.","PeriodicalId":438544,"journal":{"name":"2019 IEEE Non-Volatile Memory Systems and Applications Symposium (NVMSA)","volume":"150 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123218145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-08-01DOI: 10.1109/NVMSA.2019.8863516
Xinsheng Wang, Bin Sun
In this paper, the compressive sensing theory is applied to the integrated circuit compression modeling. The microprocessor chip is divided into a number of dense micro-regions, and the temperature information of each region in a certain time domain is collected to form a temperature parameter matrix of the time domain and the region. The high-dimensional temperature parameter matrix is mapped to the low-dimensional space by principal component analysis to obtain the critical point temperature of the chip. By observing the critical point temperature, the chip can be used to recover the temperature parameter of the dense distribution. This is the compression modeling method of integrated circuit chips, which is of great significance for the early warning and protection of integrated circuit reliability. The experiment compares the effects of the compressed sensing modeling method and the traditional modeling method. The experimental results show that the recovery efficiency and accuracy of the model are improved by nearly 1.5 times.
{"title":"Effective Compression Modeling for Packaged Integrated Circuit with Compressive Sensing","authors":"Xinsheng Wang, Bin Sun","doi":"10.1109/NVMSA.2019.8863516","DOIUrl":"https://doi.org/10.1109/NVMSA.2019.8863516","url":null,"abstract":"In this paper, the compressive sensing theory is applied to the integrated circuit compression modeling. The microprocessor chip is divided into a number of dense micro-regions, and the temperature information of each region in a certain time domain is collected to form a temperature parameter matrix of the time domain and the region. The high-dimensional temperature parameter matrix is mapped to the low-dimensional space by principal component analysis to obtain the critical point temperature of the chip. By observing the critical point temperature, the chip can be used to recover the temperature parameter of the dense distribution. This is the compression modeling method of integrated circuit chips, which is of great significance for the early warning and protection of integrated circuit reliability. The experiment compares the effects of the compressed sensing modeling method and the traditional modeling method. The experimental results show that the recovery efficiency and accuracy of the model are improved by nearly 1.5 times.","PeriodicalId":438544,"journal":{"name":"2019 IEEE Non-Volatile Memory Systems and Applications Symposium (NVMSA)","volume":"109 7","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120841971","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-08-01DOI: 10.1109/NVMSA.2019.8863518
Miao-Chiang Yen, Li-Pin Chang
This study provides a deep analysis of the write inflation problem in mobile I/O stack, which concerns the lifetime of flash-based mobile storage. We identified that write inflation is closely related to data duplication: File systems and embedded databases introduce behavior data duplication for transaction management and space re-organization. The block interface creates sub-block data duplication by writing coarse-grain blocks for tiny updates. Applications and embedded databases repeatedly write zero blocks for file scrubbing. Based on our analysis, we advocate to reconfigure and redesign the current mobile I/O stack for write conserving.
{"title":"How and Why does Mobile I/O Stack Inflate Writes?","authors":"Miao-Chiang Yen, Li-Pin Chang","doi":"10.1109/NVMSA.2019.8863518","DOIUrl":"https://doi.org/10.1109/NVMSA.2019.8863518","url":null,"abstract":"This study provides a deep analysis of the write inflation problem in mobile I/O stack, which concerns the lifetime of flash-based mobile storage. We identified that write inflation is closely related to data duplication: File systems and embedded databases introduce behavior data duplication for transaction management and space re-organization. The block interface creates sub-block data duplication by writing coarse-grain blocks for tiny updates. Applications and embedded databases repeatedly write zero blocks for file scrubbing. Based on our analysis, we advocate to reconfigure and redesign the current mobile I/O stack for write conserving.","PeriodicalId":438544,"journal":{"name":"2019 IEEE Non-Volatile Memory Systems and Applications Symposium (NVMSA)","volume":"290 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122794863","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-08-01DOI: 10.1109/nvmsa.2019.8863510
{"title":"NVMSA 2019 Organizer and Sponsors","authors":"","doi":"10.1109/nvmsa.2019.8863510","DOIUrl":"https://doi.org/10.1109/nvmsa.2019.8863510","url":null,"abstract":"","PeriodicalId":438544,"journal":{"name":"2019 IEEE Non-Volatile Memory Systems and Applications Symposium (NVMSA)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116924486","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-08-01DOI: 10.1109/NVMSA.2019.8863526
H. Shu, H. Liu, Hongyu Chen, Youyou Lu, J. Shu
At present, most existing persistent memory programming libraries use write-ahead-logging(WAL) technology to ensure the consistency of memory allocating and updating process. In the application where persistent memory is frequently updated, this approach will bring a serious impact on system performance. In this work, we carefully analyzed the actual requirements of the applications and propose an optimized release mechanism for persistent memory called Luna_TX. In the improved mechanism, we remove the memory releasing phases of logs and objects from the critical path and generating in the process of update and release of transactions is delayed to the execution out of the transaction, which reduces the performance overhead on the critical paths. The experimental results have shown that the proposed mechanism can reduce the transaction delay significantly and boost up the whole transaction performance at 59%.
{"title":"Luna-TX: An Optimized Transactional Mechanism for Persistent Memory","authors":"H. Shu, H. Liu, Hongyu Chen, Youyou Lu, J. Shu","doi":"10.1109/NVMSA.2019.8863526","DOIUrl":"https://doi.org/10.1109/NVMSA.2019.8863526","url":null,"abstract":"At present, most existing persistent memory programming libraries use write-ahead-logging(WAL) technology to ensure the consistency of memory allocating and updating process. In the application where persistent memory is frequently updated, this approach will bring a serious impact on system performance. In this work, we carefully analyzed the actual requirements of the applications and propose an optimized release mechanism for persistent memory called Luna_TX. In the improved mechanism, we remove the memory releasing phases of logs and objects from the critical path and generating in the process of update and release of transactions is delayed to the execution out of the transaction, which reduces the performance overhead on the critical paths. The experimental results have shown that the proposed mechanism can reduce the transaction delay significantly and boost up the whole transaction performance at 59%.","PeriodicalId":438544,"journal":{"name":"2019 IEEE Non-Volatile Memory Systems and Applications Symposium (NVMSA)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132237215","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-08-01DOI: 10.1109/NVMSA.2019.8863520
Shiqiang Nie, Youtao Zhang, Weiguo Wu, Chi Zhang, Jun Yang
TLC (Triple-Level Cell) NAND flash is increasingly adopted to build SSDs (Solid-State Drives) for modern computer systems. While TLC NAND flash effectively improves storage density, it faces severe reliability issues, in particular, the pages stored using different bits exhibit different BERs (bit error rates). Integrating strong LDPC (Low-Density Parity-Check code) helps to improve reliability but suffers from long and proportional read latency due to multiple read retries. In this paper, we propose DIR, a novel strategy for improving the performance of TLC NAND flash-based SSDs, in particular, the aged ones with large BERs. DIR exploits the observation that the latency of an I/O request is determined, without considering the queuing time, by the access of the slowest device page, i.e., the page that has the highest BER. By grouping consecutive logical pages that have high locality, and interleaving their encoded data in three different types of device pages that have different RBERs, DIR effectively reduces the number of read retries for LDPC. Our experimental results show that adopting DIR in aged SSDs exploits nearly 75% locality from I/O requests, and, on average, reduces 36% read latency over conventional aged SSDs.
{"title":"DIR: Dynamic Request Interleaving for Improving the Read Performance of Aged SSDs","authors":"Shiqiang Nie, Youtao Zhang, Weiguo Wu, Chi Zhang, Jun Yang","doi":"10.1109/NVMSA.2019.8863520","DOIUrl":"https://doi.org/10.1109/NVMSA.2019.8863520","url":null,"abstract":"TLC (Triple-Level Cell) NAND flash is increasingly adopted to build SSDs (Solid-State Drives) for modern computer systems. While TLC NAND flash effectively improves storage density, it faces severe reliability issues, in particular, the pages stored using different bits exhibit different BERs (bit error rates). Integrating strong LDPC (Low-Density Parity-Check code) helps to improve reliability but suffers from long and proportional read latency due to multiple read retries. In this paper, we propose DIR, a novel strategy for improving the performance of TLC NAND flash-based SSDs, in particular, the aged ones with large BERs. DIR exploits the observation that the latency of an I/O request is determined, without considering the queuing time, by the access of the slowest device page, i.e., the page that has the highest BER. By grouping consecutive logical pages that have high locality, and interleaving their encoded data in three different types of device pages that have different RBERs, DIR effectively reduces the number of read retries for LDPC. Our experimental results show that adopting DIR in aged SSDs exploits nearly 75% locality from I/O requests, and, on average, reduces 36% read latency over conventional aged SSDs.","PeriodicalId":438544,"journal":{"name":"2019 IEEE Non-Volatile Memory Systems and Applications Symposium (NVMSA)","volume":"268 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123446250","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-08-01DOI: 10.1109/NVMSA.2019.8863527
Lei Han, H. Amrouch, Z. Shao, J. Henkel
The lifetime of NAND flash cells significantly degrades with feature-size reductions and multi-level cell technology. On the other hand, we have more and more approximate data such as images and video that can tolerate errors. In this paper, we propose Rebirth-FTL which reuses faulty blocks to store approximate data for the lifetime optimization. Rebirth-FTL efficiently and effectively manages two spaces with approximation-aware address mapping, coordinated garbage collection and differential wear leveling. We also develop a scheme to pass approximate information from userland to kernel space in Linux. Evaluation results show that Rebirth-FTL can significantly increase the lifetime by up to 3. 46X.
{"title":"Rebirth-FTL: Lifetime optimization via Approximate Storage for NAND Flash","authors":"Lei Han, H. Amrouch, Z. Shao, J. Henkel","doi":"10.1109/NVMSA.2019.8863527","DOIUrl":"https://doi.org/10.1109/NVMSA.2019.8863527","url":null,"abstract":"The lifetime of NAND flash cells significantly degrades with feature-size reductions and multi-level cell technology. On the other hand, we have more and more approximate data such as images and video that can tolerate errors. In this paper, we propose Rebirth-FTL which reuses faulty blocks to store approximate data for the lifetime optimization. Rebirth-FTL efficiently and effectively manages two spaces with approximation-aware address mapping, coordinated garbage collection and differential wear leveling. We also develop a scheme to pass approximate information from userland to kernel space in Linux. Evaluation results show that Rebirth-FTL can significantly increase the lifetime by up to 3. 46X.","PeriodicalId":438544,"journal":{"name":"2019 IEEE Non-Volatile Memory Systems and Applications Symposium (NVMSA)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134249622","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-08-01DOI: 10.1109/nvmsa.2019.8863513
Yongpan Liu
General Co-Chairs: Xiaoning Qi, Alibaba Hong jiang, UT Arlington TPC Chair: Yongpan Liu, Tsinghua University Hyunok Oh, Hanyang University Local Chair: Cheng Zhuo, Zhejiang University Finance Co-Chairs: Guojie Luo, Peking University Qinmin Yang, Zhejiang University Publication Co-Chairs: Shibo He, Zhejiang University Fu Xiao, Nanjing University of Posts and Telecommunications Publicity Co-Chairs: Shimeng Yu, Georgia Institute of Technology Weisheng Zhao, Beihang University Web Chair: Zhi Ye, Zhejiang University
{"title":"NVMSA 2019 Committees","authors":"Yongpan Liu","doi":"10.1109/nvmsa.2019.8863513","DOIUrl":"https://doi.org/10.1109/nvmsa.2019.8863513","url":null,"abstract":"General Co-Chairs: Xiaoning Qi, Alibaba Hong jiang, UT Arlington TPC Chair: Yongpan Liu, Tsinghua University Hyunok Oh, Hanyang University Local Chair: Cheng Zhuo, Zhejiang University Finance Co-Chairs: Guojie Luo, Peking University Qinmin Yang, Zhejiang University Publication Co-Chairs: Shibo He, Zhejiang University Fu Xiao, Nanjing University of Posts and Telecommunications Publicity Co-Chairs: Shimeng Yu, Georgia Institute of Technology Weisheng Zhao, Beihang University Web Chair: Zhi Ye, Zhejiang University","PeriodicalId":438544,"journal":{"name":"2019 IEEE Non-Volatile Memory Systems and Applications Symposium (NVMSA)","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125004298","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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