Pub Date : 1988-09-12DOI: 10.1109/TEST.1988.207882
L. Sigal, C. Kime
Concurrent off-phase built-in self-test is described, which permits the operation of built-in self-test hardware designed for offline testing concurrently with normal system operations. It takes advantage of the logic dormancy characteristic of designs which use two-phase clocking. This method provides online detection for permanent faults and can be used in conjunction with a time-redundant concurrent test method to detect transient and intermittent as well as permanent faults. Also, the method provides guaranteed self-test for self-checking circuits. Concurrent off-phase BIST requires duplication of storage elements but otherwise makes use of BIST hardware used for noncurrent, offline testing. Also, there may be an associated time penalty which, for the given example of CMOS technology with a symmetric phase clock period of 50 ns, is estimated to be an 11.6% increase in the clock period.<>
{"title":"Concurrent off-phase built-in self-test of dormant logic","authors":"L. Sigal, C. Kime","doi":"10.1109/TEST.1988.207882","DOIUrl":"https://doi.org/10.1109/TEST.1988.207882","url":null,"abstract":"Concurrent off-phase built-in self-test is described, which permits the operation of built-in self-test hardware designed for offline testing concurrently with normal system operations. It takes advantage of the logic dormancy characteristic of designs which use two-phase clocking. This method provides online detection for permanent faults and can be used in conjunction with a time-redundant concurrent test method to detect transient and intermittent as well as permanent faults. Also, the method provides guaranteed self-test for self-checking circuits. Concurrent off-phase BIST requires duplication of storage elements but otherwise makes use of BIST hardware used for noncurrent, offline testing. Also, there may be an associated time penalty which, for the given example of CMOS technology with a symmetric phase clock period of 50 ns, is estimated to be an 11.6% increase in the clock period.<<ETX>>","PeriodicalId":439208,"journal":{"name":"International Test Conference 1988 Proceeding@m_New Frontiers in Testing","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115333697","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-09-12DOI: 10.1109/TEST.1988.207874
V. Iyengar, B. Rosen, I. Spillinger
For pt.I see ibid., p.857-66 (1988). A novel algebra is introduced for delay test generation. The algebra combines the nine natural logic values (00 , 01, 0X, 10, 11, 1X, X1, XX) with special attributes that record both heuristic choices and whatever information about waveforms is deducible algebraically (i.e. without numerical computations using actual gate delays). A test generator uses this algebra in an efficiently organized backtrack search. The test generator is linked to a delay fault simulator. Previous event-driven simulators have considered different types of events; one type of event is a change in faultless values from one test to another test, and the other type of event is a difference between faulty and faultless values. The presented simulator is driven by both types of events. Each generated test is simulated to determine the quality of detection.<>
{"title":"Delay test generation. II. Algebra and algorithms","authors":"V. Iyengar, B. Rosen, I. Spillinger","doi":"10.1109/TEST.1988.207874","DOIUrl":"https://doi.org/10.1109/TEST.1988.207874","url":null,"abstract":"For pt.I see ibid., p.857-66 (1988). A novel algebra is introduced for delay test generation. The algebra combines the nine natural logic values (00 , 01, 0X, 10, 11, 1X, X1, XX) with special attributes that record both heuristic choices and whatever information about waveforms is deducible algebraically (i.e. without numerical computations using actual gate delays). A test generator uses this algebra in an efficiently organized backtrack search. The test generator is linked to a delay fault simulator. Previous event-driven simulators have considered different types of events; one type of event is a change in faultless values from one test to another test, and the other type of event is a difference between faulty and faultless values. The presented simulator is driven by both types of events. Each generated test is simulated to determine the quality of detection.<<ETX>>","PeriodicalId":439208,"journal":{"name":"International Test Conference 1988 Proceeding@m_New Frontiers in Testing","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117218634","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-09-12DOI: 10.1109/TEST.1988.207892
S. Mourad, E. McCluskey
An approach to quantify the digital testing system (DTS) attributes is presented. The quantification will help in determining criteria according to which benchmark circuits are selected. Two main parameters that can be used in the comparison are the speed of operation and memory requirements. Attempts are made to relate each of these two parameters to different attributes of the DTS. Experiments were carried out using a commercial automatic test-pattern generator to generate test sets for some ISCAS circuits. The results of the experiments are presented.<>
{"title":"On benchmarking digital testing systems","authors":"S. Mourad, E. McCluskey","doi":"10.1109/TEST.1988.207892","DOIUrl":"https://doi.org/10.1109/TEST.1988.207892","url":null,"abstract":"An approach to quantify the digital testing system (DTS) attributes is presented. The quantification will help in determining criteria according to which benchmark circuits are selected. Two main parameters that can be used in the comparison are the speed of operation and memory requirements. Attempts are made to relate each of these two parameters to different attributes of the DTS. Experiments were carried out using a commercial automatic test-pattern generator to generate test sets for some ISCAS circuits. The results of the experiments are presented.<<ETX>>","PeriodicalId":439208,"journal":{"name":"International Test Conference 1988 Proceeding@m_New Frontiers in Testing","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124846739","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-09-12DOI: 10.1109/TEST.1988.207853
H. Cox, J. Rajski
A general technique is described to represent stuck-open faults in CMOS networks by transition (slow-to-rise and slow-to-fall) faults in equivalent gate-level circuits. Generally, CMOS complex gate require two gate-level representations: one for the n- part and another for the p-. The two representations may not be dual. After transformation, an algorithm based on the GEMINI logic system is used to determine the stuck-open fault coverage of a given test set. Multiple stuck-open faults are handled implicitly. Thus, results are not invalidated in the presence of untested or untestable faults. Robust test sets can be generated easily. The method can be used both for test generation and for fault diagnosis. Experimental results for multiple stuck-open fault coverage for ten benchmarking circuits are presented and compared. In particular, coverage figures for both robust and nonrobust test sets are presented.<>
{"title":"Stuck-open and transition fault testing in CMOS complex gates","authors":"H. Cox, J. Rajski","doi":"10.1109/TEST.1988.207853","DOIUrl":"https://doi.org/10.1109/TEST.1988.207853","url":null,"abstract":"A general technique is described to represent stuck-open faults in CMOS networks by transition (slow-to-rise and slow-to-fall) faults in equivalent gate-level circuits. Generally, CMOS complex gate require two gate-level representations: one for the n- part and another for the p-. The two representations may not be dual. After transformation, an algorithm based on the GEMINI logic system is used to determine the stuck-open fault coverage of a given test set. Multiple stuck-open faults are handled implicitly. Thus, results are not invalidated in the presence of untested or untestable faults. Robust test sets can be generated easily. The method can be used both for test generation and for fault diagnosis. Experimental results for multiple stuck-open fault coverage for ten benchmarking circuits are presented and compared. In particular, coverage figures for both robust and nonrobust test sets are presented.<<ETX>>","PeriodicalId":439208,"journal":{"name":"International Test Conference 1988 Proceeding@m_New Frontiers in Testing","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124942848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-09-12DOI: 10.1109/TEST.1988.207779
M. Karpovsky, P. Nagvajara
Board-level diagnostic techniques by signature analysis based on single-error-correcting Hamming codes over GF(2/sup M/) (where M is the number of outputs per chip) are presented. Two techniques are considered: the space-time compressor technique for the case when responses from N chips on the board are wired to the compressor; and the time compressor technique for the case when test responses from each chip are transferred to the compressor via system bus. Assuming a single-faulty-chip model, a faulty chip on the board under test is located by an analysis of the relationship between the distortions in the obtained signatures. Both techniques for board-level diagnosis require less hardware than the straightforward diagnostic techniques using a built-in signature analyzer for every chip or selective testing of each chip via the system bus, hence offering an efficient approach for a design of a built-in-self-test board for for manufacturing testing.<>
{"title":"Board-level diagnosis by signature analysis","authors":"M. Karpovsky, P. Nagvajara","doi":"10.1109/TEST.1988.207779","DOIUrl":"https://doi.org/10.1109/TEST.1988.207779","url":null,"abstract":"Board-level diagnostic techniques by signature analysis based on single-error-correcting Hamming codes over GF(2/sup M/) (where M is the number of outputs per chip) are presented. Two techniques are considered: the space-time compressor technique for the case when responses from N chips on the board are wired to the compressor; and the time compressor technique for the case when test responses from each chip are transferred to the compressor via system bus. Assuming a single-faulty-chip model, a faulty chip on the board under test is located by an analysis of the relationship between the distortions in the obtained signatures. Both techniques for board-level diagnosis require less hardware than the straightforward diagnostic techniques using a built-in signature analyzer for every chip or selective testing of each chip via the system bus, hence offering an efficient approach for a design of a built-in-self-test board for for manufacturing testing.<<ETX>>","PeriodicalId":439208,"journal":{"name":"International Test Conference 1988 Proceeding@m_New Frontiers in Testing","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115204975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-09-12DOI: 10.1109/TEST.1988.207889
J. Hallenbeck, N. Kanopoulos, N. Vasanthavada, J. W. Watterson
A methodology and the supporting CAD (computer-aided design) tools are discussed for designing a digital system so that it can meet predefined testability requirements. The set of tools is called the Test Engineer's Assistant (TEA). The TEA system creates an environment in which the designer can perform performance assessment, functional design, and design for testability (DFT). TEA is developed to support automated DFT at the board and subsystem levels, to aid in an appropriate choice of BIT (built-in test) techniques at the board level that is supported at the subsystem and system levels, to indicate where to augment system function with predefined BIT modules to increase testability, and to assess the hardware costs of implementing DFT and BIT.<>
{"title":"CAD tools for supporting system design for testability","authors":"J. Hallenbeck, N. Kanopoulos, N. Vasanthavada, J. W. Watterson","doi":"10.1109/TEST.1988.207889","DOIUrl":"https://doi.org/10.1109/TEST.1988.207889","url":null,"abstract":"A methodology and the supporting CAD (computer-aided design) tools are discussed for designing a digital system so that it can meet predefined testability requirements. The set of tools is called the Test Engineer's Assistant (TEA). The TEA system creates an environment in which the designer can perform performance assessment, functional design, and design for testability (DFT). TEA is developed to support automated DFT at the board and subsystem levels, to aid in an appropriate choice of BIT (built-in test) techniques at the board level that is supported at the subsystem and system levels, to indicate where to augment system function with predefined BIT modules to increase testability, and to assess the hardware costs of implementing DFT and BIT.<<ETX>>","PeriodicalId":439208,"journal":{"name":"International Test Conference 1988 Proceeding@m_New Frontiers in Testing","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122528237","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-09-12DOI: 10.1109/TEST.1988.207819
S. Gupta, D. Pradhan
A coding theory framework is developed for analysis and synthesis of compression techniques in the built-in self test (BIST) environment. Using this framework, exact expressions are derived for the linear feedback shift register aliasing probability. These are shown to be more accurate than earlier ones. Also shown is that there exist compression techniques for which the aliasing probability can be reduced to zero asymptotically. An error model is presented that incorporates the effects of faults on output response. It is shown that the coding theory framework correlates well with this proposed error model. A signature analysis technique is presented, which achieves smaller aliasing probability than other recently proposed schemes.<>
{"title":"A new framework for designing and analyzing BIST techniques: computation of exact aliasing probability","authors":"S. Gupta, D. Pradhan","doi":"10.1109/TEST.1988.207819","DOIUrl":"https://doi.org/10.1109/TEST.1988.207819","url":null,"abstract":"A coding theory framework is developed for analysis and synthesis of compression techniques in the built-in self test (BIST) environment. Using this framework, exact expressions are derived for the linear feedback shift register aliasing probability. These are shown to be more accurate than earlier ones. Also shown is that there exist compression techniques for which the aliasing probability can be reduced to zero asymptotically. An error model is presented that incorporates the effects of faults on output response. It is shown that the coding theory framework correlates well with this proposed error model. A signature analysis technique is presented, which achieves smaller aliasing probability than other recently proposed schemes.<<ETX>>","PeriodicalId":439208,"journal":{"name":"International Test Conference 1988 Proceeding@m_New Frontiers in Testing","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128668690","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-09-12DOI: 10.1109/TEST.1988.207780
S. Su, Hede Ma
The concepts of grey, white, and black systems are formally introduced and developed into logic testing area, i.e. the area of error detection and fault isolation, to find a direction to establish more efficient test schemes for testing digital systems at a reasonable cost. A probabilistic isolation strategy realized by a heuristic and decision-making algorithm is presented to isolate faults in grey systems efficiently in terms of computation space and time.<>
{"title":"Fault isolation in grey systems","authors":"S. Su, Hede Ma","doi":"10.1109/TEST.1988.207780","DOIUrl":"https://doi.org/10.1109/TEST.1988.207780","url":null,"abstract":"The concepts of grey, white, and black systems are formally introduced and developed into logic testing area, i.e. the area of error detection and fault isolation, to find a direction to establish more efficient test schemes for testing digital systems at a reasonable cost. A probabilistic isolation strategy realized by a heuristic and decision-making algorithm is presented to isolate faults in grey systems efficiently in terms of computation space and time.<<ETX>>","PeriodicalId":439208,"journal":{"name":"International Test Conference 1988 Proceeding@m_New Frontiers in Testing","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128918899","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-09-12DOI: 10.1109/TEST.1988.207879
H. Niijima, Y. Tokunaga, Shouichi Koshizuka, K. Yakuwa, P. Fazekas, Mathias Sturm, H. Feuerbaum
An integrated EB (electron-beam) testing system is constructed for precise failure analysis and reduction of total testing time, coupling a VLSI tester and an EB tester. Unique features of the system are briefly described, together with its system configuration and functions. The close connection of LSI testing and EB testing environments is further continued. It is planned to improve the integrated system to enable a simultaneous display of EB testing data in the LSI testing environment, with which it becomes possible to superimpose the EB pin data into the timing chart of normal pin data in the LSI testing. This type of connection of two environments is quite powerful and will be used in a standard testing method.<>
{"title":"Electron beam tester integrated into a VLSI tester","authors":"H. Niijima, Y. Tokunaga, Shouichi Koshizuka, K. Yakuwa, P. Fazekas, Mathias Sturm, H. Feuerbaum","doi":"10.1109/TEST.1988.207879","DOIUrl":"https://doi.org/10.1109/TEST.1988.207879","url":null,"abstract":"An integrated EB (electron-beam) testing system is constructed for precise failure analysis and reduction of total testing time, coupling a VLSI tester and an EB tester. Unique features of the system are briefly described, together with its system configuration and functions. The close connection of LSI testing and EB testing environments is further continued. It is planned to improve the integrated system to enable a simultaneous display of EB testing data in the LSI testing environment, with which it becomes possible to superimpose the EB pin data into the timing chart of normal pin data in the LSI testing. This type of connection of two environments is quite powerful and will be used in a standard testing method.<<ETX>>","PeriodicalId":439208,"journal":{"name":"International Test Conference 1988 Proceeding@m_New Frontiers in Testing","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130557351","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-09-12DOI: 10.1109/TEST.1988.207880
K. Wilken, John Paul Shen
Concurrent detection of processor control errors using signatured programs is discussed. The approach, called continuous signature monitoring (CSM), makes significant advances beyond the existing signature-monitoring techniques. For typical programs, CSM decreased average error-detection latency by as much as eight times, down to 1.2 to 1.6 program memory cycles. Memory overhead for storing signatures reaches a theoretical minimum, lowered as much as four times, dozen to 3-7%. The CSM monitor is less complex by more than half, and processor-performance loss is reduced as much as 10 times down to 0.6-1.5%. CSM increases coverage of control-flow errors and detects certain types of errors not detected by the existing techniques, including a stuck program counter.<>
{"title":"Continuous signature monitoring: efficient concurrent-detection of processor control errors","authors":"K. Wilken, John Paul Shen","doi":"10.1109/TEST.1988.207880","DOIUrl":"https://doi.org/10.1109/TEST.1988.207880","url":null,"abstract":"Concurrent detection of processor control errors using signatured programs is discussed. The approach, called continuous signature monitoring (CSM), makes significant advances beyond the existing signature-monitoring techniques. For typical programs, CSM decreased average error-detection latency by as much as eight times, down to 1.2 to 1.6 program memory cycles. Memory overhead for storing signatures reaches a theoretical minimum, lowered as much as four times, dozen to 3-7%. The CSM monitor is less complex by more than half, and processor-performance loss is reduced as much as 10 times down to 0.6-1.5%. CSM increases coverage of control-flow errors and detects certain types of errors not detected by the existing techniques, including a stuck program counter.<<ETX>>","PeriodicalId":439208,"journal":{"name":"International Test Conference 1988 Proceeding@m_New Frontiers in Testing","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121531815","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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