Pub Date : 2003-05-12DOI: 10.1109/CAMP.2003.1598153
M. U. de Haag, J. Sayre, J. Campbell, S. Young
This paper discusses the architecture and flight test results of a digital elevation model (DEM) integrity monitor for a synthetic vision system (SVS). An SVS provides pilots with either a heads down display (HDD) or a heads up display (HUD) containing aircraft state, guidance and navigation information, and a virtual depiction of the terrain as viewed "from the cockpit". Introduction of SVS technology in the aircraft flight deck has the potential to improve flight safety by increasing the situational awareness (SA) in low to near zero-visibility conditions to a level of awareness similar to daytime clear weather flying. This SA improvement does not only enable low-visibility operations, but may also reduce the likelihood of controlled flight into terrain (CFIT)
{"title":"Monitoring terrain database integrity through aircraft sensor consistency checking: architecture and flight test results","authors":"M. U. de Haag, J. Sayre, J. Campbell, S. Young","doi":"10.1109/CAMP.2003.1598153","DOIUrl":"https://doi.org/10.1109/CAMP.2003.1598153","url":null,"abstract":"This paper discusses the architecture and flight test results of a digital elevation model (DEM) integrity monitor for a synthetic vision system (SVS). An SVS provides pilots with either a heads down display (HDD) or a heads up display (HUD) containing aircraft state, guidance and navigation information, and a virtual depiction of the terrain as viewed \"from the cockpit\". Introduction of SVS technology in the aircraft flight deck has the potential to improve flight safety by increasing the situational awareness (SA) in low to near zero-visibility conditions to a level of awareness similar to daytime clear weather flying. This SA improvement does not only enable low-visibility operations, but may also reduce the likelihood of controlled flight into terrain (CFIT)","PeriodicalId":443821,"journal":{"name":"2003 IEEE International Workshop on Computer Architectures for Machine Perception","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-05-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122804674","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-05-12DOI: 10.1109/CAMP.2003.1598157
M. Herbordt, Jade Cravyt, Calvin Lint
Although arrays of SIMD PEs can be built with very high operating frequencies, problems exist in keeping the array busy. The inherent mismatch between host and array makes it difficult to maintain high array utilization: either the rate of instruction issue is very low or PE data locality is compromised, having the same effect. Our solution is based on an array control unit (ACU) design that expands macroinstructions in two stages, first by data tile and then into microinstructions. The expansion itself solves the issue problem; decoupling the expansion modalities maintains data locality. Several issues involving host/ACU interaction need to be resolved to effect this solution. We present experimental results showing that our approach delivers substantial improvement in memory hierarchy performance: a cache of only one fourth the size is sufficient to achieve the same performance as previous approaches
{"title":"Memory considerations for high performance SIMD systems with on-chip control","authors":"M. Herbordt, Jade Cravyt, Calvin Lint","doi":"10.1109/CAMP.2003.1598157","DOIUrl":"https://doi.org/10.1109/CAMP.2003.1598157","url":null,"abstract":"Although arrays of SIMD PEs can be built with very high operating frequencies, problems exist in keeping the array busy. The inherent mismatch between host and array makes it difficult to maintain high array utilization: either the rate of instruction issue is very low or PE data locality is compromised, having the same effect. Our solution is based on an array control unit (ACU) design that expands macroinstructions in two stages, first by data tile and then into microinstructions. The expansion itself solves the issue problem; decoupling the expansion modalities maintains data locality. Several issues involving host/ACU interaction need to be resolved to effect this solution. We present experimental results showing that our approach delivers substantial improvement in memory hierarchy performance: a cache of only one fourth the size is sufficient to achieve the same performance as previous approaches","PeriodicalId":443821,"journal":{"name":"2003 IEEE International Workshop on Computer Architectures for Machine Perception","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-05-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129090104","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-05-12DOI: 10.1109/CAMP.2003.1598158
K. Sitaraman, A. Ejnioui, N. Ranganathan
The problem of tree pattern matching for object recognition in images is computationally intensive in nature. In two-dimensional images, the objects can be represented through multiscale decomposition as tree structures. The pattern tree representing an object can be matched with a subject tree representing an image in order to detect the objects within the image. Several sequential, parallel and hardware algorithms exist in the literature for tree pattern matching. In this paper, we describe a new parallel algorithm and its realization as a VLSI chip for tree pattern matching. The hardware algorithm is based on a linear array of processing elements (PEs) where the pattern matching is done in a pipelined fashion relying on nearest-neighbor communication between the PE's and the subject and pattern trees of arbitrary length can be processed using a fixed size PE array. The algorithm has an improved execution time of O(lceilm/arceiln) required to perform the matching where m, a and n are the sizes of the pattern tree, processor array, subject tree respectively. A prototype CMOS VLSI chip implementing the proposed algorithm has been designed and verified. It is shown that the hardware algorithm proposed in this work represent a sign improvement in terms of computational complexity, data flow, and architecture over the ones previously proposed for this problem
{"title":"A parallel algorithm and architecture for object recognition in images","authors":"K. Sitaraman, A. Ejnioui, N. Ranganathan","doi":"10.1109/CAMP.2003.1598158","DOIUrl":"https://doi.org/10.1109/CAMP.2003.1598158","url":null,"abstract":"The problem of tree pattern matching for object recognition in images is computationally intensive in nature. In two-dimensional images, the objects can be represented through multiscale decomposition as tree structures. The pattern tree representing an object can be matched with a subject tree representing an image in order to detect the objects within the image. Several sequential, parallel and hardware algorithms exist in the literature for tree pattern matching. In this paper, we describe a new parallel algorithm and its realization as a VLSI chip for tree pattern matching. The hardware algorithm is based on a linear array of processing elements (PEs) where the pattern matching is done in a pipelined fashion relying on nearest-neighbor communication between the PE's and the subject and pattern trees of arbitrary length can be processed using a fixed size PE array. The algorithm has an improved execution time of O(lceilm/arceiln) required to perform the matching where m, a and n are the sizes of the pattern tree, processor array, subject tree respectively. A prototype CMOS VLSI chip implementing the proposed algorithm has been designed and verified. It is shown that the hardware algorithm proposed in this work represent a sign improvement in terms of computational complexity, data flow, and architecture over the ones previously proposed for this problem","PeriodicalId":443821,"journal":{"name":"2003 IEEE International Workshop on Computer Architectures for Machine Perception","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-05-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114637575","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-05-12DOI: 10.1109/CAMP.2003.1598176
M. Perez, F. Cabestaing
Many algorithms for computing correlation based stereo correspondence have been proposed. Some of them can be implemented on specialized architectures, in order to obtain results in real time. In this communication, we propose an experimental comparison of the amount of hardware resources required for implementing these algorithms. An efficient architecture is presented, the STREAM, (acronym for systeme temps-reel d'extraction et d'analyse du mouvement, i.e. real-time motion extraction and analysis system) which is a processor dedicated to image sequence analysis
许多基于相关的立体对应计算算法已经被提出。其中一些可以在专门的体系结构上实现，以便实时获得结果。在本通信中，我们提出了实现这些算法所需的硬件资源量的实验比较。提出了一种高效的体系结构STREAM (system temes -reel d'extraction et d'analyse du movement的缩写，即实时运动提取和分析系统)，它是一种专门用于图像序列分析的处理器
{"title":"A comparison of hardware resources required by real-time stereo dense algorithms","authors":"M. Perez, F. Cabestaing","doi":"10.1109/CAMP.2003.1598176","DOIUrl":"https://doi.org/10.1109/CAMP.2003.1598176","url":null,"abstract":"Many algorithms for computing correlation based stereo correspondence have been proposed. Some of them can be implemented on specialized architectures, in order to obtain results in real time. In this communication, we propose an experimental comparison of the amount of hardware resources required for implementing these algorithms. An efficient architecture is presented, the STREAM, (acronym for systeme temps-reel d'extraction et d'analyse du mouvement, i.e. real-time motion extraction and analysis system) which is a processor dedicated to image sequence analysis","PeriodicalId":443821,"journal":{"name":"2003 IEEE International Workshop on Computer Architectures for Machine Perception","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-05-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114735949","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-05-12DOI: 10.1109/CAMP.2003.1598175
J. Denoulet, A. Mérigot
This paper presents the current evolution of the associative mesh project. It aims at the design of a reconfigurable, asynchronous and massively parallel SIMD architecture, targeted towards image analysis implementation. Its basic principle relies on the use of global operations (associations) that, given any interpixel connection graph, can compute global operations over connected sets of these graphs. One of our current objectives is the implementation of an associative mesh with a SoC-type circuit. In this paper, we examine which architectural modifications would this approach imply. We also consider the benefits brought by this technique and the repercussions on the design's performances
{"title":"System on chip evolution of a SIMD architecture for image processing","authors":"J. Denoulet, A. Mérigot","doi":"10.1109/CAMP.2003.1598175","DOIUrl":"https://doi.org/10.1109/CAMP.2003.1598175","url":null,"abstract":"This paper presents the current evolution of the associative mesh project. It aims at the design of a reconfigurable, asynchronous and massively parallel SIMD architecture, targeted towards image analysis implementation. Its basic principle relies on the use of global operations (associations) that, given any interpixel connection graph, can compute global operations over connected sets of these graphs. One of our current objectives is the implementation of an associative mesh with a SoC-type circuit. In this paper, we examine which architectural modifications would this approach imply. We also consider the benefits brought by this technique and the repercussions on the design's performances","PeriodicalId":443821,"journal":{"name":"2003 IEEE International Workshop on Computer Architectures for Machine Perception","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-05-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125387935","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-05-12DOI: 10.1109/CAMP.2003.1598159
V. S. Murty, P. C. Reghu Raj, S. Raman
In natural language processing applications, string matching is the main time-consuming operation due to the large size of lexicon. Data dependence is minimal in string matching operations, and hence it is ideal for parallelization. A dedicated hardware for string matching that uses memory interleaving and parallel processing techniques can relieve the host CPU from this burden, thereby making the system suitable for real-time applications. This paper reports the FPGA design of such a system with m parallel matching units. The time complexity of the proposed algorithm is O (log2 n), where n is the total number of lexical entries. This has been achieved by a proper selection of the value of m. A special memory organization technique, which reduces the storage space by nearly 70%, has been adopted for storing lexical entries. The techniques used for matching and storage of lexical entries make the system language independent
{"title":"Design of a language-independent parallel string matching unit for NLP","authors":"V. S. Murty, P. C. Reghu Raj, S. Raman","doi":"10.1109/CAMP.2003.1598159","DOIUrl":"https://doi.org/10.1109/CAMP.2003.1598159","url":null,"abstract":"In natural language processing applications, string matching is the main time-consuming operation due to the large size of lexicon. Data dependence is minimal in string matching operations, and hence it is ideal for parallelization. A dedicated hardware for string matching that uses memory interleaving and parallel processing techniques can relieve the host CPU from this burden, thereby making the system suitable for real-time applications. This paper reports the FPGA design of such a system with m parallel matching units. The time complexity of the proposed algorithm is O (log2 n), where n is the total number of lexical entries. This has been achieved by a proper selection of the value of m. A special memory organization technique, which reduces the storage space by nearly 70%, has been adopted for storing lexical entries. The techniques used for matching and storage of lexical entries make the system language independent","PeriodicalId":443821,"journal":{"name":"2003 IEEE International Workshop on Computer Architectures for Machine Perception","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-05-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124334386","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-05-12DOI: 10.1109/CAMP.2003.1598167
H. Le, G. Seetharaman, B. Zavidovique
We present a technique to estimate the optical flow in an image sequence, based on a piecewise affine model. In this piecewise approach, the area of interest in each image frame is divided into a set of small triangular patches. These triangular meshes are established over a set of feature points, which are extracted from the images and tracked from one frame to another. The velocity field within each triangular patch is parameterized by an affine transform. A multiscale coarse-to-fine approach is employed to increase the robustness of the method as well as the accuracy of the optical flow resulted from piecewise affine approximations. Finally, an adaptive filter is used to refine the estimated flow field. The filter is designed in such a way that not only can it reduce noises caused by errors of the process described above, but it can also avoid smoothing the discontinuities in the motion field. The method has been implemented and some experimental results are presented in this paper. The method takes advantage of widely used MPEG-4 encoding hardware/software tools
{"title":"A multiscale technique for optical flow computation using piecewise affine approximation","authors":"H. Le, G. Seetharaman, B. Zavidovique","doi":"10.1109/CAMP.2003.1598167","DOIUrl":"https://doi.org/10.1109/CAMP.2003.1598167","url":null,"abstract":"We present a technique to estimate the optical flow in an image sequence, based on a piecewise affine model. In this piecewise approach, the area of interest in each image frame is divided into a set of small triangular patches. These triangular meshes are established over a set of feature points, which are extracted from the images and tracked from one frame to another. The velocity field within each triangular patch is parameterized by an affine transform. A multiscale coarse-to-fine approach is employed to increase the robustness of the method as well as the accuracy of the optical flow resulted from piecewise affine approximations. Finally, an adaptive filter is used to refine the estimated flow field. The filter is designed in such a way that not only can it reduce noises caused by errors of the process described above, but it can also avoid smoothing the discontinuities in the motion field. The method has been implemented and some experimental results are presented in this paper. The method takes advantage of widely used MPEG-4 encoding hardware/software tools","PeriodicalId":443821,"journal":{"name":"2003 IEEE International Workshop on Computer Architectures for Machine Perception","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-05-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121753187","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-05-12DOI: 10.1109/CAMP.2003.1598160
S. Belkacemi, K. Benkrid, D. Crookes, A. Benkrid
Matrix multiplication is a core operation in digital signal processing operations with a variety of applications such as image processing, computer graphics, sonar processing and robotics. This paper presents the design and implementation of a high performance, fully parallel matrix multiplication core. The core is parameterised and scalable in terms of the matrices' dimensions (row and column number) and the input data word length. Fully floorplanned FPGA configurations are generated automatically, from high-level descriptions of the matrix multiplication operation, in the form of EDIF netlists in less than 1 sec. These are specifically optimised for Xilinx Virtex FPGA chips. By exploiting the abundance of logic resources in Xilinx Virtex FPGAs (look-up tables, fast carry logic, shift registers, flip flops etc.), a fully parallel implementation of the matrix multiplier core has been achieved; with a full matrix result being generated every clock cycle. A 3times3 matrix multiplier instance consumes 2,448 Virtex slices and can run at 175 MHz on an XCV1000E-6 Virtex-E chip, thus performing over 4.7 billion MAC/sec. This leads to 175 million full 3times3 matrix result per second
{"title":"Design and implementation of a high performance matrix multiplier core for Xilinx Virtex FPGAs","authors":"S. Belkacemi, K. Benkrid, D. Crookes, A. Benkrid","doi":"10.1109/CAMP.2003.1598160","DOIUrl":"https://doi.org/10.1109/CAMP.2003.1598160","url":null,"abstract":"Matrix multiplication is a core operation in digital signal processing operations with a variety of applications such as image processing, computer graphics, sonar processing and robotics. This paper presents the design and implementation of a high performance, fully parallel matrix multiplication core. The core is parameterised and scalable in terms of the matrices' dimensions (row and column number) and the input data word length. Fully floorplanned FPGA configurations are generated automatically, from high-level descriptions of the matrix multiplication operation, in the form of EDIF netlists in less than 1 sec. These are specifically optimised for Xilinx Virtex FPGA chips. By exploiting the abundance of logic resources in Xilinx Virtex FPGAs (look-up tables, fast carry logic, shift registers, flip flops etc.), a fully parallel implementation of the matrix multiplier core has been achieved; with a full matrix result being generated every clock cycle. A 3times3 matrix multiplier instance consumes 2,448 Virtex slices and can run at 175 MHz on an XCV1000E-6 Virtex-E chip, thus performing over 4.7 billion MAC/sec. This leads to 175 million full 3times3 matrix result per second","PeriodicalId":443821,"journal":{"name":"2003 IEEE International Workshop on Computer Architectures for Machine Perception","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-05-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124771479","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-05-12DOI: 10.1109/CAMP.2003.1598164
R. Coudarcher, F. Duculty, J. Sérot, F. Jurie, J. Derutin, M. Dhome
This paper casts a light on the parallelisation, using algorithmic skeletons, of a complete and realistic image processing application in which we have pointed out requirement for skeleton nesting. The image processing application we have chosen is a 3D face tracking algorithm from appearance
{"title":"Parallelisation of a face tracking algorithm with the SKiPPER-II parallel programming environment","authors":"R. Coudarcher, F. Duculty, J. Sérot, F. Jurie, J. Derutin, M. Dhome","doi":"10.1109/CAMP.2003.1598164","DOIUrl":"https://doi.org/10.1109/CAMP.2003.1598164","url":null,"abstract":"This paper casts a light on the parallelisation, using algorithmic skeletons, of a complete and realistic image processing application in which we have pointed out requirement for skeleton nesting. The image processing application we have chosen is a 3D face tracking algorithm from appearance","PeriodicalId":443821,"journal":{"name":"2003 IEEE International Workshop on Computer Architectures for Machine Perception","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-05-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128207530","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-05-12DOI: 10.1109/CAMP.2003.1598169
L. Di Stefano, M. Marchionni, S. Mattoccia
This paper presents a stereo algorithm that enables real time dense disparity measurements on standard personal computers. Unlike many other dense stereo algorithms, which are based on two matching phases, the proposed algorithm relies on a single matching phase and allows for rejecting unreliable matches by exploiting violations of the uniqueness constraint and analysing the behaviour of the correlation scores. The overall algorithm has been carefully optimised using very efficient calculation schemes and deploying massively the SIMD parallel processing capabilities available nowadays in state-of-the-art general purpose microprocessors. The paper describes the algorithm and the optimisation strategies, and provides experimental results obtained on stereo pairs with ground-truth as well as execution times measurements
{"title":"Real-time dense stereo on a personal computer","authors":"L. Di Stefano, M. Marchionni, S. Mattoccia","doi":"10.1109/CAMP.2003.1598169","DOIUrl":"https://doi.org/10.1109/CAMP.2003.1598169","url":null,"abstract":"This paper presents a stereo algorithm that enables real time dense disparity measurements on standard personal computers. Unlike many other dense stereo algorithms, which are based on two matching phases, the proposed algorithm relies on a single matching phase and allows for rejecting unreliable matches by exploiting violations of the uniqueness constraint and analysing the behaviour of the correlation scores. The overall algorithm has been carefully optimised using very efficient calculation schemes and deploying massively the SIMD parallel processing capabilities available nowadays in state-of-the-art general purpose microprocessors. The paper describes the algorithm and the optimisation strategies, and provides experimental results obtained on stereo pairs with ground-truth as well as execution times measurements","PeriodicalId":443821,"journal":{"name":"2003 IEEE International Workshop on Computer Architectures for Machine Perception","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-05-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130272523","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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