Pub Date : 1900-01-01DOI: 10.1109/DCIS55711.2022.9970112
F. García-Redondo, Ali BanaGozar, K. Vadivel, H. Corporaal, Shidhartha Das
Always-ON accelerators running TinyML applications are strongly limited by the memory and computation resources available in edge devices. Compute-In-Memory (CIM) architectures based on non-volatile memories (NVM) promise to bring the required compute and memory demands of Deep Neural Networks (DNN) to the edge while consuming extremely low power. However, their system-level design is constrained by the device and periphery noise which strongly impacts and compromises the accuracy of the DNN workload. In this paper SACA, a framework for simulating host & CIM accelerator systems, is presented. The simulator quantifies the system reliability by taking into account device-level non-idealities. The accuracy of two representative TinyML workloads is analyzed based on the crossbar characteristics -NVM technology, crossbar size, periphery characteristics. To demonstrate the capabilities of SACA, extensive experiments are carried out. We have characterized a convolutional network tackling CIFAR10 image classification and a fully connected network performing Human Activity Recognition. The results lead to optimal energy/performance/accuracy profiles, while the overall analysis highlights the dramatic effects of IR-drop on larger crossbars, degrading the system's accuracy and compromising its reliability.
{"title":"SACA: System-level Analog CIM Accelerators Simulation Framework: Accurate Simulation of Non-Ideal Components","authors":"F. García-Redondo, Ali BanaGozar, K. Vadivel, H. Corporaal, Shidhartha Das","doi":"10.1109/DCIS55711.2022.9970112","DOIUrl":"https://doi.org/10.1109/DCIS55711.2022.9970112","url":null,"abstract":"Always-ON accelerators running TinyML applications are strongly limited by the memory and computation resources available in edge devices. Compute-In-Memory (CIM) architectures based on non-volatile memories (NVM) promise to bring the required compute and memory demands of Deep Neural Networks (DNN) to the edge while consuming extremely low power. However, their system-level design is constrained by the device and periphery noise which strongly impacts and compromises the accuracy of the DNN workload. In this paper SACA, a framework for simulating host & CIM accelerator systems, is presented. The simulator quantifies the system reliability by taking into account device-level non-idealities. The accuracy of two representative TinyML workloads is analyzed based on the crossbar characteristics -NVM technology, crossbar size, periphery characteristics. To demonstrate the capabilities of SACA, extensive experiments are carried out. We have characterized a convolutional network tackling CIFAR10 image classification and a fully connected network performing Human Activity Recognition. The results lead to optimal energy/performance/accuracy profiles, while the overall analysis highlights the dramatic effects of IR-drop on larger crossbars, degrading the system's accuracy and compromising its reliability.","PeriodicalId":443881,"journal":{"name":"Conference on Design of Circuits and Integrated Systems","volume":"176 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120960673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/DCIS55711.2022.9970090
K. Vadivel, F. García-Redondo, Ali BanaGozar, H. Corporaal, Shidhartha Das
Analog Computation-In-Memory (CIM) architectures promise to bring to the edge the required compute and memory demands of TinyML applications while consuming extremely low power. However, the analog CIM paradigm is suitable for accelerating vector-matrix multiplication patterns alone, and the accuracy of the computation itself is stirred by the CIM device and its driving circuit non-idealities. Despite these practical constraints, CIM accelerators are often developed and evaluated in isolation without considering real-world system-level conditions, such as sharing system resources (host CPU, main-memory, and interconnect) for inter-layer pre/post-processing, data alignment, and data movement. These make it challenging to evaluate the energy, performance, area, and accuracy tradeoff for practical, end-to-end applications. To address this, we propose a first SoC level, gem5-based, open-source simulation framework for CIM accelerator design. It supports the modeling of hierarchical CIM accelerators for different device technologies and digital/mixed-signal driving circuit configurations, along with their non-ideal behaviour. The associated full-stack software provides APIs for (re-)configuring the CIM accelerator for offloading computations at the system level. To demonstrate some capabilities of the SACA, we carried out design space exploration on two representative TinyML tasks - Human Activity Recognition and CIFAR10 image classification. The results lead to optimal accelerator profiles and indicate a tradeoff between the energy, area, performance, and accuracy for different configurations.
{"title":"SACA: System-level Analog CIM Accelerators Simulation Framework: Architecture and Cycle-accurate System-to-device Simulator","authors":"K. Vadivel, F. García-Redondo, Ali BanaGozar, H. Corporaal, Shidhartha Das","doi":"10.1109/DCIS55711.2022.9970090","DOIUrl":"https://doi.org/10.1109/DCIS55711.2022.9970090","url":null,"abstract":"Analog Computation-In-Memory (CIM) architectures promise to bring to the edge the required compute and memory demands of TinyML applications while consuming extremely low power. However, the analog CIM paradigm is suitable for accelerating vector-matrix multiplication patterns alone, and the accuracy of the computation itself is stirred by the CIM device and its driving circuit non-idealities. Despite these practical constraints, CIM accelerators are often developed and evaluated in isolation without considering real-world system-level conditions, such as sharing system resources (host CPU, main-memory, and interconnect) for inter-layer pre/post-processing, data alignment, and data movement. These make it challenging to evaluate the energy, performance, area, and accuracy tradeoff for practical, end-to-end applications. To address this, we propose a first SoC level, gem5-based, open-source simulation framework for CIM accelerator design. It supports the modeling of hierarchical CIM accelerators for different device technologies and digital/mixed-signal driving circuit configurations, along with their non-ideal behaviour. The associated full-stack software provides APIs for (re-)configuring the CIM accelerator for offloading computations at the system level. To demonstrate some capabilities of the SACA, we carried out design space exploration on two representative TinyML tasks - Human Activity Recognition and CIFAR10 image classification. The results lead to optimal accelerator profiles and indicate a tradeoff between the energy, area, performance, and accuracy for different configurations.","PeriodicalId":443881,"journal":{"name":"Conference on Design of Circuits and Integrated Systems","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126672444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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