Pub Date : 1992-09-01DOI: 10.1142/S0129626492000313
R. Sarnath
The Different Than Majority Labeling (DTML) problem has a simple polynomial time algorithm, but is not known to be in NC. In this paper, we show that the DTML problem is extremely unlikely to have an NC1 algorithm.
{"title":"DTML IS LOGSPACE HARD UNDER NC1 REDUCTIONS","authors":"R. Sarnath","doi":"10.1142/S0129626492000313","DOIUrl":"https://doi.org/10.1142/S0129626492000313","url":null,"abstract":"The Different Than Majority Labeling (DTML) problem has a simple polynomial time algorithm, but is not known to be in NC. In this paper, we show that the DTML problem is extremely unlikely to have an NC1 algorithm.","PeriodicalId":44742,"journal":{"name":"Parallel Processing Letters","volume":"65 1","pages":"189-193"},"PeriodicalIF":0.4,"publicationDate":"1992-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87161807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-09-01DOI: 10.1142/S0129626491000161
A. Arora, S. Dolev, M. Gouda
A system of simultaneously triggered clocks is designed to be stabilizing: if the clock values ever differ, the system is guaranteed to converge to a state where all clock values are identical, and are subsequently maintained to be identical. For an N-clock system, the design uses N registers of 2logN bits each and guarantees convergence to identical values within N2 "triggers".
{"title":"Maintaining Digital Clocks in Step","authors":"A. Arora, S. Dolev, M. Gouda","doi":"10.1142/S0129626491000161","DOIUrl":"https://doi.org/10.1142/S0129626491000161","url":null,"abstract":"A system of simultaneously triggered clocks is designed to be stabilizing: if the clock values ever differ, the system is guaranteed to converge to a state where all clock values are identical, and are subsequently maintained to be identical. For an N-clock system, the design uses N registers of 2logN bits each and guarantees convergence to identical values within N2 \"triggers\".","PeriodicalId":44742,"journal":{"name":"Parallel Processing Letters","volume":"21 1","pages":"71-79"},"PeriodicalIF":0.4,"publicationDate":"1991-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90217005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}