Pub Date : 2024-04-22DOI: 10.37394/232017.2024.15.6
V. M. B., Nikitha M.
Ternary logic has received substantial attention over the past decade due to its compensations of smaller chip area and interconnection compared to outmoded binary logic. Carbon Nanotube Field Effect Transistor (CNTFET) technology is widely used for ternary logic implementation due to its versatile threshold voltages. The increased power consumption in current designs utilizing CNFETs, as linked to binary logic, is attributed to elevated static power dissipation within the design. This work recommends alternative triple encoder designs with a focus on reducing the consumption of power. The model uses an additional Vdd/2 supply voltage to decrease static power dissipation and encoder power delay. Cadence virtuoso-based circuit simulations are implemented for the proposed encoder design.
{"title":"Design of Low Power Ternary Logic Encoder and ADC using CNTFET","authors":"V. M. B., Nikitha M.","doi":"10.37394/232017.2024.15.6","DOIUrl":"https://doi.org/10.37394/232017.2024.15.6","url":null,"abstract":"Ternary logic has received substantial attention over the past decade due to its compensations of smaller chip area and interconnection compared to outmoded binary logic. Carbon Nanotube Field Effect Transistor (CNTFET) technology is widely used for ternary logic implementation due to its versatile threshold voltages. The increased power consumption in current designs utilizing CNFETs, as linked to binary logic, is attributed to elevated static power dissipation within the design. This work recommends alternative triple encoder designs with a focus on reducing the consumption of power. The model uses an additional Vdd/2 supply voltage to decrease static power dissipation and encoder power delay. Cadence virtuoso-based circuit simulations are implemented for the proposed encoder design.","PeriodicalId":489755,"journal":{"name":"WSEAS Transactions on Electronics","volume":"23 25","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140674726","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-04-08DOI: 10.37394/232017.2024.15.4
Anisa Moza Sabilla, Mahir Pradana
The COVID-19 pandemic has changed the nature of education, leading to a move away from in-person instruction toward online training. This raises the question of how beneficial, given the COVID-19 epidemic, online schooling is. The effectiveness of e-learning and student efforts during the COVID-19 epidemic will be used in this study to measure the Telkom University S1 Business Administration department's level of learning satisfaction. This type of research is descriptive quantitative since it makes use of a questionnaire. A private university's hundred students made up the study's population. To evaluate data, use the SmartPLS program. The results of the data analysis show that learning satisfaction is significantly impacted by both student actions and the effectiveness of e-learning.
{"title":"Design and Implementation of Online Learning System: An Analysis from Students’ Perspectives","authors":"Anisa Moza Sabilla, Mahir Pradana","doi":"10.37394/232017.2024.15.4","DOIUrl":"https://doi.org/10.37394/232017.2024.15.4","url":null,"abstract":"The COVID-19 pandemic has changed the nature of education, leading to a move away from in-person instruction toward online training. This raises the question of how beneficial, given the COVID-19 epidemic, online schooling is. The effectiveness of e-learning and student efforts during the COVID-19 epidemic will be used in this study to measure the Telkom University S1 Business Administration department's level of learning satisfaction. This type of research is descriptive quantitative since it makes use of a questionnaire. A private university's hundred students made up the study's population. To evaluate data, use the SmartPLS program. The results of the data analysis show that learning satisfaction is significantly impacted by both student actions and the effectiveness of e-learning.","PeriodicalId":489755,"journal":{"name":"WSEAS Transactions on Electronics","volume":"41 25","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140728142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-04-02DOI: 10.37394/232017.2024.15.3
Rajath Ithal H. L., S. N., M. A. S.,, Nikhil B. G.
Constant transconductance (Gm) biasing circuits, as the name suggests, generate a bias current that ensures that the Gm of a MOS transistor remains constant. The Gm of a MOS transistor is a very important parameter as various other parameters of a circuit such as the gain, UGB (Unity Gain Bandwidth, poles, and zeros are strongly dependent upon it. Every analog circuit in a chip is subjected to varying PVT (Process, Voltage, and Temperature) conditions. This leads to a varying Gm of the devices, and hence the parameters such as the gain and UGB also tend to vary. Hence, constant Gm biasing is crucial in systems, where the parameters are expected to be constant regardless of the external factors. The majority of constant Gm biasing circuits make use of an external off-chip resistor. While this is a reasonable solution, it adds to the cost, area, and complexity of the solution. Hence, it is vital to model and design all the required functionalities within the chip, eliminating the requirement for any external components. In this paper, different architectures of constant Gm biasing circuits are designed and simulated in Cadence Virtuoso software. The proposed architecture has an error of 6.42% in the variation of transconductance, which is a significant improvement concerning the other architectures simulated. Additionally, the proposed architecture does not require any off-chip components while the other architectures require an off-chip resistor. Hence, the proposed solution has reduced cost and complexity.
{"title":"Design and Comparison of Constant Transconductance Architectures","authors":"Rajath Ithal H. L., S. N., M. A. S.,, Nikhil B. G.","doi":"10.37394/232017.2024.15.3","DOIUrl":"https://doi.org/10.37394/232017.2024.15.3","url":null,"abstract":"Constant transconductance (Gm) biasing circuits, as the name suggests, generate a bias current that ensures that the Gm of a MOS transistor remains constant. The Gm of a MOS transistor is a very important parameter as various other parameters of a circuit such as the gain, UGB (Unity Gain Bandwidth, poles, and zeros are strongly dependent upon it. Every analog circuit in a chip is subjected to varying PVT (Process, Voltage, and Temperature) conditions. This leads to a varying Gm of the devices, and hence the parameters such as the gain and UGB also tend to vary. Hence, constant Gm biasing is crucial in systems, where the parameters are expected to be constant regardless of the external factors. The majority of constant Gm biasing circuits make use of an external off-chip resistor. While this is a reasonable solution, it adds to the cost, area, and complexity of the solution. Hence, it is vital to model and design all the required functionalities within the chip, eliminating the requirement for any external components. In this paper, different architectures of constant Gm biasing circuits are designed and simulated in Cadence Virtuoso software. The proposed architecture has an error of 6.42% in the variation of transconductance, which is a significant improvement concerning the other architectures simulated. Additionally, the proposed architecture does not require any off-chip components while the other architectures require an off-chip resistor. Hence, the proposed solution has reduced cost and complexity.","PeriodicalId":489755,"journal":{"name":"WSEAS Transactions on Electronics","volume":"35 6","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140752659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-04-02DOI: 10.37394/232017.2024.15.2
Habbachi Nizar, Besbes Kamel
This paper presents the design and simulation of two-variable MEMS inductors for high-frequency applications. In two cases, the inductors' cores are enclosed between two tunable metal plates. The medium permeability changes in response to iron plate movement, ensuring a high-tuning range above 250%. The first inductor is designed for the 10 GHz range, and the inductance value is comprised of Lmin = 3.37 nH and increases to Lmax = 11.8 nH. Similar inductance values are obtained for the second inductor, but it is designed to work at 20 GHz. Furthermore, the maximum value of the quality factor of the second inductor is slightly higher than the first one and reaches Qmax = 17.5.
{"title":"Tunable RF MEMS Inductors for Two-Frequency Bands","authors":"Habbachi Nizar, Besbes Kamel","doi":"10.37394/232017.2024.15.2","DOIUrl":"https://doi.org/10.37394/232017.2024.15.2","url":null,"abstract":"This paper presents the design and simulation of two-variable MEMS inductors for high-frequency applications. In two cases, the inductors' cores are enclosed between two tunable metal plates. The medium permeability changes in response to iron plate movement, ensuring a high-tuning range above 250%. The first inductor is designed for the 10 GHz range, and the inductance value is comprised of Lmin = 3.37 nH and increases to Lmax = 11.8 nH. Similar inductance values are obtained for the second inductor, but it is designed to work at 20 GHz. Furthermore, the maximum value of the quality factor of the second inductor is slightly higher than the first one and reaches Qmax = 17.5.","PeriodicalId":489755,"journal":{"name":"WSEAS Transactions on Electronics","volume":"65 2","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140752553","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-01-23DOI: 10.37394/232017.2024.15.1
J. Ravindrababu, Dasi Swathi, J. V. R. Teja, J. V. R. Chandra, N. P. Sri, Shaik Arshiya
The Direct Sequence Code Division Multiple Access (DS-CDMA) system faces several disruptions, this is most crucial of which is the Multi Access Interference (MAI) caused by its users. The efficiency of the system gradually declines as every quantity rises, and the MAI rises, especially in faded environments. This work proposes a multiple-phase multiuser identification approach called Differencing Partial Parallel Interference Cancellation (DPPIC), which improves the overall efficiency. The methods known as Differencing Parallel Interference Cancellation (DPIC) and Partial Parallel Interference Cancellation (PPIC) are combined in this methodology. Current solutions for Parallel Interference Cancellation (PIC) and PPIC have enhanced overall effectiveness; however, this has come at the expense of increasing the complexity of computation. As the variety of consecutive stages grows, the MAI falls. Using the DPIC approach may reduce the computational burden without improving system functionality. The use of the Partial Differencing Parallel Interference Cancellation (PDPIC) technique can enhance system performance while lowering the level of complexity. According to the simulation findings, Bit Error Rate (BER) vs normalized signal strength (i.e., Eb / N0) performs more effectively for the suggested DPPIC approach than for PIC, the PPIC, and PDPIC.
{"title":"Analysis of Multiuser Detectors and Performance improvement in DS-CDMA system using Multistage Multiuser Detection Techniques","authors":"J. Ravindrababu, Dasi Swathi, J. V. R. Teja, J. V. R. Chandra, N. P. Sri, Shaik Arshiya","doi":"10.37394/232017.2024.15.1","DOIUrl":"https://doi.org/10.37394/232017.2024.15.1","url":null,"abstract":"The Direct Sequence Code Division Multiple Access (DS-CDMA) system faces several disruptions, this is most crucial of which is the Multi Access Interference (MAI) caused by its users. The efficiency of the system gradually declines as every quantity rises, and the MAI rises, especially in faded environments. This work proposes a multiple-phase multiuser identification approach called Differencing Partial Parallel Interference Cancellation (DPPIC), which improves the overall efficiency. The methods known as Differencing Parallel Interference Cancellation (DPIC) and Partial Parallel Interference Cancellation (PPIC) are combined in this methodology. Current solutions for Parallel Interference Cancellation (PIC) and PPIC have enhanced overall effectiveness; however, this has come at the expense of increasing the complexity of computation. As the variety of consecutive stages grows, the MAI falls. Using the DPIC approach may reduce the computational burden without improving system functionality. The use of the Partial Differencing Parallel Interference Cancellation (PDPIC) technique can enhance system performance while lowering the level of complexity. According to the simulation findings, Bit Error Rate (BER) vs normalized signal strength (i.e., Eb / N0) performs more effectively for the suggested DPPIC approach than for PIC, the PPIC, and PDPIC.","PeriodicalId":489755,"journal":{"name":"WSEAS Transactions on Electronics","volume":"106 3","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139606036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Electrical energy monitoring is increasingly important nowadays for residential and commercial usage. The energy meters are installed in consumer’s houses to track their energy usage. There are many chances of human mistakes for every electricity consumer while recording the manual energy meter reading in their houses. Also, the consumer does not have updated information about current electricity usage in each hour, day, and month. To overcome the above problems, the system is developed to remotely monitor from any world location using the NodeMCU and Arduino IDE. The energy monitoring is carried out by using the Node MCU, Arduino IDE, and PZEM-004T sensor. The PZEM-004T module is coupled to the Arduino controller. The sensor module receives a signal from the CT coil which is connected to load. The load parameters such as voltage current power etc., are measured and transferred to the Arduino. A NodeMCU ESP8266 is utilized as a Wi-Fi chip system. By using a Wi-Fi connection and the internet, the acquired data is sent to Thing Speak to save in the cloud to monitor the measured parameters remotely. The power analyzer instrument is also used to measure the real-time parameters consumed by the load which is used to cross verification and compare with the sensor measuring parameters. The passive load resistance, inductance, and 100-watt lamp loads are experimentally connected and tested. The load consumed electrical parameters such as current, voltage, power, power factor, real power, and frequency are monitored in online. Energy monitoring online may reduce the consumer's mistakes by recording the parameters and consumers can know each hour, day, and month's energy consumption up to date according to their usage.
{"title":"IOT based Energy Monitoring for Practical Loads using NodeMCU","authors":"Loganathan , Nachimuthu, Reem Ahmed Al-Mahrouqi, Tamadhar Salim Al-Abri, Muna Al-Hadrami","doi":"10.37394/232017.2023.14.6","DOIUrl":"https://doi.org/10.37394/232017.2023.14.6","url":null,"abstract":"Electrical energy monitoring is increasingly important nowadays for residential and commercial usage. The energy meters are installed in consumer’s houses to track their energy usage. There are many chances of human mistakes for every electricity consumer while recording the manual energy meter reading in their houses. Also, the consumer does not have updated information about current electricity usage in each hour, day, and month. To overcome the above problems, the system is developed to remotely monitor from any world location using the NodeMCU and Arduino IDE. The energy monitoring is carried out by using the Node MCU, Arduino IDE, and PZEM-004T sensor. The PZEM-004T module is coupled to the Arduino controller. The sensor module receives a signal from the CT coil which is connected to load. The load parameters such as voltage current power etc., are measured and transferred to the Arduino. A NodeMCU ESP8266 is utilized as a Wi-Fi chip system. By using a Wi-Fi connection and the internet, the acquired data is sent to Thing Speak to save in the cloud to monitor the measured parameters remotely. The power analyzer instrument is also used to measure the real-time parameters consumed by the load which is used to cross verification and compare with the sensor measuring parameters. The passive load resistance, inductance, and 100-watt lamp loads are experimentally connected and tested. The load consumed electrical parameters such as current, voltage, power, power factor, real power, and frequency are monitored in online. Energy monitoring online may reduce the consumer's mistakes by recording the parameters and consumers can know each hour, day, and month's energy consumption up to date according to their usage.","PeriodicalId":489755,"journal":{"name":"WSEAS Transactions on Electronics","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135479626","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-11-07DOI: 10.37394/232017.2023.14.7
Adil Alahmad, Firat Kaçar, Cengiz Polat Uzunoğlu
The drawbacks of traditional inverters, particularly in high-power applications and medium voltage, have been highlighted in previous investigations. Due to the cascaded H-bridge multilevel driver (CHBMD) harmonic characteristics improved and power enhanced, inverters with multiple levels are increasingly popular for high-power applications. The scientific literature has documented works on multilevel inverter topologies, control strategies, and applications. Additionally, no conclusive results investigate or rate a three-phase multilevel inverter's effectiveness. The present investigation evaluates the performance of a multi-carrier sinusoidal pulse width modification (MCS-PWM) based, Seven-Level cascaded H-bridge multilevel driver (7LCHBMD). Performance assessments develop based on the outcomes of a modeling experiment on the CHBMD functionality utilizing MATLAB. The characteristics of the results chosen to perform the task were the harmonic range, waveform arrangement, and essential significance reducing the THD output of the 7LCHBMD. The MCS-PWM technique procedure from the perspective of the voltage line had been determined according to the findings of the simulation investigation and analysis carried out for the 7LCHBMD utilizing the PD-PWM as the control framework.
{"title":"Medium-Voltage Drives (MVD) - Performance Analysis of Seven-Level Cascaded H-Bridge Multilevel Driver","authors":"Adil Alahmad, Firat Kaçar, Cengiz Polat Uzunoğlu","doi":"10.37394/232017.2023.14.7","DOIUrl":"https://doi.org/10.37394/232017.2023.14.7","url":null,"abstract":"The drawbacks of traditional inverters, particularly in high-power applications and medium voltage, have been highlighted in previous investigations. Due to the cascaded H-bridge multilevel driver (CHBMD) harmonic characteristics improved and power enhanced, inverters with multiple levels are increasingly popular for high-power applications. The scientific literature has documented works on multilevel inverter topologies, control strategies, and applications. Additionally, no conclusive results investigate or rate a three-phase multilevel inverter's effectiveness. The present investigation evaluates the performance of a multi-carrier sinusoidal pulse width modification (MCS-PWM) based, Seven-Level cascaded H-bridge multilevel driver (7LCHBMD). Performance assessments develop based on the outcomes of a modeling experiment on the CHBMD functionality utilizing MATLAB. The characteristics of the results chosen to perform the task were the harmonic range, waveform arrangement, and essential significance reducing the THD output of the 7LCHBMD. The MCS-PWM technique procedure from the perspective of the voltage line had been determined according to the findings of the simulation investigation and analysis carried out for the 7LCHBMD utilizing the PD-PWM as the control framework.","PeriodicalId":489755,"journal":{"name":"WSEAS Transactions on Electronics","volume":"312 6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135474675","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：