Pub Date : 2019-10-01DOI: 10.1109/Austrochip.2019.00012
Luca Sant, E. Bach, R. Gaggl, A. Baschirotto
This work presents a read-out amplifier for capacitive sensors, in particular for MEMS microphones, based on a current-feedback topology. This architecture allows for an extensive gain range while keeping the input impedance as well as the amplifier bandwidth independent of the selected gain. Noise performance is maximized and signal attenuation due to parasitic effects is minimized and stays constant at all gain settings. This architecture has been used for the design of an interface circuit for a MEMS microphone in a standard 0.13µm CMOS process.
这项工作提出了一种基于电流反馈拓扑的电容式传感器读出放大器，特别是用于MEMS麦克风。这种结构允许广泛的增益范围，同时保持输入阻抗以及放大器带宽与所选增益无关。噪声性能最大化，信号衰减由于寄生效应最小化，并保持恒定在所有增益设置。该架构已用于标准0.13 μ m CMOS工艺的MEMS麦克风接口电路的设计。
{"title":"A Current-Feedback Amplifier with Programmable Gain for MEMS Microphone Read-Out Circuits","authors":"Luca Sant, E. Bach, R. Gaggl, A. Baschirotto","doi":"10.1109/Austrochip.2019.00012","DOIUrl":"https://doi.org/10.1109/Austrochip.2019.00012","url":null,"abstract":"This work presents a read-out amplifier for capacitive sensors, in particular for MEMS microphones, based on a current-feedback topology. This architecture allows for an extensive gain range while keeping the input impedance as well as the amplifier bandwidth independent of the selected gain. Noise performance is maximized and signal attenuation due to parasitic effects is minimized and stays constant at all gain settings. This architecture has been used for the design of an interface circuit for a MEMS microphone in a standard 0.13µm CMOS process.","PeriodicalId":6724,"journal":{"name":"2019 Austrochip Workshop on Microelectronics (Austrochip)","volume":"23 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87931222","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/Austrochip.2019.00021
Tommaso Vincenzi, G. Schatzberger, A. Michalowska-Forsyth
This paper presents a charge-based Non-Volatile Memory device: the Sidewall Spacer. Multiple TSMC 55nm dies were tested up to 100krad to explore the effect of the programming time on data retention.
{"title":"Program Time Effects on Total Ionizing Dose Tolerance of Sidewall Spacer Memory Bit Cell","authors":"Tommaso Vincenzi, G. Schatzberger, A. Michalowska-Forsyth","doi":"10.1109/Austrochip.2019.00021","DOIUrl":"https://doi.org/10.1109/Austrochip.2019.00021","url":null,"abstract":"This paper presents a charge-based Non-Volatile Memory device: the Sidewall Spacer. Multiple TSMC 55nm dies were tested up to 100krad to explore the effect of the programming time on data retention.","PeriodicalId":6724,"journal":{"name":"2019 Austrochip Workshop on Microelectronics (Austrochip)","volume":"6 1","pages":"55-58"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89114203","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/Austrochip.2019.00027
P. Roessler, R. Höller, C. Reisner, O. Maischberger
This work provides an overview of digital logic simulators which are the classical tools for verification of digital hardware. Existing simulators and their features are presented and both commercial simulators as well as tools from the open-source community are included in our survey. Furthermore, the tools have been evaluated using a set of benchmark designs. All of the evaluation designs are freely available over the internet and have been carefully selected so that everybody can prove the results presented herein. To the authors best knowledge this is the first public available overview on existing digital logic simulators since 20 years.
{"title":"Survey and Comparison of Digital Logic Simulators","authors":"P. Roessler, R. Höller, C. Reisner, O. Maischberger","doi":"10.1109/Austrochip.2019.00027","DOIUrl":"https://doi.org/10.1109/Austrochip.2019.00027","url":null,"abstract":"This work provides an overview of digital logic simulators which are the classical tools for verification of digital hardware. Existing simulators and their features are presented and both commercial simulators as well as tools from the open-source community are included in our survey. Furthermore, the tools have been evaluated using a set of benchmark designs. All of the evaluation designs are freely available over the internet and have been carefully selected so that everybody can prove the results presented herein. To the authors best knowledge this is the first public available overview on existing digital logic simulators since 20 years.","PeriodicalId":6724,"journal":{"name":"2019 Austrochip Workshop on Microelectronics (Austrochip)","volume":"22 1","pages":"87-92"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73765655","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/Austrochip.2019.00016
T. Paireder, C. Motz, O. Lang, M. Huemer
Transmitter-to-receiver (Tx-Rx) leakage is a widely covered downside of state-of-the-art frequency division duplex radio frequency transceivers for use in mobile communication devices. Despite the distance between Tx and Rx carrier frequencies, non-idealities of the analog front-end cause receiver desensitization by folding transmit signal components into the Rx baseband. In literature, several countermeasures for this self-interference issue have been proposed, including fully-digital and mixed-signal mitigation strategies. Both methods employ signal estimation techniques in the digital domain to replicate and cancel the interference. An apparent issue of these methods is the unknown and usually time-varying delay of the leakage signal through the analog front-end of the device. Insufficient alignment of the signals used by the estimator causes severe degradation of the cancellation performance. In this work, we provide a mathematical analysis of a linear system identification scenario in the presence of an alignment mismatch. Based on these results, we present two low-complexity algorithms for static time-delay estimation and online tracking, accompanied by suitable digital hardware implementations. With focus on the particularly challenging signal statistics of Long Term Evolution (LTE) signals, we show the expectable performance of the algorithms for a specific linear self-interference cancellation task.
{"title":"Time-Delay Estimation for Self-Interference Cancellation in LTE-A/5G Transceivers","authors":"T. Paireder, C. Motz, O. Lang, M. Huemer","doi":"10.1109/Austrochip.2019.00016","DOIUrl":"https://doi.org/10.1109/Austrochip.2019.00016","url":null,"abstract":"Transmitter-to-receiver (Tx-Rx) leakage is a widely covered downside of state-of-the-art frequency division duplex radio frequency transceivers for use in mobile communication devices. Despite the distance between Tx and Rx carrier frequencies, non-idealities of the analog front-end cause receiver desensitization by folding transmit signal components into the Rx baseband. In literature, several countermeasures for this self-interference issue have been proposed, including fully-digital and mixed-signal mitigation strategies. Both methods employ signal estimation techniques in the digital domain to replicate and cancel the interference. An apparent issue of these methods is the unknown and usually time-varying delay of the leakage signal through the analog front-end of the device. Insufficient alignment of the signals used by the estimator causes severe degradation of the cancellation performance. In this work, we provide a mathematical analysis of a linear system identification scenario in the presence of an alignment mismatch. Based on these results, we present two low-complexity algorithms for static time-delay estimation and online tracking, accompanied by suitable digital hardware implementations. With focus on the particularly challenging signal statistics of Long Term Evolution (LTE) signals, we show the expectable performance of the algorithms for a specific linear self-interference cancellation task.","PeriodicalId":6724,"journal":{"name":"2019 Austrochip Workshop on Microelectronics (Austrochip)","volume":"33 1","pages":"21-28"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91330743","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/Austrochip.2019.00022
E. Hager, S. Broussev, H. Pretl
In this paper a Digitally-Controlled Oscillator (DCO) with configurable power consumption and phase-noise is presented. The DCO provides two different power/phase-noise modes while maintaining an almost constant figure-of-merit (FoM) by using a tapped inductor in the LC tank. For each mode (low-power and low-noise mode) a different DCO core is selected, which either connects to the outer taps of the tank inductor or to the inner ones. The presented design achieves a tuning range of 25.9 % with a center frequency of 4.88 GHz at a FoM of approximately 185 dBc/Hz. The DCO concept is simulated in a 16 nm FinFET CMOS process.
{"title":"A 16-nm FinFET Power- and Phase Noise-Scalable DCO using On-Chip Tapped Inductor","authors":"E. Hager, S. Broussev, H. Pretl","doi":"10.1109/Austrochip.2019.00022","DOIUrl":"https://doi.org/10.1109/Austrochip.2019.00022","url":null,"abstract":"In this paper a Digitally-Controlled Oscillator (DCO) with configurable power consumption and phase-noise is presented. The DCO provides two different power/phase-noise modes while maintaining an almost constant figure-of-merit (FoM) by using a tapped inductor in the LC tank. For each mode (low-power and low-noise mode) a different DCO core is selected, which either connects to the outer taps of the tank inductor or to the inner ones. The presented design achieves a tuning range of 25.9 % with a center frequency of 4.88 GHz at a FoM of approximately 185 dBc/Hz. The DCO concept is simulated in a 16 nm FinFET CMOS process.","PeriodicalId":6724,"journal":{"name":"2019 Austrochip Workshop on Microelectronics (Austrochip)","volume":"111 1","pages":"59-64"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76239007","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/Austrochip.2019.00017
M. Adamič, A. Trost
A high-resolution time-to-digital converter (TDC) was implemented on a Red Pitaya board, featuring a Xilinx Zynq 7010 fully programmable 28-nm system on chip (SoC). The TDC is based on an internal tapped delay line for fine time measurements. First experimental results point towards very high performance of the design, achieving 350 MHz clock speed and sub 20 ps time resolution. The work is part of a Master thesis research and serves as a demonstration of what is possible today with a fairly simple design and a low-cost modern FPGA. The chip used is the smallest dual-core Zynq-7000 device, which makes development boards like Red Pitaya easily affordable for universities. We make good use of on-board Linux to send gathered data via Ethernet to a PC client with a graphical user interface to access the TDC. The design is fully customizable and comes in the form of an independent TDC channel IP core. This offers the possibility of easily implementing TDC systems with an arbitrary number of TDC channels.
{"title":"A Fast High-Resolution Time-to-Digital Converter Implemented in a Zynq 7010 SoC","authors":"M. Adamič, A. Trost","doi":"10.1109/Austrochip.2019.00017","DOIUrl":"https://doi.org/10.1109/Austrochip.2019.00017","url":null,"abstract":"A high-resolution time-to-digital converter (TDC) was implemented on a Red Pitaya board, featuring a Xilinx Zynq 7010 fully programmable 28-nm system on chip (SoC). The TDC is based on an internal tapped delay line for fine time measurements. First experimental results point towards very high performance of the design, achieving 350 MHz clock speed and sub 20 ps time resolution. The work is part of a Master thesis research and serves as a demonstration of what is possible today with a fairly simple design and a low-cost modern FPGA. The chip used is the smallest dual-core Zynq-7000 device, which makes development boards like Red Pitaya easily affordable for universities. We make good use of on-board Linux to send gathered data via Ethernet to a PC client with a graphical user interface to access the TDC. The design is fully customizable and comes in the form of an independent TDC channel IP core. This offers the possibility of easily implementing TDC systems with an arbitrary number of TDC channels.","PeriodicalId":6724,"journal":{"name":"2019 Austrochip Workshop on Microelectronics (Austrochip)","volume":"104 1","pages":"29-34"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79531540","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/Austrochip.2019.00015
D. Hamidovic, J. Markovic, P. Preyler, C. Mayer, Mario Huemer, Andreas Springer
In this paper, an overview of different RF transmitter architectures, based on the RF-DAC implementation is given. The evolution of different types of architectures is displayed with the explanation of the main advantages and limitations and/or challenges of each architecture in usage for today's and future cellular handset-applications. The block diagrams of each architecture are shown and the most important parameters are compared across the different implementations. Additionally, the impact of a non-ideal 50% duty-cycle of the RF LO on the spectrum of the RF signal, generated by the RF-DAC is shown.
{"title":"A Comparison of All-Digital Transmitter Architectures for Cellular Handsets","authors":"D. Hamidovic, J. Markovic, P. Preyler, C. Mayer, Mario Huemer, Andreas Springer","doi":"10.1109/Austrochip.2019.00015","DOIUrl":"https://doi.org/10.1109/Austrochip.2019.00015","url":null,"abstract":"In this paper, an overview of different RF transmitter architectures, based on the RF-DAC implementation is given. The evolution of different types of architectures is displayed with the explanation of the main advantages and limitations and/or challenges of each architecture in usage for today's and future cellular handset-applications. The block diagrams of each architecture are shown and the most important parameters are compared across the different implementations. Additionally, the impact of a non-ideal 50% duty-cycle of the RF LO on the spectrum of the RF signal, generated by the RF-DAC is shown.","PeriodicalId":6724,"journal":{"name":"2019 Austrochip Workshop on Microelectronics (Austrochip)","volume":"82 1","pages":"14-20"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78201137","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/Austrochip.2019.00028
Arash Ebrahimi Jarihani, Sahar Sarafi, Michael Köberle, J. Sturm, A. Tonello
Performance of a high-speed network on a chip is mainly affected by the performance of the global on-chip interconnects. This paper investigates a point-to-point transmission line interconnect to address the performance limitations due to the scaling problems of on-chip global interconnects in new CMOS technologies. A brief explanation is given about the basic properties of the transmission lines that should be considered. Moreover, the design methodology is given for designing the on-chip interconnect and understanding its behavior. Based on the different transmission line geometry, 3D EM simulations are done and S-parameters are carried out to analyze the effects of the different metal layers, width of the signal line, and space to shield layers of the interconnect. This results in a systematic understanding of the design of the on-chip interconnect and its performance dependence on various parameters. Finally, a 5 mm length on-chip lossy transmission line with serpentine shape and shielding layers is implemented in 8-metal-layer 28 nm CMOS standard technology.
{"title":"Characterization of On-Chip Interconnects: Case Study in 28 nm CMOS Technology","authors":"Arash Ebrahimi Jarihani, Sahar Sarafi, Michael Köberle, J. Sturm, A. Tonello","doi":"10.1109/Austrochip.2019.00028","DOIUrl":"https://doi.org/10.1109/Austrochip.2019.00028","url":null,"abstract":"Performance of a high-speed network on a chip is mainly affected by the performance of the global on-chip interconnects. This paper investigates a point-to-point transmission line interconnect to address the performance limitations due to the scaling problems of on-chip global interconnects in new CMOS technologies. A brief explanation is given about the basic properties of the transmission lines that should be considered. Moreover, the design methodology is given for designing the on-chip interconnect and understanding its behavior. Based on the different transmission line geometry, 3D EM simulations are done and S-parameters are carried out to analyze the effects of the different metal layers, width of the signal line, and space to shield layers of the interconnect. This results in a systematic understanding of the design of the on-chip interconnect and its performance dependence on various parameters. Finally, a 5 mm length on-chip lossy transmission line with serpentine shape and shielding layers is implemented in 8-metal-layer 28 nm CMOS standard technology.","PeriodicalId":6724,"journal":{"name":"2019 Austrochip Workshop on Microelectronics (Austrochip)","volume":"90 1","pages":"93-99"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74742046","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/Austrochip.2019.00024
Graciele Batistell, Sina Mortezazadeh Mahani, Suchendranath Popuri, Ajinkya Kale, J. Sturm, W. Bösch
This paper presents the circuit analysis of a transformer based balun with emphasis on the improvement of Common-Mode Isolation (CMI). Critical parameters are identified based on the initial analysis of the transformer equivalent circuit. Additionally, the influence of the transformers load impedance and the use of Center-Tap (CT) on CMI enhancement are presented. EM simulations of two transformers, a stacked and an interleaved version, designed in 65 nm CMOS technology are presented. The CMI performance of both the transformers is compared to the proposed circuit model and the effect of layout and geometry is also analyzed. Finally, guidelines are presented for the design of transformer based baluns with improved CMI performance.
{"title":"Analysis of Common-Mode Isolation on Transformer Based Balun","authors":"Graciele Batistell, Sina Mortezazadeh Mahani, Suchendranath Popuri, Ajinkya Kale, J. Sturm, W. Bösch","doi":"10.1109/Austrochip.2019.00024","DOIUrl":"https://doi.org/10.1109/Austrochip.2019.00024","url":null,"abstract":"This paper presents the circuit analysis of a transformer based balun with emphasis on the improvement of Common-Mode Isolation (CMI). Critical parameters are identified based on the initial analysis of the transformer equivalent circuit. Additionally, the influence of the transformers load impedance and the use of Center-Tap (CT) on CMI enhancement are presented. EM simulations of two transformers, a stacked and an interleaved version, designed in 65 nm CMOS technology are presented. The CMI performance of both the transformers is compared to the proposed circuit model and the effect of layout and geometry is also analyzed. Finally, guidelines are presented for the design of transformer based baluns with improved CMI performance.","PeriodicalId":6724,"journal":{"name":"2019 Austrochip Workshop on Microelectronics (Austrochip)","volume":"154 1","pages":"71-75"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80386145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/Austrochip.2019.00019
Ram Ratnaker Reddy Bodha, Sahar Sarafi, Ajinkya Kale, M. Koberle, J. Sturm
In this work, a half-rate built-in self-test (BIST) system is proposed to enable bit error rate measurement without the need for off-chip subsystems such as memory and PRBS generator. The proposed BIST system consists of a half-rate series-parallel PRBS generator with a unique pattern to self-synchronize the received data stream with the reference data at the half-rate bit error checker. The proposed BIST system schematic is implemented in 0.9V, 28nm CMOS technology for a 10 Gbps on-chip serial data transmission system. The RMS jitter at the PRBS generator output is evaluated to be 1.45 ps with post-layout simulation considering the output loading in nominal conditions. The PRBS generator and bit error checker consumed total power of 5.225 mW in nominal conditions.
{"title":"A Half-Rate Built-In Self-Test for High-Speed Serial Interface using a PRBS Generator and Checker","authors":"Ram Ratnaker Reddy Bodha, Sahar Sarafi, Ajinkya Kale, M. Koberle, J. Sturm","doi":"10.1109/Austrochip.2019.00019","DOIUrl":"https://doi.org/10.1109/Austrochip.2019.00019","url":null,"abstract":"In this work, a half-rate built-in self-test (BIST) system is proposed to enable bit error rate measurement without the need for off-chip subsystems such as memory and PRBS generator. The proposed BIST system consists of a half-rate series-parallel PRBS generator with a unique pattern to self-synchronize the received data stream with the reference data at the half-rate bit error checker. The proposed BIST system schematic is implemented in 0.9V, 28nm CMOS technology for a 10 Gbps on-chip serial data transmission system. The RMS jitter at the PRBS generator output is evaluated to be 1.45 ps with post-layout simulation considering the output loading in nominal conditions. The PRBS generator and bit error checker consumed total power of 5.225 mW in nominal conditions.","PeriodicalId":6724,"journal":{"name":"2019 Austrochip Workshop on Microelectronics (Austrochip)","volume":"41 3 1","pages":"43-46"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85774673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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