Bluetooth Low Energy (BLE) is designed for the purpose of reducing the energy consumption and extending the life cycle of Bluetooth devices. Its application scenario lies in a small-scale Internet of Things environment. These devices are usually small and exquisite and easy to carry. Since these devices are powered by the battery inside, it is an important issue for BLE to reduce power consumption and extend usage time without reducing performance. The data communication of BLE devices can only start after advertising, scanning, and connecting. Therefore, the configuration of advertising and scanning parameters of BLE devices is another important issue that affects performance. For advertising, there are advertising interval, advertising event, random delay, etc. For scanning, there are scan window, scan interval, etc. The combination of different parameters can lead to a large variation in the neighbor discovery process (NDP) time. In this paper, we investigate and analyze the relationship between parameters and the discovery latency. We show that unbounded latency could occur when the advertising interval is equal to an integer multiple of scan interval minus the average random delay. We further propose a method to bound the discovery latency by adjusting the parameters as appropriate during the discovery process.
{"title":"Bounding Latency in Bluetooth Low Energy Device Discovery","authors":"Bing-Han Shih, Yang-Ren Chen, T. Hou","doi":"10.1145/3560089.3560097","DOIUrl":"https://doi.org/10.1145/3560089.3560097","url":null,"abstract":"Bluetooth Low Energy (BLE) is designed for the purpose of reducing the energy consumption and extending the life cycle of Bluetooth devices. Its application scenario lies in a small-scale Internet of Things environment. These devices are usually small and exquisite and easy to carry. Since these devices are powered by the battery inside, it is an important issue for BLE to reduce power consumption and extend usage time without reducing performance. The data communication of BLE devices can only start after advertising, scanning, and connecting. Therefore, the configuration of advertising and scanning parameters of BLE devices is another important issue that affects performance. For advertising, there are advertising interval, advertising event, random delay, etc. For scanning, there are scan window, scan interval, etc. The combination of different parameters can lead to a large variation in the neighbor discovery process (NDP) time. In this paper, we investigate and analyze the relationship between parameters and the discovery latency. We show that unbounded latency could occur when the advertising interval is equal to an integer multiple of scan interval minus the average random delay. We further propose a method to bound the discovery latency by adjusting the parameters as appropriate during the discovery process.","PeriodicalId":104014,"journal":{"name":"Proceedings of the 4th International Electronics Communication Conference","volume":"113 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130783616","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
One important building block for an integrated 60GHz millimeter-wave CMOS radio transceiver is low-noise amplifier (LNA). In this paper, two- stage cascode LNA with first stage as CS inductive source degeneration has been employed. Gain boosting technique is used to increase gain, where an inductor is attached to the gate of ,common gate stage and also network to provide positive feedback. Besides that, SNM (simultaneous noise and input conjugate impedance) matching is used. This design is simulated in 130nm bulk CMOS TSMC process by using cadence virtuoso. Each stage is biased separately by using supply voltage of 1.2V, where = 727mV for an individual stage is generated through this biasing network. Performance metrics of this design are peak gain of 20.3dB, an output-referred 1dB compression point of -22.6dBm at 60GHz, noise figure is 6.3 dB and maximum power dissipation () is 12mW.
{"title":"60GHz, 12mW, 20 dB Gain, CMOS mm-wave LNA with 6.3-dB NF","authors":"Muhammad Shuaib","doi":"10.1145/3560089.3560091","DOIUrl":"https://doi.org/10.1145/3560089.3560091","url":null,"abstract":"One important building block for an integrated 60GHz millimeter-wave CMOS radio transceiver is low-noise amplifier (LNA). In this paper, two- stage cascode LNA with first stage as CS inductive source degeneration has been employed. Gain boosting technique is used to increase gain, where an inductor is attached to the gate of ,common gate stage and also network to provide positive feedback. Besides that, SNM (simultaneous noise and input conjugate impedance) matching is used. This design is simulated in 130nm bulk CMOS TSMC process by using cadence virtuoso. Each stage is biased separately by using supply voltage of 1.2V, where = 727mV for an individual stage is generated through this biasing network. Performance metrics of this design are peak gain of 20.3dB, an output-referred 1dB compression point of -22.6dBm at 60GHz, noise figure is 6.3 dB and maximum power dissipation () is 12mW.","PeriodicalId":104014,"journal":{"name":"Proceedings of the 4th International Electronics Communication Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132908888","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Fang Nan, Xiaolei Huo, Chao Fan, Peng Chen, Yuetian Zhou, Li Wang, Jiangpin Yang
Almost blank subframe (ABS) is an effective method to eliminate interference in heterogeneous networks, but the existence of ABS will cause the degradation of the communication performance of the macro cell. To tackle this issue, an improved ABS technology based on interference suppression was proposed in this paper. Firstly, the channel parameters are estimated in the ABS frame and sent back to the micro base station (BS). Secondly, the micro BS uses the estimated parameters and the synchronized digital signal of the macro BS to calculate the pre-processed digital signal. Finally, the predistortion part of the signal from the micro BS and the signal from the macro BS cancel each other out at the terminal. The proposed method can alleviate the interference of the macro BS to the edge users of the small cell, and significantly reduce the proportion of ABS frames in the macro BS, thereby improving the communication performance of the macro cell.
{"title":"Improved Almost Blank Subframe Technology Based On Interference Suppression","authors":"Fang Nan, Xiaolei Huo, Chao Fan, Peng Chen, Yuetian Zhou, Li Wang, Jiangpin Yang","doi":"10.1145/3560089.3560100","DOIUrl":"https://doi.org/10.1145/3560089.3560100","url":null,"abstract":"Almost blank subframe (ABS) is an effective method to eliminate interference in heterogeneous networks, but the existence of ABS will cause the degradation of the communication performance of the macro cell. To tackle this issue, an improved ABS technology based on interference suppression was proposed in this paper. Firstly, the channel parameters are estimated in the ABS frame and sent back to the micro base station (BS). Secondly, the micro BS uses the estimated parameters and the synchronized digital signal of the macro BS to calculate the pre-processed digital signal. Finally, the predistortion part of the signal from the micro BS and the signal from the macro BS cancel each other out at the terminal. The proposed method can alleviate the interference of the macro BS to the edge users of the small cell, and significantly reduce the proportion of ABS frames in the macro BS, thereby improving the communication performance of the macro cell.","PeriodicalId":104014,"journal":{"name":"Proceedings of the 4th International Electronics Communication Conference","volume":"39 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120927329","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This research aims to ingestigate the effect of technological progress on capital input. To meet the research objective, the simple closed economy DSGE model was constructed. The Bayesian technique is then employed to estimate the model parameters by using the quarterly detrended data of Thailand, which covers the period between 2001:Q1 and 2019:Q2, including GDP, policy rate, and employment. The result showed that technological progress can produce potential effects on major economic variables, namely labor, capital, price, return, consumption, and national income, and fits some previous studies. Therefore, government investment in technology and support for technology development should lead to economic growth.
{"title":"The Effect of Technology on Economy","authors":"N. Rojniruttikul, Adirek Vajrapatkul","doi":"10.1145/3560089.3560103","DOIUrl":"https://doi.org/10.1145/3560089.3560103","url":null,"abstract":"This research aims to ingestigate the effect of technological progress on capital input. To meet the research objective, the simple closed economy DSGE model was constructed. The Bayesian technique is then employed to estimate the model parameters by using the quarterly detrended data of Thailand, which covers the period between 2001:Q1 and 2019:Q2, including GDP, policy rate, and employment. The result showed that technological progress can produce potential effects on major economic variables, namely labor, capital, price, return, consumption, and national income, and fits some previous studies. Therefore, government investment in technology and support for technology development should lead to economic growth.","PeriodicalId":104014,"journal":{"name":"Proceedings of the 4th International Electronics Communication Conference","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115624092","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The dynamic development of network services puts forward higher requirements for traditional information networks. In order to adapt to the development, the concept of "reconfigurable network" is proposed to improve the robustness and expansibility of network service support. However, the reconfiguration of the routing switching platform represented by the upgrading of the architecture hardware system will bring great cost pressure to users. In order to reduce the operation and maintenance cost of the network system and improve the reliability of the network system, the reconfiguration of the routing switching platform gradually transits and develops to the direction of retaining hardware equipment, upgrading software system and updating some equipment. In this paper, it analyses and design the security architecture of the open reconfigurable routing and switching platform to meet the demand for high speed, high capacity and high efficiency processing of network information, especially the demand for secure data transmission and exchange. For the prominent and critical security issues and matters in the reconfigurable routing and switching platform, the security reconfiguration method of platform components and components is constructed, and the system of components is analysed and modelled. Finally, the effectiveness and necessity of security techniques applied in the open reconfigurable routing and switching platform are verified.
{"title":"Research on Security Technologies for Open Reconfigurable Routing and Switching Platforms","authors":"Yi Yang, Qian Zhang","doi":"10.1145/3560089.3560101","DOIUrl":"https://doi.org/10.1145/3560089.3560101","url":null,"abstract":"The dynamic development of network services puts forward higher requirements for traditional information networks. In order to adapt to the development, the concept of \"reconfigurable network\" is proposed to improve the robustness and expansibility of network service support. However, the reconfiguration of the routing switching platform represented by the upgrading of the architecture hardware system will bring great cost pressure to users. In order to reduce the operation and maintenance cost of the network system and improve the reliability of the network system, the reconfiguration of the routing switching platform gradually transits and develops to the direction of retaining hardware equipment, upgrading software system and updating some equipment. In this paper, it analyses and design the security architecture of the open reconfigurable routing and switching platform to meet the demand for high speed, high capacity and high efficiency processing of network information, especially the demand for secure data transmission and exchange. For the prominent and critical security issues and matters in the reconfigurable routing and switching platform, the security reconfiguration method of platform components and components is constructed, and the system of components is analysed and modelled. Finally, the effectiveness and necessity of security techniques applied in the open reconfigurable routing and switching platform are verified.","PeriodicalId":104014,"journal":{"name":"Proceedings of the 4th International Electronics Communication Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128038717","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Wireless communication systems are evolving to the next generation to cover larger bandwidth to provide higher data rates, higher connection density, and higher reliability. Broadband Communication such as millimeter wave (mmWave) communications and teraHertz (THz) communications are both key enablers of 6G networks. Due to the inherent nonlinearity of the radio frequency (RF) components, such as power amplifiers (PAs) and mixers, larger bandwidth with high-speed modulation would cause serious nonlinear distortion, which would significantly degrade the quality of the transmission signal.If simply transmitting signal at a power level with large back-off, the power efficiency of the transmitter would dramatically drop to a unacceptable level, which would deviate from green communications with less power consumption.The digital pre-distortion (DPD) technique usually be used to correct the nonlinearity from these RF component and integration module. However, in the conventional DPD, the sampling rate of analog-to-digital (ADC) and digital-to-analog (DAC) is ten times as bandwidth for the transmitting signal, which is impractical for broadband applications, such as THz communication. Therefore, this paper proposed a novel linearization method to use ADC and DAC with low sampling rates. A nonlinearity correction model with under sampling signals are derived. Finally, simulation results verify the effectiveness of the theoretical analysis and demonstrate that the proposed linearization method could improve the EVM from 9% to 2% for a 64-QAM signal of 2 GHz bandwidth.
{"title":"A wideband linearization method using low-sampling ADCs and DACs","authors":"Fang Nan, Jianchi Zhu, X. She, Shujie Dai, Hongkun Liu, Jinlong Liu, Yingjie Liu","doi":"10.1145/3560089.3560095","DOIUrl":"https://doi.org/10.1145/3560089.3560095","url":null,"abstract":"Wireless communication systems are evolving to the next generation to cover larger bandwidth to provide higher data rates, higher connection density, and higher reliability. Broadband Communication such as millimeter wave (mmWave) communications and teraHertz (THz) communications are both key enablers of 6G networks. Due to the inherent nonlinearity of the radio frequency (RF) components, such as power amplifiers (PAs) and mixers, larger bandwidth with high-speed modulation would cause serious nonlinear distortion, which would significantly degrade the quality of the transmission signal.If simply transmitting signal at a power level with large back-off, the power efficiency of the transmitter would dramatically drop to a unacceptable level, which would deviate from green communications with less power consumption.The digital pre-distortion (DPD) technique usually be used to correct the nonlinearity from these RF component and integration module. However, in the conventional DPD, the sampling rate of analog-to-digital (ADC) and digital-to-analog (DAC) is ten times as bandwidth for the transmitting signal, which is impractical for broadband applications, such as THz communication. Therefore, this paper proposed a novel linearization method to use ADC and DAC with low sampling rates. A nonlinearity correction model with under sampling signals are derived. Finally, simulation results verify the effectiveness of the theoretical analysis and demonstrate that the proposed linearization method could improve the EVM from 9% to 2% for a 64-QAM signal of 2 GHz bandwidth.","PeriodicalId":104014,"journal":{"name":"Proceedings of the 4th International Electronics Communication Conference","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127785649","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Comparing with Radio frequency calibration technology, the main channel calibration part of Digital calibration technology is done in the digital part, which is mainly achieved by means of digital filters, digital delay lines, etc. In 5G MIMO antenna system, two channels share one crystal oscillator, real-time calibration needs to be done when rebooting the system. Based on this problem, a new digital calibration algorithm of integrative transceiver including the initial phase of the crystal oscillator is proposed in this paper. Related tests of antennas and arrays are also carried out.
{"title":"MIMO Antenna and Digital Calibration Technology","authors":"C. Bai","doi":"10.1145/3560089.3560092","DOIUrl":"https://doi.org/10.1145/3560089.3560092","url":null,"abstract":"Comparing with Radio frequency calibration technology, the main channel calibration part of Digital calibration technology is done in the digital part, which is mainly achieved by means of digital filters, digital delay lines, etc. In 5G MIMO antenna system, two channels share one crystal oscillator, real-time calibration needs to be done when rebooting the system. Based on this problem, a new digital calibration algorithm of integrative transceiver including the initial phase of the crystal oscillator is proposed in this paper. Related tests of antennas and arrays are also carried out.","PeriodicalId":104014,"journal":{"name":"Proceedings of the 4th International Electronics Communication Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125551797","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Proceedings of the 4th International Electronics Communication Conference","authors":"","doi":"10.1145/3560089","DOIUrl":"https://doi.org/10.1145/3560089","url":null,"abstract":"","PeriodicalId":104014,"journal":{"name":"Proceedings of the 4th International Electronics Communication Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126888006","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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