Pub Date : 2017-12-01DOI: 10.1109/PDCAT.2017.00014
Zhigang Lu, Hong Shen
Distributed data aggregation via summation (counting) helped us to learn the insights behind the raw data. However, such computing suffered from a high privacy risk of malicious collusion attacks. That is, the colluding adversaries infer a victim's privacy from the gaps between the aggregation outputs and their source data. Among the solutions against such collusion attacks, Distributed Differential Privacy (DDP) shows a significant effect of privacy preservation. Specifically, a DDP scheme guarantees the global differential privacy (the presence or absence of any data curator barely impacts the aggregation outputs) by ensuring local differential privacy at the end of each data curator. To guarantee an overall privacy performance of a distributed data aggregation system against malicious collusion attacks, part of the existing work on such DDP scheme aim to provide an estimated lower bound of privacy budget for the global differential privacy. However, there are two main problems: low data utility from using a large global function sensitivity; unknown privacy guarantee when the aggregation sensitivity of the whole system is less than the sum of the data curator's aggregation sensitivity. To address these problems while ensuring distributed differential privacy, we provide a new lower bound of privacy budget, which works with an unconditional aggregation sensitivity of the whole distributed system. Moreover, we study the performance of our privacy bound in different scenarios of data updates. Both theoretical and experimental evaluations show that our privacy bound offers better global privacy performance than the existing work.
{"title":"A New Lower Bound of Privacy Budget for Distributed Differential Privacy","authors":"Zhigang Lu, Hong Shen","doi":"10.1109/PDCAT.2017.00014","DOIUrl":"https://doi.org/10.1109/PDCAT.2017.00014","url":null,"abstract":"Distributed data aggregation via summation (counting) helped us to learn the insights behind the raw data. However, such computing suffered from a high privacy risk of malicious collusion attacks. That is, the colluding adversaries infer a victim's privacy from the gaps between the aggregation outputs and their source data. Among the solutions against such collusion attacks, Distributed Differential Privacy (DDP) shows a significant effect of privacy preservation. Specifically, a DDP scheme guarantees the global differential privacy (the presence or absence of any data curator barely impacts the aggregation outputs) by ensuring local differential privacy at the end of each data curator. To guarantee an overall privacy performance of a distributed data aggregation system against malicious collusion attacks, part of the existing work on such DDP scheme aim to provide an estimated lower bound of privacy budget for the global differential privacy. However, there are two main problems: low data utility from using a large global function sensitivity; unknown privacy guarantee when the aggregation sensitivity of the whole system is less than the sum of the data curator's aggregation sensitivity. To address these problems while ensuring distributed differential privacy, we provide a new lower bound of privacy budget, which works with an unconditional aggregation sensitivity of the whole distributed system. Moreover, we study the performance of our privacy bound in different scenarios of data updates. Both theoretical and experimental evaluations show that our privacy bound offers better global privacy performance than the existing work.","PeriodicalId":119197,"journal":{"name":"2017 18th International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124461884","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/PDCAT.2017.00040
H. Nakouri, Mhamed-Ali El-Aroui, M. Limam
Background and foreground separation is the major task in video surveillance system to detect moving or suspicious objects. Robust Principal Component Analysis, whose formulation relies on low-rank plus sparse matrices decomposition, shows an interestingly suitable framework to separate moving objects from the background. The optimization problem is transformed to a sequence of convex programs that minimize the sum of L1-norm and nuclear norm of the two component matrices, which are efficiently resolved by an Augmented Lagrangian Multiplierss based solver. In this paper, we propose two new robust schemas for low rank approximation of numerical matrices. The proposed algorithms allow batch and incremental robust low-rank approximal of matrices used in static and real-time foreground extraction to detect moving objects. Experiments reveal that the proposed method are both deterministic, converge decently and quickly; besides, they achieve an accurate background and foreground separation outcome.
{"title":"Robust Low-Rank Approximation of Images for Background and Foreground Separation","authors":"H. Nakouri, Mhamed-Ali El-Aroui, M. Limam","doi":"10.1109/PDCAT.2017.00040","DOIUrl":"https://doi.org/10.1109/PDCAT.2017.00040","url":null,"abstract":"Background and foreground separation is the major task in video surveillance system to detect moving or suspicious objects. Robust Principal Component Analysis, whose formulation relies on low-rank plus sparse matrices decomposition, shows an interestingly suitable framework to separate moving objects from the background. The optimization problem is transformed to a sequence of convex programs that minimize the sum of L1-norm and nuclear norm of the two component matrices, which are efficiently resolved by an Augmented Lagrangian Multiplierss based solver. In this paper, we propose two new robust schemas for low rank approximation of numerical matrices. The proposed algorithms allow batch and incremental robust low-rank approximal of matrices used in static and real-time foreground extraction to detect moving objects. Experiments reveal that the proposed method are both deterministic, converge decently and quickly; besides, they achieve an accurate background and foreground separation outcome.","PeriodicalId":119197,"journal":{"name":"2017 18th International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122953520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/PDCAT.2017.00039
Boyi Zhang, Xiaolin Xu, Hongwei Xing, Yidong Li
Power demand forecasting plays a very important role in many electricity-required industries, such as modern high-speed railways or urban railways. Accurate forecasting will guarantee that electrical equipments such as electric traction systems for trains work under safe, robust and efficient status. Recently, many studies adopt the learning-based methods to achieve the prediction of power demand. However, most of the studies use the traditional classification or clustering algorithms which may not satisfy the requirements of accuracy and efficiency due to the complex features in smart grid. In this paper, we focus on solving the power demand forecasting problem based on deep learning structures. We first propose a deep learning based framework for power demand forecasting with Deep Belief Network (DBN). Then, we use an algorithm called Adaboost to combine weak learners with strong learners, which can increase the accuracy significantly in real-world scenarios. The prediction of the load status is realized by analyzing the information of historical distribution transformer load, weather, electricity population and some other related information. It is also worth noting that the training process of these DBN networks can be parallel, which effectively shorten the processing time and provide the possible of real-time predicting. Our experiment on real-world data from the electrical company shows results that the deep leaning based methods can increase the accuracy of forecasting and significantly shorten the prediction time.
{"title":"A Deep Learning Based Framework for Power Demand Forecasting with Deep Belief Networks","authors":"Boyi Zhang, Xiaolin Xu, Hongwei Xing, Yidong Li","doi":"10.1109/PDCAT.2017.00039","DOIUrl":"https://doi.org/10.1109/PDCAT.2017.00039","url":null,"abstract":"Power demand forecasting plays a very important role in many electricity-required industries, such as modern high-speed railways or urban railways. Accurate forecasting will guarantee that electrical equipments such as electric traction systems for trains work under safe, robust and efficient status. Recently, many studies adopt the learning-based methods to achieve the prediction of power demand. However, most of the studies use the traditional classification or clustering algorithms which may not satisfy the requirements of accuracy and efficiency due to the complex features in smart grid. In this paper, we focus on solving the power demand forecasting problem based on deep learning structures. We first propose a deep learning based framework for power demand forecasting with Deep Belief Network (DBN). Then, we use an algorithm called Adaboost to combine weak learners with strong learners, which can increase the accuracy significantly in real-world scenarios. The prediction of the load status is realized by analyzing the information of historical distribution transformer load, weather, electricity population and some other related information. It is also worth noting that the training process of these DBN networks can be parallel, which effectively shorten the processing time and provide the possible of real-time predicting. Our experiment on real-world data from the electrical company shows results that the deep leaning based methods can increase the accuracy of forecasting and significantly shorten the prediction time.","PeriodicalId":119197,"journal":{"name":"2017 18th International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129307871","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/PDCAT.2017.00060
Chien-Ping Liu, Ho-Ting Wu, Chia-Chih Chien, Kai-Wei Ke
The Ethernet passive optical network (EPON) is one of the most efficient transmission technologies for broadband access. However, an unregulated transmission could waste energy if an ONU transmits an insufficient or excessive amount of packets in one time cycle on an energy saving EPON network. For an insufficient transmission, it invokes an unnecessary power consumption, since a power saving ONU has to wake up early for transmitting few packets only. For an excessive transmission, it allows an ONU to stay at the active mode for a longer time but to push other ONUs out of transmission cycle. Load regulation enables an energy saving EPON system to provide near constant loading. This paper studies an appropriate threshold for an ONU to switch between active or energy saving modes. Performance results reveal that satisfactory power saving effects can be achieved via proper load regulation applied on both upstream and downstream channels at the cost of the delay performances of low-priority packets.
{"title":"Load Regulation on Energy Saving Mechanisms of EPON Networks","authors":"Chien-Ping Liu, Ho-Ting Wu, Chia-Chih Chien, Kai-Wei Ke","doi":"10.1109/PDCAT.2017.00060","DOIUrl":"https://doi.org/10.1109/PDCAT.2017.00060","url":null,"abstract":"The Ethernet passive optical network (EPON) is one of the most efficient transmission technologies for broadband access. However, an unregulated transmission could waste energy if an ONU transmits an insufficient or excessive amount of packets in one time cycle on an energy saving EPON network. For an insufficient transmission, it invokes an unnecessary power consumption, since a power saving ONU has to wake up early for transmitting few packets only. For an excessive transmission, it allows an ONU to stay at the active mode for a longer time but to push other ONUs out of transmission cycle. Load regulation enables an energy saving EPON system to provide near constant loading. This paper studies an appropriate threshold for an ONU to switch between active or energy saving modes. Performance results reveal that satisfactory power saving effects can be achieved via proper load regulation applied on both upstream and downstream channels at the cost of the delay performances of low-priority packets.","PeriodicalId":119197,"journal":{"name":"2017 18th International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121823741","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/PDCAT.2017.00059
A. Meddeb, Atef Jaballah
Radio Frequency IDentification (RFID) was identified as one of the ten best technologies in the 21st century. This technology is frequently used in different sectors: industrial, agricultural and academic. In RFID networks, readers and tags communicate wirelessly through electromagnetic signals. Due to the optimized tag coverage, multiple readers must be deployed in the same working area, causing reader-to-reader or/and readerto- tag collisions. In addition, the RFID reader is characterized by a maximum number of tags that can read them and a maximum interrogation range. Then the problem of activating the RFID readers and adjusting their interrogation ranges in order to cover the maximum number of tags without collisions is one of hot spot researches in RFID networks. This problem is known as the Reader Coverage Collision Avoidance Arrangement (RCCAA) problem. In the literature, an algorithm called the Maximum-Weight-Independent-Set-Based Algorithm (MWISBA) was put forward to solve the RCCAA problem. In this algorithm, only the interrogation ranges of readers where adjusted. The interference range was not taken into account. Thus, a readerto- reader collision could occur if a reader interrogated a tag located in the overlap area of its interrogation area with the interference area of another reader. To fill in this gap, we propose an improvement of the MWISBA called the MWISBAII which is able to solve the RCCAA problem avoiding all types of collisions. The experimental results show the superiority of our algorithm compared with the state-of-the-art solutions.
{"title":"Algorithm for Readers Arrangement without Collision in RFID Networks","authors":"A. Meddeb, Atef Jaballah","doi":"10.1109/PDCAT.2017.00059","DOIUrl":"https://doi.org/10.1109/PDCAT.2017.00059","url":null,"abstract":"Radio Frequency IDentification (RFID) was identified as one of the ten best technologies in the 21st century. This technology is frequently used in different sectors: industrial, agricultural and academic. In RFID networks, readers and tags communicate wirelessly through electromagnetic signals. Due to the optimized tag coverage, multiple readers must be deployed in the same working area, causing reader-to-reader or/and readerto- tag collisions. In addition, the RFID reader is characterized by a maximum number of tags that can read them and a maximum interrogation range. Then the problem of activating the RFID readers and adjusting their interrogation ranges in order to cover the maximum number of tags without collisions is one of hot spot researches in RFID networks. This problem is known as the Reader Coverage Collision Avoidance Arrangement (RCCAA) problem. In the literature, an algorithm called the Maximum-Weight-Independent-Set-Based Algorithm (MWISBA) was put forward to solve the RCCAA problem. In this algorithm, only the interrogation ranges of readers where adjusted. The interference range was not taken into account. Thus, a readerto- reader collision could occur if a reader interrogated a tag located in the overlap area of its interrogation area with the interference area of another reader. To fill in this gap, we propose an improvement of the MWISBA called the MWISBAII which is able to solve the RCCAA problem avoiding all types of collisions. The experimental results show the superiority of our algorithm compared with the state-of-the-art solutions.","PeriodicalId":119197,"journal":{"name":"2017 18th International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT)","volume":"29 11","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120972737","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/PDCAT.2017.00052
Yao Hu, T. Kudoh, M. Koibuchi
Circuit switching is a way to minimize network latency and maximize network bandwidth when a limited number of source-and-destination pairs exchange messages which are predictable. Although there are a large number of studies of optical circuit switching (OCS) on HPC systems and datacenters, it is still not mature. In this context, we explore the use of electrical circuit switching (ECS) for the low-latency purpose on HPC systems and datacenters. ECS has the same link bandwidth as existing electrical packet switched networks, and inherits quick update of input-and-output connections from electrical switches. We develop a network topology generator for ECS to minimize the number of time slots optimized to target applications whose traffic patterns are predictable. By performing a quantitative discrete-event simulation, we present that an ideal ECS network outperforms counterpart EPS networks. Evaluation results show that the minimum necessary number of slots (MNNS) can be reduced to a small number in a generated topology while keeping resource amount less than that in a standard mesh network.
{"title":"A Case of Electrical Circuit Switched Interconnection Network for Parallel Computers","authors":"Yao Hu, T. Kudoh, M. Koibuchi","doi":"10.1109/PDCAT.2017.00052","DOIUrl":"https://doi.org/10.1109/PDCAT.2017.00052","url":null,"abstract":"Circuit switching is a way to minimize network latency and maximize network bandwidth when a limited number of source-and-destination pairs exchange messages which are predictable. Although there are a large number of studies of optical circuit switching (OCS) on HPC systems and datacenters, it is still not mature. In this context, we explore the use of electrical circuit switching (ECS) for the low-latency purpose on HPC systems and datacenters. ECS has the same link bandwidth as existing electrical packet switched networks, and inherits quick update of input-and-output connections from electrical switches. We develop a network topology generator for ECS to minimize the number of time slots optimized to target applications whose traffic patterns are predictable. By performing a quantitative discrete-event simulation, we present that an ideal ECS network outperforms counterpart EPS networks. Evaluation results show that the minimum necessary number of slots (MNNS) can be reduced to a small number in a generated topology while keeping resource amount less than that in a standard mesh network.","PeriodicalId":119197,"journal":{"name":"2017 18th International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126853209","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/PDCAT.2017.00017
Song Liu, Xiao Xie, Yuanzhen Cui, Weiguo Wu
Task scheduling can improve the performance of parallel execution through optimizing the utilization of on-chip computing resources, and thus it has been widely studied. Most of the previous work uses data access locality to predict cache behaviors for task scheduling, but usually suffering accuracy and computational time complexity issues. This paper proposes an efficient task assignment algorithm to minimize the contention for shared caches on multi-core processors among parallel independent process level tasks. The proposed algorithm leverages the property of footprint to approximately estimate the locality parameter of parallel tasks, choosing the best grouping of tasks with minimum locality value in a quick way for task assignment. The calculation time is therefore significantly reduced and the algorithm complexity is O(nlog2n). Meanwhile, the algorithm accuracy is very high. On an Intel 8 cores dual-processor system, the experimental results show that the task assignment algorithm achieves over 99% of the actual optimal performance on average and outperforms the default Linux task scheduling method by an average of over 5% for two sets of different parallel tasks.
{"title":"An Efficient Locality-Aware Task Assignment Algorithm for Minimizing Shared Cache Contention","authors":"Song Liu, Xiao Xie, Yuanzhen Cui, Weiguo Wu","doi":"10.1109/PDCAT.2017.00017","DOIUrl":"https://doi.org/10.1109/PDCAT.2017.00017","url":null,"abstract":"Task scheduling can improve the performance of parallel execution through optimizing the utilization of on-chip computing resources, and thus it has been widely studied. Most of the previous work uses data access locality to predict cache behaviors for task scheduling, but usually suffering accuracy and computational time complexity issues. This paper proposes an efficient task assignment algorithm to minimize the contention for shared caches on multi-core processors among parallel independent process level tasks. The proposed algorithm leverages the property of footprint to approximately estimate the locality parameter of parallel tasks, choosing the best grouping of tasks with minimum locality value in a quick way for task assignment. The calculation time is therefore significantly reduced and the algorithm complexity is O(nlog2n). Meanwhile, the algorithm accuracy is very high. On an Intel 8 cores dual-processor system, the experimental results show that the task assignment algorithm achieves over 99% of the actual optimal performance on average and outperforms the default Linux task scheduling method by an average of over 5% for two sets of different parallel tasks.","PeriodicalId":119197,"journal":{"name":"2017 18th International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122212338","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/PDCAT.2017.00058
Shang-Chih Ma, Chang-Hong Lee, Hong Chang
Using the multilevel concatenation, long block codes can be constructed from shorter component codes, resulting in much less decoding complexity. The component codes can also be constructed from multilevel concatenation so that a hierarchical multilevel concatenated structure is built. The decoding complexity of the hierarchical scheme can be further decreased.
{"title":"Multilevel Concatenated Codes with Parallel Construction","authors":"Shang-Chih Ma, Chang-Hong Lee, Hong Chang","doi":"10.1109/PDCAT.2017.00058","DOIUrl":"https://doi.org/10.1109/PDCAT.2017.00058","url":null,"abstract":"Using the multilevel concatenation, long block codes can be constructed from shorter component codes, resulting in much less decoding complexity. The component codes can also be constructed from multilevel concatenation so that a hierarchical multilevel concatenated structure is built. The decoding complexity of the hierarchical scheme can be further decreased.","PeriodicalId":119197,"journal":{"name":"2017 18th International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128608872","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/PDCAT.2017.00080
Geoffrey Phi C. Tran, J. Walters, S. Crago
Large-scale data processing paradigms, such as stream processing, are widespread in academic and corporate workloads. These environments are commonly subject to real-time requirements, such as latency and throughput, and resiliency requirements to node or network failures. These requirements have generally been approached as separate problems. Intermittent timing delays due to factors such as garbage collection can further complicate the management of the stream processing workload. Insufficient resource allocations can also lead to poor performance. Currently, tuning these applications is done manually. We show that improper configuration can greatly affect performance. It is reported that even 100ms of increased latency in online sales platforms can potentially result in lower sales. In this paper we propose Dynamo, a framework and monitor that implements a methodology for addressing both the performance and timing error problems by increasing the resiliency of stream processing frameworks to timing delays. Dynamo autonomously adjusts the resource allocation by using a performance profile that is generated through application profiling. Dynamo partitions an application’s allocated resources into active and passive partitions that are dynamically adjusted to match an application’s multi-modal behavior. The distribution of resources determines the amount of computation that Dynamo can duplicate and process redundantly, thereby reducing the probability of timing errors that affect a tuple’s total execution time. In our experiments, we observed improvements in the number of tuples with missed deadlines. Our results show that Dynamo is able to consistently improve the resiliency to timing errors over a number of differing occurrence rates. Furthermore, we show that the improvement in the number of missed deadlines increases with the amount of spare resources, with a 71.40% reduction in the best case.
{"title":"Dynamically Improving Resiliency to Timing Errors for Stream Processing Workloads","authors":"Geoffrey Phi C. Tran, J. Walters, S. Crago","doi":"10.1109/PDCAT.2017.00080","DOIUrl":"https://doi.org/10.1109/PDCAT.2017.00080","url":null,"abstract":"Large-scale data processing paradigms, such as stream processing, are widespread in academic and corporate workloads. These environments are commonly subject to real-time requirements, such as latency and throughput, and resiliency requirements to node or network failures. These requirements have generally been approached as separate problems. Intermittent timing delays due to factors such as garbage collection can further complicate the management of the stream processing workload. Insufficient resource allocations can also lead to poor performance. Currently, tuning these applications is done manually. We show that improper configuration can greatly affect performance. It is reported that even 100ms of increased latency in online sales platforms can potentially result in lower sales. In this paper we propose Dynamo, a framework and monitor that implements a methodology for addressing both the performance and timing error problems by increasing the resiliency of stream processing frameworks to timing delays. Dynamo autonomously adjusts the resource allocation by using a performance profile that is generated through application profiling. Dynamo partitions an application’s allocated resources into active and passive partitions that are dynamically adjusted to match an application’s multi-modal behavior. The distribution of resources determines the amount of computation that Dynamo can duplicate and process redundantly, thereby reducing the probability of timing errors that affect a tuple’s total execution time. In our experiments, we observed improvements in the number of tuples with missed deadlines. Our results show that Dynamo is able to consistently improve the resiliency to timing errors over a number of differing occurrence rates. Furthermore, we show that the improvement in the number of missed deadlines increases with the amount of spare resources, with a 71.40% reduction in the best case.","PeriodicalId":119197,"journal":{"name":"2017 18th International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121403125","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/PDCAT.2017.00062
Qi Zeng, R. Jha, J. Peir
Spin-Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) is a promising memory technology, which has high density, low leakage power, fast read speed, and non-volatility, and is suitable for on-chip last-level caches with large capacity. Recently, Multi-Level Cell (MLC) STT-MRAM records two bits in a single cell to further improve the density for building even bigger on-chip caches. However, MLC worsens write energy consumption and endurance. The magnetization directions of its hard and soft domains cannot be flipped to two opposite directions simultaneously, which leads to the two-step transition problem for certain combinations of updating the 2-bit value. The two-step transition incurs extra flip in the soft domains, consume high energy, and negatively impact the life time of MLC STT-MRAM. In this paper, we present a new dimension to alleviate high write energy issue in MLC. During cache replacement, we select among a few candidates blocks close to the LRU position for replacement to lower the write energy with minimum impact on cache performance. We propose a novel block content encoding method to represent whole block with a few bits and use the encoding bits for better cache replacement. After picking the replacement block, we apply intelligent remap of each updated 2-bit values to further reduce the write energy. Performance evaluation results show this content-aware cache replacement can lower the write energy by 26.1% in comparison with MLC caches using regular Pseudo-LRU replacement polic
{"title":"Towards Energy-Efficient Multi-Level Cell STT-MRAM Caches with Content Awareness","authors":"Qi Zeng, R. Jha, J. Peir","doi":"10.1109/PDCAT.2017.00062","DOIUrl":"https://doi.org/10.1109/PDCAT.2017.00062","url":null,"abstract":"Spin-Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) is a promising memory technology, which has high density, low leakage power, fast read speed, and non-volatility, and is suitable for on-chip last-level caches with large capacity. Recently, Multi-Level Cell (MLC) STT-MRAM records two bits in a single cell to further improve the density for building even bigger on-chip caches. However, MLC worsens write energy consumption and endurance. The magnetization directions of its hard and soft domains cannot be flipped to two opposite directions simultaneously, which leads to the two-step transition problem for certain combinations of updating the 2-bit value. The two-step transition incurs extra flip in the soft domains, consume high energy, and negatively impact the life time of MLC STT-MRAM. In this paper, we present a new dimension to alleviate high write energy issue in MLC. During cache replacement, we select among a few candidates blocks close to the LRU position for replacement to lower the write energy with minimum impact on cache performance. We propose a novel block content encoding method to represent whole block with a few bits and use the encoding bits for better cache replacement. After picking the replacement block, we apply intelligent remap of each updated 2-bit values to further reduce the write energy. Performance evaluation results show this content-aware cache replacement can lower the write energy by 26.1% in comparison with MLC caches using regular Pseudo-LRU replacement polic","PeriodicalId":119197,"journal":{"name":"2017 18th International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127142821","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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