Pub Date : 2017-11-13DOI: 10.1109/ICCAD.2017.8203834
Zhanwei Zhong, Zipeng Li, K. Chakrabarty
Digital microfluidic biochips (DMFBs) are being increasingly used in biochemistry labs for automating bioassays. However, traditional DMFBs suffer from some key shortcomings: 1) inability to vary droplet volume in a flexible manner; 2) difficulty of integrating on-chip sensors; 3) the need for special fabrication processes. To overcome these problems, DMFBs based on micro-electrode-dot-array (MEDA) have recently be-en proposed. However, errors are likely to occur on a MEDA DMFB due to chip defects and the unpredictability inherent to biochemical experiments. We present fine-grained error-recovery solutions for MEDA by exploiting real-time sensing and advanced MEDA-specific droplet operations. The proposed methods rely on adaptive droplet-aliquot operations and predictive analysis of mixing. Experimental results on three representative benchmarks demonstrate the efficiency of the proposed error-recovery strategy.
{"title":"Adaptive error recovery in MEDA biochips based on droplet-aliquot operations and predictive analysis","authors":"Zhanwei Zhong, Zipeng Li, K. Chakrabarty","doi":"10.1109/ICCAD.2017.8203834","DOIUrl":"https://doi.org/10.1109/ICCAD.2017.8203834","url":null,"abstract":"Digital microfluidic biochips (DMFBs) are being increasingly used in biochemistry labs for automating bioassays. However, traditional DMFBs suffer from some key shortcomings: 1) inability to vary droplet volume in a flexible manner; 2) difficulty of integrating on-chip sensors; 3) the need for special fabrication processes. To overcome these problems, DMFBs based on micro-electrode-dot-array (MEDA) have recently be-en proposed. However, errors are likely to occur on a MEDA DMFB due to chip defects and the unpredictability inherent to biochemical experiments. We present fine-grained error-recovery solutions for MEDA by exploiting real-time sensing and advanced MEDA-specific droplet operations. The proposed methods rely on adaptive droplet-aliquot operations and predictive analysis of mixing. Experimental results on three representative benchmarks demonstrate the efficiency of the proposed error-recovery strategy.","PeriodicalId":126686,"journal":{"name":"2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"261 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134245260","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-13DOI: 10.1109/ICCAD.2017.8203825
F. Merrikh-Bayat, M. Prezioso, B. Chakrabarti, I. Kataeva, D. Strukov
We experimentally demonstrate classification of 4×4 binary images into 4 classes, using a 3-layer mixed-signal neuromorphic network (“MLP perceptron”), based on two passive 20×20 memristive crossbar arrays, board-integrated with discrete CMOS components. The network features 10 hidden-layer and 4 output-layer analog CMOS neurons and 428 metal-oxide memristors, i.e. is almost an order of magnitude more complex than any previously reported functional passive (0T1R) memristor classifier. Moreover, the inference operation of this classifier is performed entirely in the integrated hardware. To deal with larger crossbar arrays, we have developed a semiautomatic approach to their forming and testing, and compared several memristor training schemes for coping with imperfect behavior of these devices, as well as with variability of analog CMOS neurons. The effectiveness of the proposed schemes for defect and variation tolerance was verified experimentally using the implemented network and, additionally, by modeling the operation of a larger network, with 300 hidden-layer neurons, on the MNIST benchmark. Finally, we propose a simple modification of the implemented memristor-based vector-by-matrix multiplier to allow its operation in a wider temperature range.
{"title":"Memristor-based perceptron classifier: Increasing complexity and coping with imperfect hardware","authors":"F. Merrikh-Bayat, M. Prezioso, B. Chakrabarti, I. Kataeva, D. Strukov","doi":"10.1109/ICCAD.2017.8203825","DOIUrl":"https://doi.org/10.1109/ICCAD.2017.8203825","url":null,"abstract":"We experimentally demonstrate classification of 4×4 binary images into 4 classes, using a 3-layer mixed-signal neuromorphic network (“MLP perceptron”), based on two passive 20×20 memristive crossbar arrays, board-integrated with discrete CMOS components. The network features 10 hidden-layer and 4 output-layer analog CMOS neurons and 428 metal-oxide memristors, i.e. is almost an order of magnitude more complex than any previously reported functional passive (0T1R) memristor classifier. Moreover, the inference operation of this classifier is performed entirely in the integrated hardware. To deal with larger crossbar arrays, we have developed a semiautomatic approach to their forming and testing, and compared several memristor training schemes for coping with imperfect behavior of these devices, as well as with variability of analog CMOS neurons. The effectiveness of the proposed schemes for defect and variation tolerance was verified experimentally using the implemented network and, additionally, by modeling the operation of a larger network, with 300 hidden-layer neurons, on the MNIST benchmark. Finally, we propose a simple modification of the implemented memristor-based vector-by-matrix multiplier to allow its operation in a wider temperature range.","PeriodicalId":126686,"journal":{"name":"2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114864545","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-13DOI: 10.1109/ICCAD.2017.8203761
Yen-Yi Wu, Yao-Wen Chang
Mixed-cell-height circuits have prevailed in advanced technology to address various design needs. Along with device scaling, complex minimum-implant-area (MIA) constraints arise as an emerging challenge in modern circuit designs, adding to the difficulties in mixed-cell-height placement. Existing MIA-aware detailed placement with single-row-height standard cells is insufficient for mixed-cell-height designs: (1) filler insertion, typically used to resolve MIA violations, might incur unaffordable area and wirelength overheads, and (2) mixed-height cell perturbation could cause severe inter-row MIA violations. This paper presents the first work to address the mixed-cell-height detailed placement problem considering both intra- and inter-row MIA constraints. We first fix intra-row violations by clustering violating mixed-height cells of the same threshold voltage, and then perturb each cluster to obtain a desired cell permutation by applying an efficient, optimal dynamic-programming-based algorithm for a special case and Algorithm DLX for general ones, where a provably constant performance ratio for a mixed-cell-height reshaping problem can be achieved. With a network-flow-based formulation, remaining violating cells are placed in appropriate filler-insertion positions to fix cell violations and minimize area. After performing mixed-cell-height detailed placement, we finally fix inter-row violations by shifting violating cells in minimum displacement. Compared with a filler insertion method and a greedy clustering approach, experimental results show that our proposed algorithm can resolve all MIA violations with smallest HPWL and area overheads in reasonable running time.
{"title":"Mixed-cell-height detailed placement considering complex minimum-implant-area constraints","authors":"Yen-Yi Wu, Yao-Wen Chang","doi":"10.1109/ICCAD.2017.8203761","DOIUrl":"https://doi.org/10.1109/ICCAD.2017.8203761","url":null,"abstract":"Mixed-cell-height circuits have prevailed in advanced technology to address various design needs. Along with device scaling, complex minimum-implant-area (MIA) constraints arise as an emerging challenge in modern circuit designs, adding to the difficulties in mixed-cell-height placement. Existing MIA-aware detailed placement with single-row-height standard cells is insufficient for mixed-cell-height designs: (1) filler insertion, typically used to resolve MIA violations, might incur unaffordable area and wirelength overheads, and (2) mixed-height cell perturbation could cause severe inter-row MIA violations. This paper presents the first work to address the mixed-cell-height detailed placement problem considering both intra- and inter-row MIA constraints. We first fix intra-row violations by clustering violating mixed-height cells of the same threshold voltage, and then perturb each cluster to obtain a desired cell permutation by applying an efficient, optimal dynamic-programming-based algorithm for a special case and Algorithm DLX for general ones, where a provably constant performance ratio for a mixed-cell-height reshaping problem can be achieved. With a network-flow-based formulation, remaining violating cells are placed in appropriate filler-insertion positions to fix cell violations and minimize area. After performing mixed-cell-height detailed placement, we finally fix inter-row violations by shifting violating cells in minimum displacement. Compared with a filler insertion method and a greedy clustering approach, experimental results show that our proposed algorithm can resolve all MIA violations with smallest HPWL and area overheads in reasonable running time.","PeriodicalId":126686,"journal":{"name":"2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121906542","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-13DOI: 10.1109/ICCAD.2017.8203792
Moslem Didehban, Aviral Shrivastava, Sai Ram Dheeraj Lokam
Soft errors are considered as the main reliability challenge for sub-nanoscale microprocessors. Software-level soft error resilience schemes are desirable because they require no hardware modifications and their protection can be tuned based on the application requirements. However, existing software-level error tolerant schemes do not provide high-level of protection. In this work, we present NEMESIS — a compiler-level fine-grain soft error detection, diagnosis and recovery technique that can provide high degree of error-resiliency. NEMESIS runs three versions of computations and detects soft errors by checking the results of all memory write and branch operations. In the case of mismatch, NEMESIS recovery routine reverts the effect of error from the architectural state of the program and program resumes its normal execution. Our extensive μ-architectural-level fault injection experiments results show that NEMESIS transformation is able to detect all soft errors and recover from 97% of detected errors.
{"title":"NEMESIS: A software approach for computing in presence of soft errors","authors":"Moslem Didehban, Aviral Shrivastava, Sai Ram Dheeraj Lokam","doi":"10.1109/ICCAD.2017.8203792","DOIUrl":"https://doi.org/10.1109/ICCAD.2017.8203792","url":null,"abstract":"Soft errors are considered as the main reliability challenge for sub-nanoscale microprocessors. Software-level soft error resilience schemes are desirable because they require no hardware modifications and their protection can be tuned based on the application requirements. However, existing software-level error tolerant schemes do not provide high-level of protection. In this work, we present NEMESIS — a compiler-level fine-grain soft error detection, diagnosis and recovery technique that can provide high degree of error-resiliency. NEMESIS runs three versions of computations and detects soft errors by checking the results of all memory write and branch operations. In the case of mismatch, NEMESIS recovery routine reverts the effect of error from the architectural state of the program and program resumes its normal execution. Our extensive μ-architectural-level fault injection experiments results show that NEMESIS transformation is able to detect all soft errors and recover from 97% of detected errors.","PeriodicalId":126686,"journal":{"name":"2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130935080","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-13DOI: 10.1109/ICCAD.2017.8203836
Amar Shrestha, Khadeer Ahmed, Yanzhi Wang, D. Widemann, A. Moody, B. V. Essen, Qinru Qiu
Low-power brain-inspired hardware systems have gained significant traction in recent years. They offer high energy efficiency and massive parallelism due to the distributed and asynchronous nature of neural computation through low-energy spikes. One such platform is the IBM TrueNorth Neurosynaptic System. Recently TrueNorth compatible representation learning algorithms have emerged, achieving close to state-of-the-art performance in various datasets. An exception is its application in temporal sequence processing models such as recurrent neural networks (RNNs), which is still at the proof of concept level. This is partly due to the hardware constraints in connectivity and syn-aptic weight resolution, and the inherent difficulty in capturing temporal dynamics of an RNN using spiking neurons. This work presents a design flow that overcomes the aforementioned difficulties and maps a special case of recurrent networks called Long Short-Term Memory (LSTM) onto a spike-based platform. The framework is built on top of various approximation techniques, weight and activation discretization, spiking neuron sub-circuits that implements the complex gating mechanisms and a store-and-release technique to enable neuron synchronization and faithful storage. While many of the techniques can be applied to map LSTM to any SNN simulator/emulator, here we demonstrate this approach on the TrueNorth chip adhering to its constraints. Two benchmark LSTM applications, parity check and Extended Reber Grammar, are evaluated and their accuracy, energy and speed tradeoffs are analyzed.
{"title":"A spike-based long short-term memory on a neurosynaptic processor","authors":"Amar Shrestha, Khadeer Ahmed, Yanzhi Wang, D. Widemann, A. Moody, B. V. Essen, Qinru Qiu","doi":"10.1109/ICCAD.2017.8203836","DOIUrl":"https://doi.org/10.1109/ICCAD.2017.8203836","url":null,"abstract":"Low-power brain-inspired hardware systems have gained significant traction in recent years. They offer high energy efficiency and massive parallelism due to the distributed and asynchronous nature of neural computation through low-energy spikes. One such platform is the IBM TrueNorth Neurosynaptic System. Recently TrueNorth compatible representation learning algorithms have emerged, achieving close to state-of-the-art performance in various datasets. An exception is its application in temporal sequence processing models such as recurrent neural networks (RNNs), which is still at the proof of concept level. This is partly due to the hardware constraints in connectivity and syn-aptic weight resolution, and the inherent difficulty in capturing temporal dynamics of an RNN using spiking neurons. This work presents a design flow that overcomes the aforementioned difficulties and maps a special case of recurrent networks called Long Short-Term Memory (LSTM) onto a spike-based platform. The framework is built on top of various approximation techniques, weight and activation discretization, spiking neuron sub-circuits that implements the complex gating mechanisms and a store-and-release technique to enable neuron synchronization and faithful storage. While many of the techniques can be applied to map LSTM to any SNN simulator/emulator, here we demonstrate this approach on the TrueNorth chip adhering to its constraints. Two benchmark LSTM applications, parity check and Extended Reber Grammar, are evaluated and their accuracy, energy and speed tradeoffs are analyzed.","PeriodicalId":126686,"journal":{"name":"2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115943220","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-13DOI: 10.1109/ICCAD.2017.8203754
Yun Liang, Xiuhong Li, Xiaolong Xie
Graphics Processing Units (GPUs) computing has become ubiquitous for embedded system, evidenced by its wide adoption for various general purpose applications. As more and more applications are accelerated by GPUs, multi-tasking scenario starts to emerge. Multi-tasking allows multiple applications to simultaneously execute on the same GPU and share the resource. This brings new challenges due to the contention among the different applications for the shared resources such as caches. However, the caches on GPUs are difficult to use. If used inappropriately, it may hurt the performance instead of improving it. In this paper, we propose to use cache partitioning together with cache bypassing as the shared cache management mechanism for multi-tasking on GPUs. The combined approach aims to reduce the interference among the tasks and preserve the locality for each task. However, the interplay among the cache partitioning and bypassing brings greater challenges. On one hand, the partitioned cache space to each task affects its cache bypassing decision. On the other hand, cache bypassing affects the cache capacity required for each task. To address this, we propose a two-step approach. First, we use cache partitioning to assign dedicated cache space to each task to reduce the interference among the tasks. During this process, we compare cache partitioning with coarse-grained cache bypassing. Then, we use fine-grained cache bypassing to selectively bypass certain data requests and threads for each task. We explore different cache partitioning and bypassing designs and demonstrate the potential benefits of this approach. Experiments using a wide range of applications demonstrate that our technique improves the overall system throughput by 52% on average compared to the default multi-tasking solution on GPUs.
{"title":"Exploring cache bypassing and partitioning for multi-tasking on GPUs","authors":"Yun Liang, Xiuhong Li, Xiaolong Xie","doi":"10.1109/ICCAD.2017.8203754","DOIUrl":"https://doi.org/10.1109/ICCAD.2017.8203754","url":null,"abstract":"Graphics Processing Units (GPUs) computing has become ubiquitous for embedded system, evidenced by its wide adoption for various general purpose applications. As more and more applications are accelerated by GPUs, multi-tasking scenario starts to emerge. Multi-tasking allows multiple applications to simultaneously execute on the same GPU and share the resource. This brings new challenges due to the contention among the different applications for the shared resources such as caches. However, the caches on GPUs are difficult to use. If used inappropriately, it may hurt the performance instead of improving it. In this paper, we propose to use cache partitioning together with cache bypassing as the shared cache management mechanism for multi-tasking on GPUs. The combined approach aims to reduce the interference among the tasks and preserve the locality for each task. However, the interplay among the cache partitioning and bypassing brings greater challenges. On one hand, the partitioned cache space to each task affects its cache bypassing decision. On the other hand, cache bypassing affects the cache capacity required for each task. To address this, we propose a two-step approach. First, we use cache partitioning to assign dedicated cache space to each task to reduce the interference among the tasks. During this process, we compare cache partitioning with coarse-grained cache bypassing. Then, we use fine-grained cache bypassing to selectively bypass certain data requests and threads for each task. We explore different cache partitioning and bypassing designs and demonstrate the potential benefits of this approach. Experiments using a wide range of applications demonstrate that our technique improves the overall system throughput by 52% on average compared to the default multi-tasking solution on GPUs.","PeriodicalId":126686,"journal":{"name":"2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"230 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126684519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-13DOI: 10.1109/ICCAD.2017.8203830
Hari Cherupalli, J. Sartori
As the overheads for ensuring the correctness of electronic designs continue to increase with continued technology scaling and increased variability, better-than-worst-case (BTWC) design has gained significant attention. Many BTWC design techniques utilize dynamic timing and activity information for design analysis and optimization. These techniques rely on path-based analysis that enumerates the exercised paths in a design as targets for analysis and optimization. However, path-based dynamic analysis techniques are not scalable and cannot be used to analyze full processors and full applications. On the other hand, graph-based techniques like those that form the foundational building blocks of electronic design automation tools are scalable and can efficiently analyze large designs. In this paper, we extend graph-based analysis to provide the fundamental dynamic analysis tools necessary for BTWC design, analysis, and optimization. Specifically, we present scalable graph-based techniques to report the N-worst exercised paths in a design for three metrics — timing criticality (slack), activity (toggle count), and activity subject to delay constraints. Compared to existing path-based techniques, our scalable dynamic analysis techniques improve average performance by 977 x, 163 x, and 113 x, respectively, and enable scalable analysis for a full processor design running full applications.
{"title":"Scalable N-worst algorithms for dynamic timing and activity analysis","authors":"Hari Cherupalli, J. Sartori","doi":"10.1109/ICCAD.2017.8203830","DOIUrl":"https://doi.org/10.1109/ICCAD.2017.8203830","url":null,"abstract":"As the overheads for ensuring the correctness of electronic designs continue to increase with continued technology scaling and increased variability, better-than-worst-case (BTWC) design has gained significant attention. Many BTWC design techniques utilize dynamic timing and activity information for design analysis and optimization. These techniques rely on path-based analysis that enumerates the exercised paths in a design as targets for analysis and optimization. However, path-based dynamic analysis techniques are not scalable and cannot be used to analyze full processors and full applications. On the other hand, graph-based techniques like those that form the foundational building blocks of electronic design automation tools are scalable and can efficiently analyze large designs. In this paper, we extend graph-based analysis to provide the fundamental dynamic analysis tools necessary for BTWC design, analysis, and optimization. Specifically, we present scalable graph-based techniques to report the N-worst exercised paths in a design for three metrics — timing criticality (slack), activity (toggle count), and activity subject to delay constraints. Compared to existing path-based techniques, our scalable dynamic analysis techniques improve average performance by 977 x, 163 x, and 113 x, respectively, and enable scalable analysis for a full processor design running full applications.","PeriodicalId":126686,"journal":{"name":"2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127402322","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-13DOI: 10.1109/ICCAD.2017.8203886
A. Nardi, A. Armato
Safety-critical automotive applications have stringent demands for functional safety and reliability. Traditionally, functional safety requirements have been managed by car manufacturers and system providers. However, with the increasing complexity of electronics involved, the responsibility of addressing functional safety is now propagating through the supply chain to semiconductor companies and design tool providers. This paper introduces some basic concepts of functional safety analysis and optimization and shows the bridge with the tradition design flow. Considerations are presented on how design methodologies are capturing and addressing the new safety metrics.
{"title":"Functional safety methodologies for automotive applications","authors":"A. Nardi, A. Armato","doi":"10.1109/ICCAD.2017.8203886","DOIUrl":"https://doi.org/10.1109/ICCAD.2017.8203886","url":null,"abstract":"Safety-critical automotive applications have stringent demands for functional safety and reliability. Traditionally, functional safety requirements have been managed by car manufacturers and system providers. However, with the increasing complexity of electronics involved, the responsibility of addressing functional safety is now propagating through the supply chain to semiconductor companies and design tool providers. This paper introduces some basic concepts of functional safety analysis and optimization and shows the bridge with the tradition design flow. Considerations are presented on how design methodologies are capturing and addressing the new safety metrics.","PeriodicalId":126686,"journal":{"name":"2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130976831","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-13DOI: 10.1109/ICCAD.2017.8203820
M. Woo, Seungwon Kim, Seokhyeong Kang
Layout pattern classification has been recently utilized in IC design. It clusters hotspot patterns for design-space analysis or yield optimization. In pattern classification, an optimal clustering is essential, as well as its runtime and accuracy. Within the research-oriented infrastructure used in the ICCAD 2016 contest, we have developed a fast metaheuristic for the pattern classification that utilizes the Greedy Randomized Adaptive Search Procedure (GRASP). Our proposed metaheuristic outperforms the best-reported results on all of the ICCAD 2016 benchmarks. In addition, we achieve up to a 50% cluster count reduction, and improve a runtime significantly compared to a commercial EDA tool provided in the ICCAD 2016 contest [1].
{"title":"GRASP based metaheuristics for layout pattern classification","authors":"M. Woo, Seungwon Kim, Seokhyeong Kang","doi":"10.1109/ICCAD.2017.8203820","DOIUrl":"https://doi.org/10.1109/ICCAD.2017.8203820","url":null,"abstract":"Layout pattern classification has been recently utilized in IC design. It clusters hotspot patterns for design-space analysis or yield optimization. In pattern classification, an optimal clustering is essential, as well as its runtime and accuracy. Within the research-oriented infrastructure used in the ICCAD 2016 contest, we have developed a fast metaheuristic for the pattern classification that utilizes the Greedy Randomized Adaptive Search Procedure (GRASP). Our proposed metaheuristic outperforms the best-reported results on all of the ICCAD 2016 benchmarks. In addition, we achieve up to a 50% cluster count reduction, and improve a runtime significantly compared to a commercial EDA tool provided in the ICCAD 2016 contest [1].","PeriodicalId":126686,"journal":{"name":"2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"457 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131433063","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-13DOI: 10.1109/ICCAD.2017.8203815
Bi Wu, Yuanqing Cheng, Pengcheng Dai, Jianlei Yang, Youguang Zhang, Dijun Liu, Y. Wang, Weisheng Zhao
As the speed gap of the modern processor and the off-chip main memory enlarges, on-chip cache capacity increases to sustain the performance scaling. As a result, the cache power occupies a large portion of the total power budget. STT-MRAM (Spin Transfer Torque Magnetic Memory) is proposed as a promising solution for the low power cache design due to its high integration density and ultra-low leakage. Nevertheless, the high write power and latency of STT-MRAM become new barriers for the commercialization of this emerging technology. In this paper, we investigate the thermal effect on the access performance of STT-MRAM and observe that the temperature can affect the write delay and energy significantly. Then, we explore the NUCA (Non-Uniform Cache Access) design of the CMPs (Chip-Multi-Processors)with STT-MRAM based LLC (Last Level Cache). A thermal aware data migration policy, called “Thermosiphon”, which takes advantage of the thermal property of STT-MRAM, is proposed to reduce the LLC write energy. This policy splits the LLC into different regions based on the thermal distribution and adaptively migrate write intensive data considering the temperature gradient among different thermal regions. Compared to the conventional NUCA design, our proposed design can save 22.5% write energy with negligible hardware overhead.
随着现代处理器和片外主存储器的速度差距的扩大，片上缓存容量增加以维持性能扩展。因此，缓存功率占用了总功率预算的很大一部分。STT-MRAM (Spin Transfer Torque Magnetic Memory，自旋传递转矩磁记忆体)由于其高集成度和超低泄漏，被认为是低功耗高速缓存设计的一个很有前途的解决方案。然而，STT-MRAM的高写入功率和延迟成为这一新兴技术商业化的新障碍。本文研究了热效应对STT-MRAM存取性能的影响，发现温度会显著影响写入延迟和能量。然后，我们探讨了基于STT-MRAM的LLC(最后一级缓存)的cmp (Chip-Multi-Processors)的NUCA (Non-Uniform Cache Access)设计。利用STT-MRAM的热特性，提出了一种热感知数据迁移策略，称为“热虹吸”，以降低LLC写入能量。该策略根据热分布将LLC划分为不同的区域，并考虑不同热区域之间的温度梯度自适应迁移写密集型数据。与传统的NUCA设计相比，我们提出的设计可以节省22.5%的写入能量，而硬件开销可以忽略不计。
{"title":"Thermosiphon: A thermal aware NUCA architecture for write energy reduction of the STT-MRAM based LLCs","authors":"Bi Wu, Yuanqing Cheng, Pengcheng Dai, Jianlei Yang, Youguang Zhang, Dijun Liu, Y. Wang, Weisheng Zhao","doi":"10.1109/ICCAD.2017.8203815","DOIUrl":"https://doi.org/10.1109/ICCAD.2017.8203815","url":null,"abstract":"As the speed gap of the modern processor and the off-chip main memory enlarges, on-chip cache capacity increases to sustain the performance scaling. As a result, the cache power occupies a large portion of the total power budget. STT-MRAM (Spin Transfer Torque Magnetic Memory) is proposed as a promising solution for the low power cache design due to its high integration density and ultra-low leakage. Nevertheless, the high write power and latency of STT-MRAM become new barriers for the commercialization of this emerging technology. In this paper, we investigate the thermal effect on the access performance of STT-MRAM and observe that the temperature can affect the write delay and energy significantly. Then, we explore the NUCA (Non-Uniform Cache Access) design of the CMPs (Chip-Multi-Processors)with STT-MRAM based LLC (Last Level Cache). A thermal aware data migration policy, called “Thermosiphon”, which takes advantage of the thermal property of STT-MRAM, is proposed to reduce the LLC write energy. This policy splits the LLC into different regions based on the thermal distribution and adaptively migrate write intensive data considering the temperature gradient among different thermal regions. Compared to the conventional NUCA design, our proposed design can save 22.5% write energy with negligible hardware overhead.","PeriodicalId":126686,"journal":{"name":"2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123863464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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