Pub Date : 2000-04-02DOI: 10.1109/ASYNC.2000.837010
M. Lewis, L. Brackenbury
An architecture for a low-power asynchronous DSP has been developed, for the target application of GSM (digital cellphone) chipsets. A key part of this architecture is an instruction buffer which both provides storage for prefetched instructions and performs hardware looping, This requires low latency and a reasonably fast cycle time, but must also be designed for low power. A design is presented based on a word-slice FIFO structure. This avoids the problems of input latency and power consumption associated with linear micropipeline FIFOs, and the structure lends itself reactively easily to the required looping behaviour. The latency, cycle time and power consumption for this design is compared to that of a simple micropipeline FIFO. The cycle time for the instruction buffer is around three times slower than the micropipeline FIFO. However the instruction buffer shows an energy per operation of between 48-62% of that for the (much less capable) micropipeline structure. The input to output latency with an empty FIFO is less than the micropipeline design by a factor of ten.
{"title":"An instruction buffer for a low-power DSP","authors":"M. Lewis, L. Brackenbury","doi":"10.1109/ASYNC.2000.837010","DOIUrl":"https://doi.org/10.1109/ASYNC.2000.837010","url":null,"abstract":"An architecture for a low-power asynchronous DSP has been developed, for the target application of GSM (digital cellphone) chipsets. A key part of this architecture is an instruction buffer which both provides storage for prefetched instructions and performs hardware looping, This requires low latency and a reasonably fast cycle time, but must also be designed for low power. A design is presented based on a word-slice FIFO structure. This avoids the problems of input latency and power consumption associated with linear micropipeline FIFOs, and the structure lends itself reactively easily to the required looping behaviour. The latency, cycle time and power consumption for this design is compared to that of a simple micropipeline FIFO. The cycle time for the instruction buffer is around three times slower than the micropipeline FIFO. However the instruction buffer shows an energy per operation of between 48-62% of that for the (much less capable) micropipeline structure. The input to output latency with an empty FIFO is less than the micropipeline design by a factor of ten.","PeriodicalId":127481,"journal":{"name":"Proceedings Sixth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000) (Cat. No. PR00586)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128160570","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-04-02DOI: 10.1109/ASYNC.2000.836784
I. Benko, J. Ebergen
A simple formal framework for representing safety and progress properties of concurrent systems is introduced. The framework is based on Enhanced Characteristic Functions (ECF), which lead to simple definitions of operations such as hiding and process product. Two distinct compositions are proposed: The network composition that models networks of devices, and the specification composition that enables a constraint-based approach to building specifications. A part-wise design and verification approach is proposed. This approach may avoid state explosion in the verification of implementations for constraint-based specifications.
{"title":"Composing snippets","authors":"I. Benko, J. Ebergen","doi":"10.1109/ASYNC.2000.836784","DOIUrl":"https://doi.org/10.1109/ASYNC.2000.836784","url":null,"abstract":"A simple formal framework for representing safety and progress properties of concurrent systems is introduced. The framework is based on Enhanced Characteristic Functions (ECF), which lead to simple definitions of operations such as hiding and process product. Two distinct compositions are proposed: The network composition that models networks of devices, and the specification composition that enables a constraint-based approach to building specifications. A part-wise design and verification approach is proposed. This approach may avoid state explosion in the verification of implementations for constraint-based specifications.","PeriodicalId":127481,"journal":{"name":"Proceedings Sixth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000) (Cat. No. PR00586)","volume":"129 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132778868","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-04-02DOI: 10.1109/ASYNC.2000.836962
P. Shirvani, S. Mitra, J. Ebergen, M. Roncken
This paper addresses the problem of fault collapsing in asynchronous circuits. We investigate different transistor-level implementations of some basic elements that are used in delay-insensitive asynchronous circuit designs, and analyze them in the presence of single stuck-at-faults. From this analysis, we conclude that all internal stuck-at faults which are detectable by Boolean testing, can be represented as pin-faults. This abstraction makes it possible to perform fault simulation at the logic level (network of basic elements) rather than at transistor level, which reduces the simulation time. We show how this fault model, called DUDES, can be used for fault collapsing to reduce the size of fault lists at the logic level, thereby reducing the simulation time even further. We set the basis for a formal technique for deriving equivalence relationships among the faults under consideration, using trace expressions, and illustrate that this formal technique also supports fault collapsing at the system level. This framework can be expanded to a theory of fault abstraction and collapsing for asynchronous circuits that can reduce the complexity of rest pattern generation and fault simulation.
{"title":"DUDES: a fault abstraction and collapsing framework for asynchronous circuits","authors":"P. Shirvani, S. Mitra, J. Ebergen, M. Roncken","doi":"10.1109/ASYNC.2000.836962","DOIUrl":"https://doi.org/10.1109/ASYNC.2000.836962","url":null,"abstract":"This paper addresses the problem of fault collapsing in asynchronous circuits. We investigate different transistor-level implementations of some basic elements that are used in delay-insensitive asynchronous circuit designs, and analyze them in the presence of single stuck-at-faults. From this analysis, we conclude that all internal stuck-at faults which are detectable by Boolean testing, can be represented as pin-faults. This abstraction makes it possible to perform fault simulation at the logic level (network of basic elements) rather than at transistor level, which reduces the simulation time. We show how this fault model, called DUDES, can be used for fault collapsing to reduce the size of fault lists at the logic level, thereby reducing the simulation time even further. We set the basis for a formal technique for deriving equivalence relationships among the faults under consideration, using trace expressions, and illustrate that this formal technique also supports fault collapsing at the system level. This framework can be expanded to a theory of fault abstraction and collapsing for asynchronous circuits that can reduce the complexity of rest pattern generation and fault simulation.","PeriodicalId":127481,"journal":{"name":"Proceedings Sixth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000) (Cat. No. PR00586)","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123533600","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-04-02DOI: 10.1109/ASYNC.2000.837024
Tiberiu Chelcea, S. Nowick
This paper presents several new asynchronous FIFO designs. While most existing FIFO's trade higher throughput for higher latency, our goal is to achieve very low latency while maintaining good throughput. The designs are implemented as circular arrays of cells connected to common data buses. Data items are not moved around the array once they are enqueued. Each cell's input and output behavior is dictated by the flow of two tokens around the ring: one that allows enqueuing data and one that allows dequeuing data. Two novel protocols are introduced with various degrees of parallelism, as well as four different implementations. The best simulation results, in 0.6 /spl mu/, have a latency of 1.73 ns and throughput of 454 MegaOperations/second for a 4-place FIFO.
{"title":"Low-latency asynchronous FIFO's using token rings","authors":"Tiberiu Chelcea, S. Nowick","doi":"10.1109/ASYNC.2000.837024","DOIUrl":"https://doi.org/10.1109/ASYNC.2000.837024","url":null,"abstract":"This paper presents several new asynchronous FIFO designs. While most existing FIFO's trade higher throughput for higher latency, our goal is to achieve very low latency while maintaining good throughput. The designs are implemented as circular arrays of cells connected to common data buses. Data items are not moved around the array once they are enqueued. Each cell's input and output behavior is dictated by the flow of two tokens around the ring: one that allows enqueuing data and one that allows dequeuing data. Two novel protocols are introduced with various degrees of parallelism, as well as four different implementations. The best simulation results, in 0.6 /spl mu/, have a latency of 1.73 ns and throughput of 454 MegaOperations/second for a 4-place FIFO.","PeriodicalId":127481,"journal":{"name":"Proceedings Sixth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000) (Cat. No. PR00586)","volume":"453 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132043113","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-04-02DOI: 10.1109/ASYNC.2000.836999
J. Garside, William John Bainbridge, A. Bardsley, David M. Clark, D. A. Edwards, S. Furber, D. Lloyd, S. Mohammadi, J. Pepper, S. Temple, J. V. Woods, Jianwei Liu, O. Petli
AMULET3i is the third generation asynchronous ARM-compatible microprocessor subsystem developed at the University of Manchester. It is internally modular being based around the MARBLE asynchronous on-chip bus, and is also extensible through the addition of conventional clocked synthesizable peripherals via an on-chip synchronous peripheral bus. As such it is capable of forming the core of a wide range of system-on-chip applications, bringing asynchronous design into commercial use in a flexible and easy-to-use configuration. Its performance and area are comparable with clocked equivalents, and its low-power and electromagnetic emission characteristics give it unique capabilities in appropriate applications.
{"title":"AMULET3i-an asynchronous system-on-chip","authors":"J. Garside, William John Bainbridge, A. Bardsley, David M. Clark, D. A. Edwards, S. Furber, D. Lloyd, S. Mohammadi, J. Pepper, S. Temple, J. V. Woods, Jianwei Liu, O. Petli","doi":"10.1109/ASYNC.2000.836999","DOIUrl":"https://doi.org/10.1109/ASYNC.2000.836999","url":null,"abstract":"AMULET3i is the third generation asynchronous ARM-compatible microprocessor subsystem developed at the University of Manchester. It is internally modular being based around the MARBLE asynchronous on-chip bus, and is also extensible through the addition of conventional clocked synthesizable peripherals via an on-chip synchronous peripheral bus. As such it is capable of forming the core of a wide range of system-on-chip applications, bringing asynchronous design into commercial use in a flexible and easy-to-use configuration. Its performance and area are comparable with clocked equivalents, and its low-power and electromagnetic emission characteristics give it unique capabilities in appropriate applications.","PeriodicalId":127481,"journal":{"name":"Proceedings Sixth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000) (Cat. No. PR00586)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123848315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-04-02DOI: 10.1109/ASYNC.2000.836990
A. Bystrov, D. Kinniment, A. Yakovlev
The paper presents asynchronous design solutions to the problem of Priority Arbitration which is defined in the following form. A system consists of multiple, physically concurrent, processes with a shared resource. The discipline of resource allocation is a function of parameters of the active requests, which are assigned to the requests either statically or dynamically. This function can be defined in an (arbitrary) combinatorial way (contrary to conventional, 'topological', mappings, such as that used in a daisy-chain arbiter). The proposed designs are quasi-speed-independent. Furthermore, the priority logic, in the dynamic case, has the following architectural feature: it is a tree structure in which the control flow is maximally decoupled from the data-path by means of an early propagation of the 'valid'-'invalid' signals, concurrently, with processing the priority data. This lends to significant reduction in the overall arbitration delay when the number of active requests is low.
{"title":"Priority arbiters","authors":"A. Bystrov, D. Kinniment, A. Yakovlev","doi":"10.1109/ASYNC.2000.836990","DOIUrl":"https://doi.org/10.1109/ASYNC.2000.836990","url":null,"abstract":"The paper presents asynchronous design solutions to the problem of Priority Arbitration which is defined in the following form. A system consists of multiple, physically concurrent, processes with a shared resource. The discipline of resource allocation is a function of parameters of the active requests, which are assigned to the requests either statically or dynamically. This function can be defined in an (arbitrary) combinatorial way (contrary to conventional, 'topological', mappings, such as that used in a daisy-chain arbiter). The proposed designs are quasi-speed-independent. Furthermore, the priority logic, in the dynamic case, has the following architectural feature: it is a tree structure in which the control flow is maximally decoupled from the data-path by means of an early propagation of the 'valid'-'invalid' signals, concurrently, with processing the priority data. This lends to significant reduction in the overall arbitration delay when the number of active requests is low.","PeriodicalId":127481,"journal":{"name":"Proceedings Sixth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000) (Cat. No. PR00586)","volume":"330 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122743114","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-04-02DOI: 10.1109/ASYNC.2000.837017
Montek Singh, S. Nowick
This paper introduces several new asynchronous pipeline designs which offer high throughput as well as low latency. The designs target dynamic datapaths, both dual-rail as well as single-rail. The new pipelines are latch-free and therefore are particularly well-suited for fine-grain pipelining, i.e., where each pipeline stage is only a single gate deep. The pipelines employ new control structures and protocols aimed at reducing the handshaking delay, the principal impediment to achieving high throughput in asynchronous pipelines. As a test vehicle, a 4-bit FIFO was designed using 0.6 micron technology. The results of careful HSPICE simulations of the FIFO designs are very encouraging. The dual-rail designs deliver a throughput of up to 860 million data items per second. This performance represents an improvement by a factor of 2 over a widely-used comparable approach by T.E. Williams (1991). The new single-rail designs deliver a throughput of up to 1208 million data items per second.
{"title":"High-throughput asynchronous pipelines for fine-grain dynamic datapaths","authors":"Montek Singh, S. Nowick","doi":"10.1109/ASYNC.2000.837017","DOIUrl":"https://doi.org/10.1109/ASYNC.2000.837017","url":null,"abstract":"This paper introduces several new asynchronous pipeline designs which offer high throughput as well as low latency. The designs target dynamic datapaths, both dual-rail as well as single-rail. The new pipelines are latch-free and therefore are particularly well-suited for fine-grain pipelining, i.e., where each pipeline stage is only a single gate deep. The pipelines employ new control structures and protocols aimed at reducing the handshaking delay, the principal impediment to achieving high throughput in asynchronous pipelines. As a test vehicle, a 4-bit FIFO was designed using 0.6 micron technology. The results of careful HSPICE simulations of the FIFO designs are very encouraging. The dual-rail designs deliver a throughput of up to 860 million data items per second. This performance represents an improvement by a factor of 2 over a widely-used comparable approach by T.E. Williams (1991). The new single-rail designs deliver a throughput of up to 1208 million data items per second.","PeriodicalId":127481,"journal":{"name":"Proceedings Sixth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000) (Cat. No. PR00586)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116606955","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-04-02DOI: 10.1109/ASYNC.2000.836975
H. Jacobson, E. Brunvand, G. Gopalakrishnan, P. Kudva
Designing asynchronous circuits is becoming easier as a number of design styles are making the transition from research projects to real, usable tools. However designing asynchronous "systems" is still a difficult problem. We define asynchronous systems to be medium to large digital systems whose descriptions include both datapath and control, that may involve non-trivial interface requirements, and whose control is too large to be synthesized in one large controller. ACK is a framework for designing high-performance asynchronous systems of this type. In ACK we advocate an approach that begins with procedural level descriptions of-control and datapath and results in a hybrid system that mires a variety of hardware implementation styles including burst-mode AFSMs, macromodule circuits, and programmable control. We present our views on what makes asynchronous high level system design different from lower level circuit design, motivate our ACK approach, and demonstrate using an example system design.
{"title":"High-level asynchronous system design using the ACK framework","authors":"H. Jacobson, E. Brunvand, G. Gopalakrishnan, P. Kudva","doi":"10.1109/ASYNC.2000.836975","DOIUrl":"https://doi.org/10.1109/ASYNC.2000.836975","url":null,"abstract":"Designing asynchronous circuits is becoming easier as a number of design styles are making the transition from research projects to real, usable tools. However designing asynchronous \"systems\" is still a difficult problem. We define asynchronous systems to be medium to large digital systems whose descriptions include both datapath and control, that may involve non-trivial interface requirements, and whose control is too large to be synthesized in one large controller. ACK is a framework for designing high-performance asynchronous systems of this type. In ACK we advocate an approach that begins with procedural level descriptions of-control and datapath and results in a hybrid system that mires a variety of hardware implementation styles including burst-mode AFSMs, macromodule circuits, and programmable control. We present our views on what makes asynchronous high level system design different from lower level circuit design, motivate our ACK approach, and demonstrate using an example system design.","PeriodicalId":127481,"journal":{"name":"Proceedings Sixth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000) (Cat. No. PR00586)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125109232","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-04-02DOI: 10.1109/ASYNC.2000.836774
M. A. Peña, J. Cortadella, E. Pastor, A. Kondratyev
The incorporation of timing makes circuit verification computationally expensive. This paper proposes a new approach for the verification of timed circuits. Rather than calculating the exact timed stare space, a conservative overestimation that fulfills the property under verification is derived. Timing analysis with absolute delays is efficiently performed at the level of event structures and transformed into a set of relative timing constraints. With this approach, conventional symbolic techniques for reachability analysis can be efficiently combined with timing analysis. Moreover the set of timing constraints used to prove the correctness of the circuit can also be reported for backannotation purposes. Some preliminary results obtained by a naive implementation of the approach show that systems with more than 10/sup 6/ untimed states can be verified.
{"title":"Formal verification of safety properties in timed circuits","authors":"M. A. Peña, J. Cortadella, E. Pastor, A. Kondratyev","doi":"10.1109/ASYNC.2000.836774","DOIUrl":"https://doi.org/10.1109/ASYNC.2000.836774","url":null,"abstract":"The incorporation of timing makes circuit verification computationally expensive. This paper proposes a new approach for the verification of timed circuits. Rather than calculating the exact timed stare space, a conservative overestimation that fulfills the property under verification is derived. Timing analysis with absolute delays is efficiently performed at the level of event structures and transformed into a set of relative timing constraints. With this approach, conventional symbolic techniques for reachability analysis can be efficiently combined with timing analysis. Moreover the set of timing constraints used to prove the correctness of the circuit can also be reported for backannotation purposes. Some preliminary results obtained by a naive implementation of the approach show that systems with more than 10/sup 6/ untimed states can be verified.","PeriodicalId":127481,"journal":{"name":"Proceedings Sixth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000) (Cat. No. PR00586)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121135847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-04-02DOI: 10.1109/ASYNC.2000.836983
M. Ligthart, K. Fant, Ross Smith, A. Taubin, A. Kondratyev
New design technologies rely on truly reusable IP blocks with simple means of assembly. Asynchronous methodologies could be a promising option to implement these requirements. Promotion of asynchronous design strongly depends upon the "level of service" delivered to the designer. Current asynchronous design tools require a significant re-education of designers and their capabilities are far behind synchronous commercial tools. One solution to these problems, which we advance in this paper, is to stick to a conventional design flow as closely as possible and to use commercial design tools as much as possible. The paper considers a particular subclass of asynchronous circuits (Null Convention Logic or NCL) and suggests a design flow which is completely based on commercial CAD tools. It argues about the trade-off between the simplicity of design flow and the quality of obtained implementations.
{"title":"Asynchronous design using commercial HDL synthesis tools","authors":"M. Ligthart, K. Fant, Ross Smith, A. Taubin, A. Kondratyev","doi":"10.1109/ASYNC.2000.836983","DOIUrl":"https://doi.org/10.1109/ASYNC.2000.836983","url":null,"abstract":"New design technologies rely on truly reusable IP blocks with simple means of assembly. Asynchronous methodologies could be a promising option to implement these requirements. Promotion of asynchronous design strongly depends upon the \"level of service\" delivered to the designer. Current asynchronous design tools require a significant re-education of designers and their capabilities are far behind synchronous commercial tools. One solution to these problems, which we advance in this paper, is to stick to a conventional design flow as closely as possible and to use commercial design tools as much as possible. The paper considers a particular subclass of asynchronous circuits (Null Convention Logic or NCL) and suggests a design flow which is completely based on commercial CAD tools. It argues about the trade-off between the simplicity of design flow and the quality of obtained implementations.","PeriodicalId":127481,"journal":{"name":"Proceedings Sixth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000) (Cat. No. PR00586)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114383045","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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