Pub Date : 2000-04-02DOI: 10.1109/ASYNC.2000.836786
G. Taylor, S. Moore, S. Wilcox, Peter Robinson
Self-timed systems often have to communicate with their environment through a clocked interface. For example, off-chip memory may require clocking and this can reduce the benefits of self-timed design. This paper presents the design of a delay line which may be used to control the timing of an off-chip interface. Timing accuracy is maintained by periodically recalibrating against a low frequency reference clock. The design uses two delay lines so that one can be recalibrated while the other is in use. Recalibration is undertaken once each second; power consumption is low as the calibration circuitry is dormant most of the time. A particular implementation of the design is presented which is suitable for a standard cell or FPGA technology together with experimental performance figures. The paper concludes with some remarks about possible applications in low-power synchronous design.
{"title":"An on-chip dynamically recalibrated delay line for embedded self-timed systems","authors":"G. Taylor, S. Moore, S. Wilcox, Peter Robinson","doi":"10.1109/ASYNC.2000.836786","DOIUrl":"https://doi.org/10.1109/ASYNC.2000.836786","url":null,"abstract":"Self-timed systems often have to communicate with their environment through a clocked interface. For example, off-chip memory may require clocking and this can reduce the benefits of self-timed design. This paper presents the design of a delay line which may be used to control the timing of an off-chip interface. Timing accuracy is maintained by periodically recalibrating against a low frequency reference clock. The design uses two delay lines so that one can be recalibrated while the other is in use. Recalibration is undertaken once each second; power consumption is low as the calibration circuitry is dormant most of the time. A particular implementation of the design is presented which is suitable for a standard cell or FPGA technology together with experimental performance figures. The paper concludes with some remarks about possible applications in low-power synchronous design.","PeriodicalId":127481,"journal":{"name":"Proceedings Sixth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000) (Cat. No. PR00586)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114231607","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-04-02DOI: 10.1109/ASYNC.2000.836997
Fei Xia, A. Yakovlev, D. Shang, A. Bystrov, A. Koelmans, D. Kinniment
Two asynchronous data communication mechanisms (ACMs) using self-timed circuits are presented. Mutual exclusion elements are used to concentrate potential metastability to discrete points so that it can be resolved entirely within the ACMs themselves. Self-timed circuits allow the minimisation of the interface between the reader and writer processes and the ACMs. Initial analysis shows that these VLSI solutions are more robust with regard to steering logic metastability, and can potentially run faster than solutions under fundamental mode assumptions. They are therefore more suitable for use in on-chip multiprocessing systems.
{"title":"Asynchronous communication mechanisms using self-timed circuits","authors":"Fei Xia, A. Yakovlev, D. Shang, A. Bystrov, A. Koelmans, D. Kinniment","doi":"10.1109/ASYNC.2000.836997","DOIUrl":"https://doi.org/10.1109/ASYNC.2000.836997","url":null,"abstract":"Two asynchronous data communication mechanisms (ACMs) using self-timed circuits are presented. Mutual exclusion elements are used to concentrate potential metastability to discrete points so that it can be resolved entirely within the ACMs themselves. Self-timed circuits allow the minimisation of the interface between the reader and writer processes and the ACMs. Initial analysis shows that these VLSI solutions are more robust with regard to steering logic metastability, and can potentially run faster than solutions under fundamental mode assumptions. They are therefore more suitable for use in on-chip multiprocessing systems.","PeriodicalId":127481,"journal":{"name":"Proceedings Sixth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000) (Cat. No. PR00586)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116631192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-04-02DOI: 10.1109/ASYNC.2000.836791
J. Muttersbach, T. Villiger, W. Fichtner
In this paper we describe a complete design methodology for a globally asynchronous on-chip communication network connecting both locally-synchronous and asynchronous modules. Synchronous modules are equipped with asynchronous wrappers which adapt their interfaces to the self-timed environment and prevent metastability. These wrappers are assembled from a concise library of predesigned technology-independent elements and provide high-speed data transfer. We confirmed the validity of our concept by applying it to an ASIC design implementing the Safer crypto-algorithm.
{"title":"Practical design of globally-asynchronous locally-synchronous systems","authors":"J. Muttersbach, T. Villiger, W. Fichtner","doi":"10.1109/ASYNC.2000.836791","DOIUrl":"https://doi.org/10.1109/ASYNC.2000.836791","url":null,"abstract":"In this paper we describe a complete design methodology for a globally asynchronous on-chip communication network connecting both locally-synchronous and asynchronous modules. Synchronous modules are equipped with asynchronous wrappers which adapt their interfaces to the self-timed environment and prevent metastability. These wrappers are assembled from a concise library of predesigned technology-independent elements and provide high-speed data transfer. We confirmed the validity of our concept by applying it to an ASIC design implementing the Safer crypto-algorithm.","PeriodicalId":127481,"journal":{"name":"Proceedings Sixth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000) (Cat. No. PR00586)","volume":"128 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123251708","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-04-02DOI: 10.1109/ASYNC.2000.836995
C. E. Molnar, I. W. Jones
This paper brings together a selection of creative circuit designs and ideas that Charles Molnar devised while working at Sun Microsystems Laboratories. The circuits offer fast implementations of functions that were severe speed bottlenecks in our existing systems. Charlie strongly believed that reliable and very fast circuit module implementations must make use of local delay constraints, and that the interfaces between these modules can then employ more robust and delay-insensitive signaling protocols. These circuit designs provided us with: an unusual 2-phase arbiter known as the propeller arbiter; a method of using arbiters to measure on-chip delays very precisely; and three versions of a latch control circuit, known as a Charlie Box.
{"title":"Simple circuits that work for complicated reasons","authors":"C. E. Molnar, I. W. Jones","doi":"10.1109/ASYNC.2000.836995","DOIUrl":"https://doi.org/10.1109/ASYNC.2000.836995","url":null,"abstract":"This paper brings together a selection of creative circuit designs and ideas that Charles Molnar devised while working at Sun Microsystems Laboratories. The circuits offer fast implementations of functions that were severe speed bottlenecks in our existing systems. Charlie strongly believed that reliable and very fast circuit module implementations must make use of local delay constraints, and that the interfaces between these modules can then employ more robust and delay-insensitive signaling protocols. These circuit designs provided us with: an unusual 2-phase arbiter known as the propeller arbiter; a method of using arbiters to measure on-chip delays very precisely; and three versions of a latch control circuit, known as a Charlie Box.","PeriodicalId":127481,"journal":{"name":"Proceedings Sixth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000) (Cat. No. PR00586)","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115734163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-04-02DOI: 10.1109/ASYNC.2000.836779
W. C. Mallon
Delay-insensitive specifications model communicating processes that are embedded in a medium that introduces arbitrary and varying delays on the communication channels. In this paper we study transformations of such specifications. The transformations we study are directed. They are either contracting or expanding. The former are useful when trying to improve specifications, the latter when trying to find implementations. The theory we develop is inspired by transformations based on handshake protocols. We show how an implementation of such a protocol can be derived. We also show how the transformations can help when analyzing specifications containing unavoidable nondeterminism, which is closely related to unavoidable metastability.
{"title":"On directed transformations of delay-insensitive specifications, alternations and dynamic nondeterminism","authors":"W. C. Mallon","doi":"10.1109/ASYNC.2000.836779","DOIUrl":"https://doi.org/10.1109/ASYNC.2000.836779","url":null,"abstract":"Delay-insensitive specifications model communicating processes that are embedded in a medium that introduces arbitrary and varying delays on the communication channels. In this paper we study transformations of such specifications. The transformations we study are directed. They are either contracting or expanding. The former are useful when trying to improve specifications, the latter when trying to find implementations. The theory we develop is inspired by transformations based on handshake protocols. We show how an implementation of such a protocol can be derived. We also show how the transformations can help when analyzing specifications containing unavoidable nondeterminism, which is closely related to unavoidable metastability.","PeriodicalId":127481,"journal":{"name":"Proceedings Sixth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000) (Cat. No. PR00586)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124752480","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-04-02DOI: 10.1109/ASYNC.2000.836798
M. Roncken, K. Stevens, R. Pendurkar, Shai Rotem, P. P. Chaudhuri
This paper presents a case study in low-cost noninvasive Built-in Self Test (BIST) for RAPPID, a large-scale 120,000-transistor asynchronous version of the Pentium(R) Pro Instruction Length Decoded which runs at 3.6 GHz. RAPPID uses a synchronous 0.25 micron CMOS library for static and domino logic, and has no Design-for-Test hooks other than some debug features. We explore the use of Cellular Automata (CA) for on-chip test pattern generation and response evaluation. More specifically, we look for fast ways to tune the CA-BIST to the RAPPID design, rather than using pseudo-random testing. The metric for tuning the CA-BIST pattern generation is based on an abstract hardware description model of the instruction length decodes which is independent of implementation details, and hence also independent of the asynchronous circuit style. Our CA-BIST solution uses a novel bootstrap procedure for generating the test patterns, which give complete coverage for this metric, and cover 94% of the testable stuck-at faults for the actual design at switch level. Analysis of the undetected and untestable faults shows that the same fault effects can be expected for a similar clocked circuit. This is encouraging evidence that testability is no excuse to avoid asynchronous design techniques in addition to high-performance synchronous solutions.
{"title":"CA-BIST for asynchronous circuits: a case study on the RAPPID asynchronous instruction length decoder","authors":"M. Roncken, K. Stevens, R. Pendurkar, Shai Rotem, P. P. Chaudhuri","doi":"10.1109/ASYNC.2000.836798","DOIUrl":"https://doi.org/10.1109/ASYNC.2000.836798","url":null,"abstract":"This paper presents a case study in low-cost noninvasive Built-in Self Test (BIST) for RAPPID, a large-scale 120,000-transistor asynchronous version of the Pentium(R) Pro Instruction Length Decoded which runs at 3.6 GHz. RAPPID uses a synchronous 0.25 micron CMOS library for static and domino logic, and has no Design-for-Test hooks other than some debug features. We explore the use of Cellular Automata (CA) for on-chip test pattern generation and response evaluation. More specifically, we look for fast ways to tune the CA-BIST to the RAPPID design, rather than using pseudo-random testing. The metric for tuning the CA-BIST pattern generation is based on an abstract hardware description model of the instruction length decodes which is independent of implementation details, and hence also independent of the asynchronous circuit style. Our CA-BIST solution uses a novel bootstrap procedure for generating the test patterns, which give complete coverage for this metric, and cover 94% of the testable stuck-at faults for the actual design at switch level. Analysis of the undetected and untestable faults shows that the same fault effects can be expected for a similar clocked circuit. This is encouraging evidence that testability is no excuse to avoid asynchronous design techniques in addition to high-performance synchronous solutions.","PeriodicalId":127481,"journal":{"name":"Proceedings Sixth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000) (Cat. No. PR00586)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121899456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-04-02DOI: 10.1109/ASYNC.2000.836785
J. Kessels, G. D. Besten, A. Peeters, Torsten Kramer, Volker Timm
We have designed an asynchronous chip for contactless smart cards. Asynchronous circuits have two power properties that make them very suitable for contactless devices: low average power and small current peaks. The fact that asynchronous circuits operate over a wide range of the supply voltage, while automatically adapting their speed has been used to obtain a circuit that is very resilient to voltage drops while giving maximum performance for the power being received. The asynchronous circuit has been built, tested and evaluated and the results were so convincing that, based on the circuits presented, a product is being designed.
{"title":"Applying asynchronous circuits in contactless smart cards","authors":"J. Kessels, G. D. Besten, A. Peeters, Torsten Kramer, Volker Timm","doi":"10.1109/ASYNC.2000.836785","DOIUrl":"https://doi.org/10.1109/ASYNC.2000.836785","url":null,"abstract":"We have designed an asynchronous chip for contactless smart cards. Asynchronous circuits have two power properties that make them very suitable for contactless devices: low average power and small current peaks. The fact that asynchronous circuits operate over a wide range of the supply voltage, while automatically adapting their speed has been used to obtain a circuit that is very resilient to voltage drops while giving maximum performance for the power being received. The asynchronous circuit has been built, tested and evaluated and the results were so convincing that, based on the circuits presented, a product is being designed.","PeriodicalId":127481,"journal":{"name":"Proceedings Sixth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000) (Cat. No. PR00586)","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121957193","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-04-02DOI: 10.1109/ASYNC.2000.836976
Euiseok Kim, Jeong-Gun Lee, Dong-Ik Lee
As an asynchronous design style becomes popular, the request for asynchronous high-level synthesis (AHLS) tools is increasing continuously. In this paper, a method, so called process-oriented method, which generates distributed asynchronous control circuits automatically in a hierarchical and systematic manner is suggested as part of an AHLS tool. Experimental results show that the suggested method is efficient in the aspects of area and performance of derived control circuits.
{"title":"Automatic process-oriented control circuit generation for asynchronous high-level synthesis","authors":"Euiseok Kim, Jeong-Gun Lee, Dong-Ik Lee","doi":"10.1109/ASYNC.2000.836976","DOIUrl":"https://doi.org/10.1109/ASYNC.2000.836976","url":null,"abstract":"As an asynchronous design style becomes popular, the request for asynchronous high-level synthesis (AHLS) tools is increasing continuously. In this paper, a method, so called process-oriented method, which generates distributed asynchronous control circuits automatically in a hierarchical and systematic manner is suggested as part of an AHLS tool. Experimental results show that the suggested method is efficient in the aspects of area and performance of derived control circuits.","PeriodicalId":127481,"journal":{"name":"Proceedings Sixth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000) (Cat. No. PR00586)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114145982","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-04-02DOI: 10.1109/ASYNC.2000.836967
I. Blunno, L. Lavagno
This paper presents a compiler from a standard Hardware Description Language (Verilog HDL) to an asynchronous Control Unit and a synchronous Data Path. The Control Unit, specified as a Signal Transition Graph, can be implemented using research-oriented asynchronous synthesis tools. The Data Path, specified using the Synthesizable Subset of Verilog, can be implemented using state-of-the-art commercial synchronous synthesis tools. Our compiler integrates in a fully automated manner source parsing, control/data splitting, managing the design and inserting matched delays for data bundling constraints. It can be used to produce asynchronous designs in an Application Specific Integrated Circuit design style, since the result is a netlist of standard cells ready for physical design. We describe a simple example of compilation and its results, and we discuss some outstanding issues in the domain of asynchronous Control Unit synthesis.
{"title":"Automated synthesis of micro-pipelines from behavioral Verilog HDL","authors":"I. Blunno, L. Lavagno","doi":"10.1109/ASYNC.2000.836967","DOIUrl":"https://doi.org/10.1109/ASYNC.2000.836967","url":null,"abstract":"This paper presents a compiler from a standard Hardware Description Language (Verilog HDL) to an asynchronous Control Unit and a synchronous Data Path. The Control Unit, specified as a Signal Transition Graph, can be implemented using research-oriented asynchronous synthesis tools. The Data Path, specified using the Synthesizable Subset of Verilog, can be implemented using state-of-the-art commercial synchronous synthesis tools. Our compiler integrates in a fully automated manner source parsing, control/data splitting, managing the design and inserting matched delays for data bundling constraints. It can be used to produce asynchronous designs in an Application Specific Integrated Circuit design style, since the result is a netlist of standard cells ready for physical design. We describe a simple example of compilation and its results, and we discuss some outstanding issues in the domain of asynchronous Control Unit synthesis.","PeriodicalId":127481,"journal":{"name":"Proceedings Sixth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000) (Cat. No. PR00586)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125444978","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-04-02DOI: 10.1109/ASYNC.2000.837014
O. Hauck, A. Katoch, S. Huss
This paper presents VLSI system design using asynchronous wave pipelines (AWPs) with a public key crypto chip as an example. The design challenges imposed by the crypto chip include very wide data paths, bit-level wave pipelining, hierarchical control resulting in different frequency domains, and interfacing synchronous registers with asynchronous controllers and data paths. The timing analysis indicates that AWPs operate more safely than synchronous wave pipelines. At the circuit level, SRCMOS is shown to be superior to previously proposed logic styles for wave pipelining. The same circuit style applies for both data path and control. Following some mathematics and cryptography background, the architecture of the chip is detailed whose outstanding feature is a wave pipelined Massey-Omura finite field multiplier. Simulations from layout of key circuits running at a rate of 1.5 GHz in a 0.35 /spl mu/m CMOS process demonstrate the feasibility of the AWP concept.
{"title":"VLSI system design using asynchronous wave pipelines: a 0.35 /spl mu/m CMOS 1.5 GHz elliptic curve public key cryptosystem chip","authors":"O. Hauck, A. Katoch, S. Huss","doi":"10.1109/ASYNC.2000.837014","DOIUrl":"https://doi.org/10.1109/ASYNC.2000.837014","url":null,"abstract":"This paper presents VLSI system design using asynchronous wave pipelines (AWPs) with a public key crypto chip as an example. The design challenges imposed by the crypto chip include very wide data paths, bit-level wave pipelining, hierarchical control resulting in different frequency domains, and interfacing synchronous registers with asynchronous controllers and data paths. The timing analysis indicates that AWPs operate more safely than synchronous wave pipelines. At the circuit level, SRCMOS is shown to be superior to previously proposed logic styles for wave pipelining. The same circuit style applies for both data path and control. Following some mathematics and cryptography background, the architecture of the chip is detailed whose outstanding feature is a wave pipelined Massey-Omura finite field multiplier. Simulations from layout of key circuits running at a rate of 1.5 GHz in a 0.35 /spl mu/m CMOS process demonstrate the feasibility of the AWP concept.","PeriodicalId":127481,"journal":{"name":"Proceedings Sixth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000) (Cat. No. PR00586)","volume":"138 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124359756","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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